Abstract The development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those operations demanding stringent security levels but also many daily use consumer applications request the existence of computational platforms in charge of recognizing the identity of one individual based on the analysis of his/her physiological and/or behavioural characteristics. The state of the art points out two main open problems in the implementation of such applications: on the one hand, the needed reliability improvement in terms of recognition accuracy, overall security and real-time performances; and on the other hand, the cost reduction of those physical platforms in charge of the processing. This work aims at finding the proper system architecture able to address those limitations of current personal recognition applications. Embedded system solutions based on hardware-software co-design techniques and programmable (and run-time reconfigurable) logic devices under FPGAs or SOPCs is proven to be an efficient alternative to those existing multiprocessor systems based on HPCs, GPUs or PC platforms in the development of that kind of high-performance applications at low cost / El desenvolupament de sistemes automàtics de reconeixement personal basats en tècniques biomètriques esdevé una realitat en l’era tecnològica actual. No només aquelles operacions que exigeixen un elevat nivell de seguretat sinó també moltes aplicacions quotidianes demanen l’existència de plataformes computacionals encarregades de reconèixer la identitat d’un individu a partir de l’anàlisi de les seves característiques fisiològiques i/o comportamentals. L’estat de l’art de la tècnica identifica dues limitacions importants en la implementació d’aquest tipus d’aplicacions: per una banda, és necessària la millora de la fiabilitat d’aquests sistemes en termes de precisió en el procés de reconeixement personal, seguretat i execució en temps real; i per altra banda, és necessari reduir notablement el cost dels sistemes electrònics encarregats del processat biomètric. Aquest treball té per objectiu la cerca de l’arquitectura adequada a nivell de sistema que permeti fer front a les limitacions de les aplicacions de reconeixement personal actuals. Es demostra que la proposta de sistemes empotrats basats en tècniques de codisseny hardware-software i dispositius lògics programables (i reconfigurables en temps d’execució) sobre FPGAs o SOPCs resulta ser una alternativa eficient en front d’aquells sistemes multiprocessadors existents basats en HPCs, GPUs o plataformes PC per al desenvolupament d’aquests tipus d’aplicacions que requereixen un alt nivell de prestacions a baix cost. / El desarrollo de sistemas automáticos de reconocimiento personal basados en técnicas biométricas se ha convertido en una realidad en la era tecnológica actual. No tan solo aquellas operaciones que requieren un alto nivel de seguridad sino también muchas otras aplicaciones cotidianas exigen la existencia de plataformas computacionales encargadas de verificar la identidad de un individuo a partir del análisis de sus características fisiológicas y/o comportamentales. El estado del arte de la técnica identifica dos limitaciones importantes en la implementación de este tipo de aplicaciones: por un lado, es necesario mejorar la fiabilidad que presentan estos sistemas en términos de precisión en el proceso de reconocimiento personal, seguridad y ejecución en tiempo real; y por otro lado, es necesario reducir notablemente el coste de los sistemas electrónicos encargados de dicho procesado biométrico. Este trabajo tiene por objetivo la búsqueda de aquella arquitectura adecuada a nivel de sistema que permita hacer frente a las limitaciones de los sistemas de reconocimiento personal actuales. Se demuestra que la propuesta basada en sistemas embebidos implementados mediante técnicas de codiseño hardware-software y dispositivos lógicos programables (y reconfigurables en tiempo de ejecución) sobre FPGAs o SOPCs resulta ser una alternativa eficiente frente a aquellos sistemas multiprocesador actuales basados en HPCs, GPUs o plataformas PC en el ámbito del desarrollo de aplicaciones que demandan un alto nivel de prestaciones a bajo coste

This project will create a navigation system based on dead reckoning using anaccelerometer and a magnetometer. There have previously been several studiesmade on navigation with accelerometers, magnetometers (electronic compass) andgyros. With these three components it is possible to do positioning and differentkinds of movement analyses. There are several methods for detection of movementand calculation of position. To achieve greater accuracy in these applications,gyros are often used. Compared to magnetometers and accelerometer gyrosconsumes a lot of power. In an embedded system with limited power suppliesfrom a battery this may be unacceptable. In this project a positioning system without a gyro have been developedand evaluated. Is this possible to do, and what accuracy is possible to achieve arequestions asked.Algorithms have been developed and tested in MATLAB. The project is based ona device called a BeeBadge, part of the project will be to transfer the developedalgorithms from MATLAB to C-code. Optimizations of the code will be performeddue to the constraints in the memory and speed of the microcontroller on theBeeBadge.

With the popularity of Smart Handset devices, much more discussion of the design and development of embedded systems, some of embedded system problems such as the stability and efficiency of the device, the easy-operating interface design and a variety of application design are more and more important. Application development in the embedded systems is often limited by the system resource such as memory. Compared with common computer systems, embedded system got very limited memory. Therefore, program development in the embedded systems often need to consider the problem of insufficient memory, and program design must also avoid using too large number of memory allocation to cause the program take up a lot of system memory, affecting the system operation, causing the system hazard. Java is one of the common programming languages using in the embedded system development. Based on the high portability, Java programs can easily port to another system environment by using the Java virtual machine. However, the Java programming is also restricted, such as Java programming is not allowed to access memory space direct, and the memory allocation and release are all controlled by the system, rather than users. The purpose of the research is to design a set of Java programming tools. It can be applied to Android Dalvik virtual machine, which is responsible for operating the memory allocation and release, to allow users to control memory so as to ensure that memory can be reused to avoid the system hazard caused by the system memory leak problem.

Positioning and navigation systems play an important role in our daily life, but now most of positioning systems were confined in outdoor environments, most of which were used on transportation. Therefore, the goal of this thesis is to develop a Pedestrian Dead Reckoning System (PDRS), which can not only be used to solve a problem of GPS out-of-lock, but also be used in the field of indoor positioning. In dangerous environments, such as the scene of a fire, when the rescue personnel have an accident on himself or discover a wounded who need to be salvaged, if the rescue personnel who has configured the PDRS, then the other rescue personnel can assist them immediately. In the part of hardware system, we used embedded system to be the primary part of the entire system, the embedded system has the characters of low power consumption and portability. Therefore, we chose the TI OMAP35x EVM platform to be our primary system of PDRS. In order to get the information of pedestrian, we also need the Inertial Measurement Unit (IMU) and Compass to provide the information of acceleration and heading for PDRS. To achieve the function of remote monitoring, we used wireless transmission module to send data of sensors to OMAP35x EVM. Finally, the most important function that we must accomplish in this thesis is to use OMAP35x EVM to build a real-time PDRS. In the part of software system, we use Linux OS and Qt SDK to build the software system of PDRS in this thesis. In the part of algorithm, we use step detection, step length estimation and dead reckoning method to construct the algorithm of PDRS in this thesis.

Taipower Company has already completed the installation of the Outage Management System (OMS) in all service districts. The attributes of all distribution equipments and customers have been included in the computerized mapping system. However, the phasing attributes of distribution transformers are not very accurate in the database because they are very difficult to be identified for the distribution systems. The phase information of transformers in the OMS database is often inconsistent with the actual service phase, which deteriorates the performance of distribution system analysis, planning, and operation of Taipower distribution systems. The objective of this thesis is to develop an innovative Phasor Measurement Unit (PMU) to support the phasing identification of distribution transformers in a very effective way. The proposed PMU is used to measure the low voltage signal at the secondary side of transformers to prevent the survey personnel from safety problem. With the measured phases information of distribution transformers stored in the embedded system, the attributes of transformer phases in OMS can be updated to improve the accuracy of database. For the underground distribution systems, it is very difficult to receive the 1PPS signal of GPS system for timing synchronous to support the proposed transformer phasing measurement because all transformers are located at the building basement. This thesis proposes a timing synchronous module by using the Temperature Compensated Crystal Oscillator, TCXO to maintain the timing accuracy with high precision. Before executing the phasing measurement, this module is calibrated using the GPS 1PPS signal with fuzzy control calibration algorithm. It is found that the proposed PMU module can maintain the timing synchronous with 6˚, during two hours time period which will support the transformer phasing measurement by providing the reference timing synchronous even without the GPS 1PPS signal.

Along with the development of localization and navigation technologies, the Global Positioning System (GPS) plays an important role in our daily life, but it is confined in outdoor environments. The technology of human localization has been developed in recent years. This technology utilizes sensors to determine the movement of human and measure the distance of walking, which is not only used to solve the problem of GPS out-of-lock, but also used for the indoor localization. This thesis describes a human step-length recognition and real-time localization base on an embedded system. The goal of this system is to develop a gait pattern classification and pedestrian dead reckoning (PDR) method for human localization. Through the information of an Inertial Measurement Unit (IMU) and two force sensors mounted on a shoe, the wireless transmission module is used to send data of sensors to an embedded platform. Then the functions of step detection, step length estimation and gait pattern recognition can be achieved. According to coordinate transformation and the ZUPT algorithm, the accumulated error of velocity can be corrected. The dead reckoning method is used to obtain the information of location. Finally, the information of human location and gait patterns is sent to the Android system for remote monitoring.

¡@¡@An embedded system has improved quickly in recent years and now functions like a small computer. Equipped with operating systems (OS), graphic user interfaces (GUI), and software developed for various platforms, an embedded system provides users with services more powerful and friendlier than ever. Qt/Embedded and OpenGL ES are an OS and a GUI developed for embedded systems. In this thesis, We integrated Qt/Embedded with OpenGL ES on a Versatile PB 92EJ-S and conducted various tests. ¡@¡@The Versatile PB 92EJ-S was equipped with ARM926EJ-S, an onboard chip capable of performing VFP9 vector floating operation. However, not all embedded systems are powered by a floating coprocessor. To make the test results applicable to all systems, We performed only fixed-point operations, a practice also improving the overall performance. In addition, to provide communications between OpenGL ES and Windows and interfaces for OpenGL ES to draw, We implemented EGL, a platform interface layer defined in OpenGL ES. Furthermore, We developed GLUT ES, a modification of GLUT, to make the embedded system compatible with Windows of different versions. Finally, We benchmarked the platform with programs developed by GLUT ES interfaces and OpenGL ES.

In this paper, we proposed a hardware development environment of the Embedded system to reduce the complexity of the Embedded system archeitecture, fit the varied specification, decrease the difficulties and time consuming on hardware integration, and short the life period of products. According to the On-Cihp Bus platform, we can utilize certain modules repeatly and recofigure the parameters flexibily to integrate the necessary system hardware and complete the system verification rapidly that we can achieve the time to market. In this thesis, we discuss architecture of hardware platform and the technique of system integration. Further more; we introduce the concept of VRM (Verification Reuse Methodology) on the system verification that reduces the verification time of system.

<p>The recent increase in performance of embedded processors has enabled the use of computationally heavy asymmetric cryptography in small and power efficient embedded systems. The goal of this thesis is to analyze whether it is possible to use this type of cryptography to enhance the security in access systems.</p><p>This report contains a literature study of the complications related to access systems and their functionality. Also a basic introduction to cryptography is included.</p><p>Several cryptographic algorithms were implemented using the public library LibTomCrypt and benchmarked on an ARM7-processor platform. The asymmetric coding schemes were ECC and RSA. The tested symmetric algorithms included AES, 3DES and Twofish among others. The benchmark considered both codesize and speed of the algorithms.</p><p>The two asymmetric algorithms, ECC and RSA, are possible to be used in an ARM7 based access system. Although, both technologies can be configured to finish the calculations within a reasonable time-frame of 10 Sec, ECC archives a higher security level for the same execution time. Therefore, an implementation of ECC would be preferable since it is faster and requires less resources. Some further suggestions of improvements to the implementation is discussed in the final chapters.</p>

Embedded environment imposes severe constraints of system resources on embedded applications. Performance, memory footprint, and power consumption are critical factors for embedded applications. Meanwhile, the data in embedded applications demonstrate unique properties. More specifically, narrow width data are data representable in considerably fewer bits than in one word, which nevertheless occupy an entire register or memory word and streaming data are the input data processed by an application sequentially, which stay in the system for a short duration and thus exhibit little data locality. Narrow width and streaming data affect the efficiency of register, cache, and memory and must be taken into account when optimizing for performance, memory footprint, and power consumption.This dissertation proposes methods to efficiently handle narrow width and streaming data in embedded applications. Quantitative measurements of narrow width and streaming data are performed to provide guidance for optimizations. Novel architectural features and associated compiler algorithms are developed. To efficiently handle narrow width data in registers, two register allocation schemes are proposed for the ARM processor to allocate two narrow width variables to one register. A static scheme exploits maximum bitwidth. A speculative scheme further exploits dynamic bitwidth. Both result in reduced spill cost and performance improvement. To efficiently handle narrow width data in memory, a memory layout method is proposed to coalesce multiple narrow width data in one memory location in a DSP processor, leading to fewer explicit address calculations. This method improves performance and shrinks memory footprint. To efficiently handle streaming data in network processor, two cache mechanisms are proposed to enable the reuse of data and computation. The slack created is further transformed into reduction in energy consumption through a fetch gating mechanism.