Today, heterogeneous computing has truly reshaped the way scientists think and approach high-performance computing (HPC). Hardware accelerators such as general-purpose graphics processing units (GPUs) and Intel Many Integrated Core (MIC) architecture continue to make in-roads in accelerating large-scale scientific applications. These advancements, however, introduce new sets of challenges to the scientific community such as: selection of best processor for an application, effective performance optimization strategies, maintaining performance portability across architectures etc. In this thesis, we present our techniques and approach to address some of these significant issues. Firstly, we present a fully automated approach to project the relative performance of an OpenCL program over different GPUs. Performance projections can be made within a small amount of time, and the projection overhead stays relatively constant with the input data size. As a result, the technique can help runtime tools make dynamic decisions about which GPU would run faster for a given kernel. Usage cases of this technique include scheduling or migrating GPU workloads over a heterogeneous cluster with different types of GPUs. We then present our approach to accelerate a seismology modeling application that is based on the finite difference method (FDM), using MPI and CUDA over a hybrid CPU+GPU cluster. We describe the generic computational complexities involved in porting such applications to the GPUs and present our strategy of efficient performance optimization and characterization. We also show how performance modeling can be used to reason and drive the hardware-specific optimizations on the GPU. The performance evaluation of our approach delivers a maximum speedup of 23-fold with a single GPU and 33-fold with dual GPUs per node over the serial version of the application, which in turn results in a many-fold speedup when coupled with the MPI distribution of the computation across the cluster. We also study the efficacy of GPU-integrated MPI, with MPI-ACC as an example implementation, in a seismology modeling application and discuss the lessons learned. / Master of Science

Video communication is an important application in wireless ad hoc network environment. Although current off-the-shelf video communication software would work for ad hoc network operating under stable conditions (e.g., extremely low link and node failures), video communications for ad hoc network operating under extreme conditions remain a challenging problem. This is because traditional video codec, either single steam or layered video, requires at least one relatively stable path between source and destination nodes. Recent advances in multiple description (MD) video coding have opened up new possibilities to offer video communications over ad hoc networks. In this thesis, we perform a systematic study on MD video for ad hoc networks. The theoretical foundation of this research is based on an application-centric approach to formulate a cross-layer multipath routing problem that minimizes the application layer video distortion. The solution procedure to this complex optimization problem is based on the so-called Genetic Algorithm (GA). The theoretical results have been documented in [7] and will be reviewed in Chapter 2. Although the theoretical foundation for MD video over dynamic ad hoc networks has been laid, there remains a lot of skepticisms in the research community on whether such cross-layer optimal routing can be implemented in practice. To fill this gap, this thesis is devoted to the experimental research (or proof-of-concept) for the work in [7]. Our approach is to design and implement an emulation testbed where we can actually implement the ideas and algorithms proposed in [7] in a controlled laboratory setting. The highlights of our experimental research include: 1. A testbed that emulates three properties of a wireless ad hoc network: topology, link success probability, and link bandwidth; 2. A source routing implementation that can easily support comparative study between the proposed GA-based routing with other routing schemes under different network conditions; 3. A modified H.263+ video codec that employs Unequal Error Protection (UEP) approach to generate MD video; 4. Implementation of three experiments that • compared the GA-based routing with existing technologies (NetMeeting video conferencing plus AODV routing); • compared our GA-based routing with network-centric routing schemes (two-disjoint paths routing); • proved that our approach has great potential in supporting video communications in wireless ad hoc networks. 5. Experimental results that show the proposed cross-layer optimization significantly outperforms the current off-the-shelf technologies, and that the proposed cross-layer optimization provides much better performance than network-centric routing schemes in supporting routing of MD video. In summary, the experimental research in this thesis has demonstrated that a cross-layer multipath routing algorithm can be practically implemented in a dynamic ad hoc network to support video communications. / Master of Science

L’objet de cette thèse est l’étude d’un groupe d’ivoires, trouvés dans plusieurs sites du Proche-Orient ancien, connu sous le nom d’ivoires égyptisants. Nous avons examiné les différentes interprétations possibles, quant à l’origine et la signification de ces objets, en examinant les sources bibliographiques à notre disposition. Sans proposer une révision fondamentale des hypothèses présentées jusqu’à aujourd’hui, ce travail, en se fondant sur des témoignages archéologiques, iconographiques et textuels, essaye de mettre en évidence les différentes voies de transmission des motifs iconographiques égyptiens dans le répertoire iconographique du Proche-Orient ancien et cela notamment dans l’art de l’ivoire. Après une discussion générale sur l’ivoire et sur les différentes sources dont disposaient les artistes de l’antiquité, nous sommes arrivés à la conclusion que les ivoires égyptisants étaient le produit des artistes locaux du Proche-Orient ancien, qui se sont inspirés de l’art égyptien,soit à travers les échanges commerciaux, soit à travers les objets égyptiens trouvés dans plusieurs sites du Levant. Quant à l’interprétation de ces motifs, nous pensons que les artistes du Proche-Orient ancien ont représenté les objets de culte égyptien sans forcément comprendre la signification religieuse ou symbolique que ces motifs représentaient pour les Égyptiens. Ceci dit, ces artistes n’ignoraient pas complètement le message général attaché à ces objets ; ils ont adopté et adapté l’iconographie égyptienne en suivant les conventions de l’art proche-Oriental selon leur besoin du moment. / The purpose of this thesis is the study of a group of ivories found in several sites of the ancient Near East, known as egyptianizing ivories. We studied various interpretations as to the origin and meaning of these objects by consulting the bibliographic sources at our disposal. Without proposing a fundamental revision of the hypotheses made so far, this study, based on archaeological, iconographical and textual evidence, tries to highlight the different routes of transmission of the Egyptian iconographic motifs into the iconographical repertoire of the Ancient Near East, with a special emphasis on the art of ivory carving. After a general discussion on the ivory and the various sources available to the artists of antiquity, we concluded that the egyptianizing ivories were the product of local artists of the ancient Near East, that were inspired by the Egyptian art, either through trade or through the Egyptian artefacts found at several sites in the Levant. As for the interpretation of these motifs, we believe that the artists of the Ancient Near East have represented Egyptian cult objects without necessarily understanding the religious or symbolic meaning that these motifs had for the Egyptians. That said, these artists were not completely unaware of the general message attached to these objects; they have adopted and adapted the Egyptian iconography by following the conventions of the ancient neareastern art according to their needs.

The heterogenous nature and the demand for extensive parallel processing in modern applications have resulted in widespread use of Multicore System-on-Chip (SoC) architectures. The emerging Network-on-Chip (NoC) architecture provides an energy-efficient and scalable communication solution for Multicore SoCs, serving as a powerful replacement for traditional bus-based solutions. The key to successful realization of such architectures is a flexible, fast and robust emulation platform for fast design space exploration. In this research, we present the design and evaluation of a highly configurable NoC used in AcENoCs (Accelerated Emulation platform for NoCs), a flexible and cycle accurate field programmable gate array (FPGA) emulation platform for validating NoC architectures. Along with the implementation details, we also discuss the various design optimizations and tradeoffs, and assess the performance improvements of AcENoCs over existing simulators and emulators. We design a hardware library consisting of routers and links using verilog hardware description language (HDL). The router is parameterized and has a configurable number of physical ports, virtual channels (VCs) and pipeline depth. A packet switched NoC is constructed by connecting the routers in either 2D-Mesh or 2D-Torus topology. The NoC is integrated in the AcENoCs platform and prototyped on Xilinx Virtex-5 FPGA. The NoC was evaluated under various synthetic and realistic workloads generated by AcENoCs' traffic generators implemented on the Xilinx MicroBlaze embedded processor. In order to validate the NoC design, performance metrics like average latency and throughput were measured and compared against the results obtained using standard network simulators. FPGA implementation of the NoC using Xilinx tools indicated a 76% LUT utilization for a 5x5 2D-Mesh network. A VC allocator was found to be the single largest consumer of hardware resources within a router. The router design synthesized at a frequency of 135MHz, 124MHz and 109MHz for 3-port, 4-port and 5-port configurations, respectively. The operational frequency of the router in the AcENoCs environment was limited only by the software execution latency even though the hardware itself could be clocked at a much higher rate. An AcENoCs emulator showed speedup improvements of 10000-12000X over HDL simulators and 5-15X over software simulators, without sacrificing cycle accuracy.

The evolution of computer communications and the Internet has led to the emergence of a large number of communication technologies with widely different capabilities and characteristics. While this multitude of technologies provides a wide array of possibilities it also creates a complex and heterogeneous environment for higher-layer communication protocols. Specific link technologies, as well as overall network heterogeneity, can hamper user-perceived performance or impede end-to-end throughput. In this thesis we examine two transport layer centered approaches to improve performance. The first approach addresses the decrease in user satisfaction that occurs when web waiting times become too long. Increased transport layer flexibility with regards to reliability, together with error-resilient image coding, is used to enable a new trade-off. The user is given the possibility to reduce waiting times, at the expense of image fidelity. An experimental examination of this new functionality is provided, with a focus on image-coding aspects. The results show that reduced waiting times can be achieved, and user studies indicate the usefulness of this new trade-off. The second approach concerns the throughput degradations that can occur as a consequence of link and transport layer interactions. An experimental evaluation of the GSM environment shows that when negative interactions do occur, they are coupled to large variability in link layer round-trip times rather than simply to poor radio conditions. Another type of interaction can occur for link layers which expose higher layers to residual bit errors. Residual bit errors create an ambiguity problem for congestion controlled transport layer protocols which cannot correctly determine the cause for a loss. This ambiguity leads to an unnecessary throughput degradation. To mitigate this degradation, loss differentiation and notification mechanisms are proposed and experimentally evaluated from both performance and fairness perspectives. The results show that considerable performance improvements can be realized. However, there are also fairness implications that need to be taken into account since the same mechanisms that improve performance may also lead to unfairness towards flows that do not employ loss differentiation.

Este trabalho apresenta uma plataforma e uma técnica para o melhoramento da eficiência da graduação de falhas stuck-at de padrões de teste através do uso de co-emulação de hardware. Os fabricantes de Circuitos Integrados continuamente buscam novas formas de testar seus dispositivos com o intuito de distribuir peças sem defeitos aos seus clientes. Scan é uma técnica bem conhecida que consegue alta cobertura de falhas com eficiência. As demandas por novos recursos motivam a criação de sistemas complexos que fazem uso de uma mistura de blocos analógicos e digitais com uma interface de comunicação, difícil de ser coberta pelos padrões de scan. Adicionalmente, a lógica que configura o chip para cada um dos diferentes modos de operação, algumas interfaces com circuitos de teste de memória (BIST), divisores ou geradores de clocks assíncronos, entre outros, são exemplos de circuitos que se encontram bloqueados em scan ou possuem poucos pontos de observação/controle. Este trabalho descreve uma plataforma baseada em FPGA que usa modelos heterogêneos para co-emular blocos digitais, analógicos e de memória para a graduação de padrões em sistemas complexos. Adicionalmente introduziu-se quatro tipos de modelos que podem ser usados no FPGA, e os resultados de aplicar a técnica de co-emulação de falhas em alguns circuitos de benchmark incluindo ISCAS89, um conversor análogo digital, portas configuráveis de entrada/saída e um controlador de memória. / A platform and a technique to improve stuck-at fault grading efficiency through the use of hardware co-emulation is presented. IC manufacturers are always seeking for new ways to test their devices in order to deliver parts with zero defects to their customers. Scan is a well known technique that attains high fault coverage results with efficiency. Demands for new features motivate the creation of high complex systems with a mixture of analog and digital blocks with a communication interface that is difficult to cover with scan patterns. In addition, the logic that configures the chip for each of the different test modes, some BIST memory interfaces, asynchronous clock dividers or generators, among others, are examples of circuits that are blocked or have few observation/control points during scan. A FPGA based-platform that uses heterogeneous models to emulate digital, analog and memory blocks for fault grading patterns on complex systems is described. Also introduced in our proposal are four types of models that can be used with FPGAs, and the results of applying our fault co-emulation technique to some benchmark circuits including ISCAS89, ADC, iopads and memory controllers.

"Real-time performance evaluation of wireless local area networks (WLANs) is an extremely challenging topic. The major drawback of real-time performance analysis in actual network installations is a lack of repeatability due to uncontrollable interference and propagation complexities. These are caused by unpredictable variations in the interference scenarios and statistical behavior of the wireless propagation channel. This underscores the need for a Radio Frequency (RF) test platform that provides isolation from interfering sources while simulating a real-time wireless channel, thereby creating a realistic and controllable radio propagation test environment. Such an RF-isolated testbed is necessary to enable an empirical yet repeatable evaluation of the effects of the wireless channel on WLAN performance. In this thesis, a testbed is developed that enables real-time laboratory performance evaluation of WLANs. This testbed utilizes an RF-isolated test system, Azimuthâ„¢ Systems 801W, for isolation from external interfering sources such as cordless phones and microwave ovens and a real-time multipath channel simulator, Elektrobit PROPSimâ„¢ C8, for wireless channel emulation. A software protocol analyzer, WildPackets Airopeek NX, is used to capture data packets in the testbed from which statistical data characterizing performance such as data rate and Received Signal Strength (RSS) are collected. The relationship between the wireless channel and WLAN performance, under controlled propagation and interference conditions, is analyzed using this RF-isolated multipath testbed. Average throughput and instantaneous throughput variation of IEEE 802.11b and 802.11g WLANs operating in four different channels - a constant channel and IEEE 802.11 Task Group n (TGn) Channel Models A, B, and C - are examined. Practical models describing the average throughput as a function of the average received power and throughput variation as a function of the average throughput under different propagation conditions are presented. Comprehensive throughput models that incorporate throughput variation are proposed for the four channels using Weibull and Gaussian probability distributions. These models provide a means for realistic simulation of throughput for a specific channel at an average received power. Also proposed is a metric to describe the normalized throughput capacity of WLANs for comparative performance evaluation."

Este trabalho apresenta uma plataforma e uma técnica para o melhoramento da eficiência da graduação de falhas stuck-at de padrões de teste através do uso de co-emulação de hardware. Os fabricantes de Circuitos Integrados continuamente buscam novas formas de testar seus dispositivos com o intuito de distribuir peças sem defeitos aos seus clientes. Scan é uma técnica bem conhecida que consegue alta cobertura de falhas com eficiência. As demandas por novos recursos motivam a criação de sistemas complexos que fazem uso de uma mistura de blocos analógicos e digitais com uma interface de comunicação, difícil de ser coberta pelos padrões de scan. Adicionalmente, a lógica que configura o chip para cada um dos diferentes modos de operação, algumas interfaces com circuitos de teste de memória (BIST), divisores ou geradores de clocks assíncronos, entre outros, são exemplos de circuitos que se encontram bloqueados em scan ou possuem poucos pontos de observação/controle. Este trabalho descreve uma plataforma baseada em FPGA que usa modelos heterogêneos para co-emular blocos digitais, analógicos e de memória para a graduação de padrões em sistemas complexos. Adicionalmente introduziu-se quatro tipos de modelos que podem ser usados no FPGA, e os resultados de aplicar a técnica de co-emulação de falhas em alguns circuitos de benchmark incluindo ISCAS89, um conversor análogo digital, portas configuráveis de entrada/saída e um controlador de memória. / A platform and a technique to improve stuck-at fault grading efficiency through the use of hardware co-emulation is presented. IC manufacturers are always seeking for new ways to test their devices in order to deliver parts with zero defects to their customers. Scan is a well known technique that attains high fault coverage results with efficiency. Demands for new features motivate the creation of high complex systems with a mixture of analog and digital blocks with a communication interface that is difficult to cover with scan patterns. In addition, the logic that configures the chip for each of the different test modes, some BIST memory interfaces, asynchronous clock dividers or generators, among others, are examples of circuits that are blocked or have few observation/control points during scan. A FPGA based-platform that uses heterogeneous models to emulate digital, analog and memory blocks for fault grading patterns on complex systems is described. Also introduced in our proposal are four types of models that can be used with FPGAs, and the results of applying our fault co-emulation technique to some benchmark circuits including ISCAS89, ADC, iopads and memory controllers.

Ce travail de thèse porte sur la manière dont les images et les discours produits sur l’Amazonie, ses populations et ses ressources, ont permis de faire du sud du Pará l'un des territoires d’expansion de l'élevage bovin les plus importants. Nous avons pour cela considéré l’élevage comme une institution, définie ici comme des foyers d’expérience en mouvement, posture à la base de la formulation de notre cadre théorique et méthodologique. Celui-ci nous a permis de nous écarter des variables explicatives conventionnelles et d’identifier plutôt les différents mécanismes et dispositifs qui ont rendu possible la justification et légitimité de cette activité dans une région où les forêts prédominent. Nous avons utilisé pour cela une approche multidisciplinaire alimentée principalement par Thorstein Veblen, Michel Foucault, Gilles Deleuze et Veena Das,. La polyphonie de cette tessiture théorique et méthodologique a favorisé la mise en place d'un regard distinct sur l'évolution de l'élevage bovin dans le biome de l'Amazonie. Nous avons utilisé l'analyse d'images, de discours et d'autres pratiques qui sont à la base de la formation et du fonctionnement de cette institution unique. L'accent est mis sur certains mécanismes qui en font partie : les déclarations de « peur de perdre » et « volonté de changer », ce que nous appelons ici « dispositif d'efficacité » et « émulation-force ». Ces mécanismes ont été mis en valeur par la relecture des écrits sur les élevages itinérants partant du Nord-Est du Brésil et arrivés dans le sud du Para, qui sont considérés ici sous le concept de « machine de guerre », aux côtés de la notion de «marges d'État ». / Essa tese analisa como as imagens e os discursos produzidos sobre a Amazônia, as populações e os recursos, desde uma perspectiva histórica, permitiram tornar o sul do Pará em um dos locais de maior expansão da criação de gado bovino. No primeiro momento, passamos a considerar a pecuária como uma instituição, definida aqui como focos de experiência em movimento, de modo a conduzir a formulação de um referencial teórico e metodológico que fugisse das variáveis explicativas convencionais, buscando, antes, os diversos mecanismos e dispositivos que possibilitaram a justificação/legitimidade da atividade em uma região onde predominavam florestas. Para esse percurso, valemo-nos de uma abordagem multidisciplinar fecundada principalmente por reflexões de autores como Thorstein Veblen, Michel Foucault, Gilles Deleuze, Veena Das, entre outros. A polifonia dessa tessitura teórica e metodológica aqui proposta favoreceu a constituição de um olhar distinto sobre a evolução da pecuária bovina no bioma amazônico, pensando-a como uma instituição, e trazendo para o escopo das análises as imagens, os discursos e outras práticas que permitiram a formação e funcionamento dessa instituição singular. Há uma ênfase para alguns mecanismos que fizeram parte dessa trama: os enunciados do “medo de perder” e da “vontade de transformar” e aquilo que aqui chamamos de “dispositivos de eficiência” e a “emulação-força”, que foram construídos na tese a partir da releitura dos escritos sobre a pecuária itinerante que saiu do Nordeste brasileiro e chegou ao sul do Pará, considerada aqui à luz do conceito de “máquina de guerra”, juntamente com a noção de “margens do estado”. / This thesis examines how the images and discourses produced on Amazon, populations and resources, from a historical perspective, allowed making the south of Para in one of the sites of greatest expansion of cattle breeding. At first we should consider livestock as an institution, defined here as moving experience outbreaks, so as to allow the formulation of a theoretical and methodological framework to flee the conventional explanatory variables, seeking rather to the various mechanisms and devices that allowed the justification / legitimacy of the activity in a region where forests predominated. For this route, we make use of a multidisciplinary approach enriched mainly by reflections of authors such as Thorstein Veblen, Michel Foucault, Gilles Deleuze, Veena Das, among others. This polyphony made possible by theoretical and methodological frameworks proposed here allowed the establishment of a different look at the evolution of cattle breedingin the Amazon biome, considering it as an institution, and bringing to the scope of the image analysis, speeches and other practices that allowed the formation and operation of this unique institution. There is an emphasis on some mechanisms that were part of this plot: the statements of the "fear of losing" and "wish of transforming" and what we here call "efficiency device" and "emulation-force", as well as a reinterpretation the writings on the itinerant cattle that came out from Northeast Brazil and reached the south of Pará, considered here in the light of the concept of a "war machine" with the notion of "state banks".

L'objet de cette thèse est de doter les réseaux satellites d'accès géostationnaires d'une architecture de QoS compatible avec l'infrastructure NGN (Next Generation Network) qui entend réaliser la convergence des réseaux et services de communication existants et à venir. Dans une première étape, nous établissons un modèle de QoS NGN s'inspirant principalement de l'évolution des architectures de QoS dans les réseaux IP. Dans une deuxième étape, nous démontrons que les réseaux satellites ne disposent pas, en l'état actuel, d'une architecture de QoS suffisamment mature pour assurer un accès large bande aux futurs services IP multimédias. Afin d'y remédier, nous spécifions une architecture de QoS NGN unifiée assurant une étroite collaboration entre les mécanismes de QoS déployés à différents niveaux de communication (Application, Session, Réseau et MAC). Elle assure à la fois une différenciation de la QoS adaptée aux besoins des différentes classes d'applications au niveau IP tout en optimisant l'utilisation des ressources satellites via des mécanismes de bande passante à la demande au niveau MAC. Deux solutions applicatives assurant la corrélation dynamique entre les applications et les services réseaux différenciés sont également spécifiées et implémentées. Enfin un émulateur satellite de niveau réseau a été implémenté et nous a permis d'évaluer les garanties de QoS offertes par notre architecture et de valider leur conformité avec les besoins d'applications multimédias réelles.