Optimal decision directed equalization techniques for time dispersive communication channels are often too complex to implement. This thesis considers reduced complexity decision directed equalization that lowers complexity demands yet retains close to optimal performance. The first part of this dissertation consists of three reduced complexity algorithms based on the Viterbi Algorithm (VA) which are: the Parallel Trellis VA (PTVA); Time Reverse Reduced State Sequence Estimation (TR-RSSE); and Forward-Backward State Sequence Detection (FBSSD). The second part of the thesis considers structural modifications of the Decision Feedback Equalizer (DFE), which is a special derivative of the VA, specifically, optimal vector quantization for fractionally spaced DFEs, and extended stability regions for baud spaced DFEs using passivity analysis are investigated.¶ For a special class of sparse channels the VA can be decomposed over a number of independent parallel trellises. This decomposition will be called the Parallel Trellis Viterbi Algorithm and can have lower complexity than the VA yet it retains optimal performance. By relaxing strict sparseness constraints on the channel a sub-optimal approach is proposed which keeps complexity low and obtains good performance.¶ Reduced State Sequence Estimation (RSSE) is a popular technique to reduce complexity. However, its deficiency can be the inability to adequately equalize non-minimum phase channels. For channels that have energy peaks in the tail of the impulse response (post-cursor dominant) RSSE's complexity must be close to the VA or performance will be poor. Using a property of the VA which makes it invariant to channel reversal, TR-RSSE is proposed to extend application of RSSE to post-cursor dominant channels.¶ To further extend the class of channels suitable for RSSE type processing, FBSSD is suggested. This uses a two pass processing method, and is suited to channels that have low energy pre and post-cursor. The first pass generates preliminary estimates used in the second pass to aid the decision process. FBSSD can range from RSSE to TR-RSSE depending on parameter settings.¶ The DFE is obtained when the complexity of RSSE is minimized. Two characterizing properties of the DFE, which are addressed in this thesis, are feedback and quantization. A novel fractionally spaced (FS) DFE structure is presented which allows the quantizer to be generalized relative to the quantizer used in conventional FS-DFEs. The quantizer can be designed according to a maximum a posteriori criterion which takes into account a priori statistical knowledge of error occurrences. A radically different quantizer can be obtained using this technique which can result in significant performance improvements.¶ Due to the feedback nature of the DFE a form of stability can be considered. After a decision error occurs, a stable DFE will, after some finite time and in the absence of noise, operate error free. Passivity analysis provides sufficient conditions to determine a class of channels which insures a DFE will be stable. Under conditions of short channels and small modulation alphabets, it is proposed that conventional passivity analysis can be extended to account for varying operator gains, leading to weaker sufficient conditions for stability (larger class of channels).

Advances in CMOS technology have resulted in increased clock fre-quencies, even exceeding 3GHz. At the same time, frequencies on most board wires are 125-800MHz. It is especially problematic in modern computer mem-ory buses and high speed telecommunication devices, such as switches and routers operating at 10Gb/s on its ports. It is believed that circuit board buses can be used up to about 20GHz, but there is a problem with Intersymbol Inter-ference (ISI) causing distortion of transmitted symbols by multiple reflections. Actually, the circuit board bus behaves like a passive low pass filter with unknown (perhaps changing) transfer characteristic. The problem of ISI was solved some time ago in the telecommunication area. With use of adaptive equalizers it is possible to increase throughput of a long distance communication channel dramatically. But the microprocessor bus has certain differences from telecommunica-tion devices such as modems. First of all, the clock frequency on a bus is much higher than in modems. Secondly, a bus has a much more complex structure than a telecommunication channel. At the same time, we can’t use a lot of re-sources for bus maintaining. The aim of the thesis work is to investigate the possibility of using adap-tive equalization on a bus, and the construction of a reasonable mathematical model of such an equalizer. Also limits of equalizationare examined and de-pendencies are derived.

This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit architecture and topology and implements the circuit in 0.18-um CMOS to enable 10-Gb/sec serial baseband data transmission over FR-4 backplane and optical fibre. The ADFE overcomes the first feedback-loop latency challenge of traditional digital and mixed-signal DFEs by separating data re-timing from equalization and also eliminates the need for clock-recovery prior to decision-feedback equalization. The ADFE enables 10-Gb/sec decision-feedback equalization using a 0.18-um CMOS process, the first to do so to the author s knowledge. A tuneable current-mode-logic (CML) feedback-loop is designed to enable first post-cursor cancellation for a range of data-rates and to have external control over loop latency over variations in process, voltage and temperature. CML design techniques are used to minimize current consumption and achieve the required voltage swing for decision-feedback to take place. The all-analog equalizer consumes less power and area than comparable state-of-the art DFEs. The ADFE is used to compensate inter-symbol interference (ISI) for 20 inches of FR-4 backplane and 300 m of multi-mode fibre at 10-Gb/sec. The ADFE also extends the reach of single-mode fibre at 10-Gb/sec to 120 km. The work described in this dissertation advances the state-of-the-art in equalization solutions for multi-Gb/sec serial data transmission and can find applications in several of the 10-Gb/sec Ethernet standards that have been approved recently. The contributions of this work toward future research are also discussed.

Recently, interference alignment (IA) has emerged as a promising technique to effectively mitigate interference in wireless communication systems. It has also evolved as a powerful technique to achieve the optimal degrees of freedom of interference channel. IA can be constructed in many domains such as space, time, frequency and codes. Currently, most researches on developing IA assume that channel state information (CSI) is well-known at the transceiver. However, in practice, perfect CSI at the transceiver can¡¦t be obtained due to many factors such as channel estimation error, quantization error, and feedback error. Under our investigation, the performance of IA is very sensitive to imperfect CSI. Therefore, this thesis proposes a spatial domain IA scheme for the three-user multiple-input multiple-output (MIMO) downlink interference channels, and analyzes the effect of channel estimation errors by modeling the estimation error as independent complex Gaussian random variables. The approximated bit error rate (BER) for the system with MIMO Zero-Forcing equalizer using IA is derived.

All digital communication channels are subject to inter-symbol interference (ISI). To achieve the desired system performance, at receiver end, the effect of ISI must be compensated and the task of the equalizer is to combat the degrading effects of ISI on the transmission. Due to the demand of high data transmission rate, the multicarrier modulation (MCM) technique implemented with the orthogonal frequency division multiplexing (OFDM) has been adopted in many modern communications systems for block transmission. In block transmission systems, transmitter-included redundancy using finite-impulse response (FIR) filterbanks can be utilized to suppress inter-block-interference (IBI). However, the length of redundancy will affect the system performance, which is highly dependent on the length of channel impulse response. To deal with the effect of ISI, many equalizing schemes have been proposed, among them the FIR zero-forcing (ZF) equalizer with the non-orthogonal projector provides a useful transceiver design structure for suppressing the IBI and ISI, simultaneously. In this thesis, we propose a new equalizing scheme; it combines the FIR-ZF equalizer with non-orthogonal projector as well as the Bayesian decision feedback equalizer (DFE) for IBI and ISI suppression. The Bayesian DFE is known to be one of the best schemes to achieve the desired performance for eliminating ISI. It can be employed to achieve the full potential of symbol-by-symbol equalizer. That is, after removing the effect of IBI with the non-orthogonal projector, the Bayesian DFE is employed for eliminating the ISI, simultaneously. For comparison, the system performance, in term of bit error rate (BER) is investigated, and compared with the minimum mean square error (MMSE)-IBI-DFE. The advantage of the new proposed equalizing scheme is verified via computer simulation under condition of insufficient redundancy.

<p>Advances in CMOS technology have resulted in increased clock fre-quencies, even exceeding 3GHz. At the same time, frequencies on most board wires are 125-800MHz. It is especially problematic in modern computer mem-ory buses and high speed telecommunication devices, such as switches and routers operating at 10Gb/s on its ports. It is believed that circuit board buses can be used up to about 20GHz, but there is a problem with Intersymbol Inter-ference (ISI) causing distortion of transmitted symbols by multiple reflections. </p><p>Actually, the circuit board bus behaves like a passive low pass filter with unknown (perhaps changing) transfer characteristic. The problem of ISI was solved some time ago in the telecommunication area. With use of adaptive equalizers it is possible to increase throughput of a long distance communication channel dramatically. </p><p>But the microprocessor bus has certain differences from telecommunica-tion devices such as modems. First of all, the clock frequency on a bus is much higher than in modems. Secondly, a bus has a much more complex structure than a telecommunication channel. At the same time, we can’t use a lot of re-sources for bus maintaining. </p><p>The aim of the thesis work is to investigate the possibility of using adap-tive equalization on a bus, and the construction of a reasonable mathematical model of such an equalizer. Also limits of equalizationare examined and de-pendencies are derived.</p>

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

This paper examines three models used for business plan analysis. These models highlight some of the most important questions of the business: What are my strengths and how do I compete? More importantly, it gives founders a systematic tool to approach the creation of strategy for their business. There are three business planning tools presented here: Porter’s Five Forces, SWOT, and Price Equalizer.

In recent years Multiple Input Multiple Output (MIMO) systems have been employed in wireless communication systems to reach the goals of high data rate. A MIMO use multiple antennas at both transmitting and receiving ends. These antennas communicate with each other on the same frequency band and help in linearly increasing the channel capacity. Due to the multi paths wireless channels face the problem of channel fading which cause Inter Symbol Interference (ISI). Each channel path has an independent path delay, independent path loss or path gain and phase shift, cause deformations in a signal and due to this deformation the receiver can detect a wrong or a distorted signal. To remove this fading effect of channel from received signal many Neural Network (NN) based channel equalizers have been proposed in literature. Due to high level non-linearity, NN can be efficient to decode transmitted symbols that are effected by fading channels. The task of channel equalization can also be considered as a classification job. In the data (received symbol sequences) spaces NN can easily make decision regions. Specifically, NN has the universal approximation capability and form decision regions with arbitrarily shaped boundaries. This property supports the NN to be introduced and perform the task of channel equalization and symbol detection. This research project presents the implementation of NN to be use as a channel equalizer for Rayleigh fading channels causing ISI in MIMO systems. Channel equalization has been done using NN as a classification problem. The equalizer is implemented over MIMO system of different forms using Quadrature Amplitude Modulation scheme (4QAM &amp; 16QAM) signals. Levenberg-Marquardt (LM), One Step Secant (OSS), Gradient Descent (GD), Resilient backpropagation (Rprop) and Conjugate Gradient (CG) algorithms are used for the training of NN. The Weights calculated during the training process provides the equalization matrix as an estimate of Channel. The output of the NN provides the estimate of transmitted signals. The equalizer is assessed in terms of Symbol Error Rate (SER) and equalizer efficiency.