The objective of this thesis was to develop an 8051 microcontroller soft core in the Verilog hardware description language (HDL). Each functional unit of the 8051 microcontroller was developed as a separate module, and tested for functionality using the open-source VHDL Dalton model as benchmark. These modules were then integrated to operate as concurrent processes in the 8051 soft core. The Verilog 8051 soft core was then synthesized in Quartus® II simulation and synthesis environment (Altera Corp., San Jose, CA, www.altera.com) and yielded the expected behavioral response to test programs written in 8051 assembler residing in the v8051 ROM. The design can operate at speeds up to 41 MHz and used only 16% of the FPGA fabric, thus allowing complex systems to be designed on a single chip. Further research and development can be performed on v8051 to enhance performance and functionality.

This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create computational materials that can conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays with nearest neighbor communication and are capable of general computation. They operate asynchronously to minimize power consumption and to allow sealing without the limitations imposed by a global clock. Cell operations are stimulated by pulses which use two wires to encode a data bit. Cells are individually reconfirgurable to perform logic, move and store information, and coordinate parallel activity. The PQ-cell design targets a 0.25 μm CMOS technology. Simulation results show that a PQ-cell, when pulsed at 1.3 GHz, consumes 16.9 pJ per operation. Examples of self-timed multi-cell structures include a 98 MHz ring oscillator and a 385 MHz pipeline.

Seit einigen Jahren werden für den Entwurf anwendungsspezifischer Schaltungen verstärkt Field-Programmable Gate-Arrays (FPGAs) als Alternative zu maskenprogrammierten ASICs eingesetzt. Der Vorteil von FPGAs liegt vor allem in der schnellen und preiswerten Schaltungsentwicklung. Für den Entwurf von Schaltungen sind derzeit jedoch Software-Werkzeuge verschiedener Hersteller erforderlich. Im Rahmen eines von der Deutschen Forschungsgemeinschaft geförderten Projektes wurde gemeinsam mit der Universität Tübingen und der Technischen Universität München ein funktionsfähiges FPGA-Entwurfssystem entwickelt. Das in diesem Bericht vorgestellte Entwurfssystem beinhaltet alle wichtigen Synthese- und Layout-Komponenten zur Realisierung von Schaltungen auf FPGAs. Es wird eine Entwurfsmethodik vorgestellt, mit der alle notwendigen Entwurfsschritte bis zur Verdrahtung durchführbar sind. Ausgangspunkt ist dabei eine Schaltungsbeschreibung in verhaltensbasiertem VHDL. Für die einzelnen Systemkomponenten werden Software-Werkzeuge verwendet, die an den beteiligten Instituten entwickelt werden. Zur Ablaufsteuerung wurde eine Benutzeroberfläche entworfen, in die bisher die Technologieabbildung sowie das Layout integriert wurden.

Zur Verdrahtung der meisten FPGA-Architekturen können die aus dem ASIC-Entwurf stammenden Werkzeuge wie z.B. Kanalverdrahter nicht eingesetzt werden. Eine vollautomatische Verdrahtung mit optimalen Signallaufzeiten kann nur dann erreicht werden, wenn bei gegebener Plazierung die Leitungführung den technologischen Gegebenheiten angepaßt wird. Diese unterscheiden sich deutlich von denen in ASICs. Im Rahmen des von der Deutschen Forschungsgemeinschaft (DFG) geförderten Gemeinschafts-Projekts „FPGA Entwurfssystem“, an dem die Universität Leipzig, die Universität Tübingen und die Technischen Universität München beteiligt sind, wurden am Lehrstuhl für Computersysteme (Prof. W.G. Spruth) des Instituts für Informatik der Universität Leipzig Verfahren zur effizienten und qualitativ hochwertigen Verdrahtung von FPGA-Bausteinen entwickelt. Es wird eine Beschreibung des Verdrahtungsproblems für FPGAs gegeben und ein Lösungsansatz mit Hilfe des Branch&Bound – Verfahrens vorgestellt. Die Ergebnisse in Form von Programmlaufzeiten, Länge des kritischen Pfades und Anzahl der betrachteten Suchknoten in Abhängigkeit von einer Vielzahl von Schaltungsvarianten sind tabellarisch dargestellt und dokumentieren eine deutliche Verkürzung der längsten Pfade gegenüber dem Plazier- und Verdrahtungswerkzeug von Xilinx. Abschließend werden Probleme und weiterführende Arbeiten diskutiert.

A user-friendly fully digital TDPAC-spectrometer with six detectors and fast digitizers using Field Programmable Gate Arrays is described and performance data are given.

Productivity for digital circuit design is being outpaced currently by the rate at which<br />silicon is growing such as FPGAs. Complex designs take a large amount of engineering<br />hours to complete. Reuse of existing design can potentially decrease this cost and increase<br />design productivity. However, existing digital hardware designs are not being effectively<br />reused by the hardware community due to the inability of designers to have knowledge of<br />all the attributes of designs that can be reused. In addition, designers will have to accustom<br />themselves to designs in the hardware library. By having a back-end system that looks for<br />similar circuits, there is little to no effort for the designer to reuse the design. This thesis<br />provides an overview and comparison of different methods for characterizing and comparing<br />digital circuits in order to suggest candidate circuits that engineers can reuse. Several of<br />these methods are implemented, modified, and compared to show the feasibility of utilizing<br />this work for increasing overall productivity.<br /> / Master of Science

An IVDS (Interactive Video Data Service) uses an interactive television system to transmit data to and from subscribers' homes. IVDS allows the viewer to interact with content provided on the television using a remote control. A typical IVDS application would be ordering an advertised product or playing along with a quiz show. The Virginia Tech Center for Wireless Telecommunications (CWT), under a contract with Interactive Return Service, Inc., is developing an IVDS system in which content is provided through the television cable system in the form of audio codes. A special remote control can detected these audio codes and query the user for input. The return path for this system is a wireless channel. The remote control contains a spread spectrum transmitter that transmits packets to a Repeater unit residing within a quarter mile of the user's home. With the popularity of the World Wide Web soaring, many companies are announcing internet appliances that will bring the content of the web to the user at a fraction of the cost of a standard personal computer. CWT has been contracted to extend the core IVDS system to provide a web browsing capability, allowing the user to browse the web with only the remote control. This thesis outlines the requirements of the IVDS Web Browser System. The different hardware design concepts are documented. The final Browser System specification is presented, as well as a board-level description of the Decoder Unit that is part of this final Browser System. Finally, a detailed description, current status, and simulation results are presented for the FPGA (Field Programmable Gate Array) that serves as the controller for the Decoder Unit. / Master of Science

Many problems faced in the engineering world are computationally intensive. Filtering using FIR (Finite Impulse Response) filters is an example to that. This thesis discusses the implementation of a fast, reconfigurable, and scalable FIR (Finite Impulse Response) digital filter. Constant coefficient multipliers and a Fast FIFO implementation are also discussed in connection with the FIR filter. This filter is used in two of its structures: the direct-form and the lattice structure. The thesis describes several configurations that can be created with the different components available and reports the testing results of these configurations. / Master of Science

This thesis describes the development of a multi-sensor, multi-energy x-ray prototype for automated explosives detection. The system is based on the American Science and Engineering model 101ZZ x-ray system. The 101ZZ unit received was an early model and lacked documentation of the many specialized electronic components. X-ray image quality was poor. The system was significantly modified and almost all AS&E system electronics bypassed: the x-ray source controller and conveyor belt motor were made computer controllable; the x-ray detectors were re-positioned to provide forward scatter detection capabilities; new hardware was developed to interface to the AS&E pre-amplifier boards, to collect image data from all three x-ray detectors, and to transfer the data to a personal computer. This hardware, the Differential Pair Interface Board (DPIB), is based on a Field Programmable Gate Array (FPGA) and can be dynamically re-configured to serve as a general purpose data collection device in a variety of applications. Software was also developed for the prototype system. A Windows NT device driver was written for the DPIB and a custom bus master DMA collection device. These drivers are portable and can be used as a basis for the development of other Windows NT drivers. A graphical user interface (GUI) was also developed. The GUI automates the data collection tasks and controls all the prototype system components. It interfaces with the image processing software for explosives detection and displays the results. Suspicious areas are color coded and presented to the operator for further examination. / Master of Science

Artificial neural networks are increasing in power, with attendant increases in demand for efficient processing. Performance is limited by clock speed and degree of parallelization available through multi-core processors and GPUs. With a design tailored to a specific network, a field-programmable gate array (FPGA) can be used to minimize latency without the need for geographically distributed computing. However, the task of programming an FPGA is outside the realm of most data scientists. There are tools to program FPGAs from a high level description of a network, but there is no unified interface for programmers across these tools. In this thesis, I present the design and implementation of NeuralSynth, a prototype Python framework which aims to bridge the gap between data scientists and FPGA programming for neural networks. My method relies on creating an extensible Python framework that is used to automate programming and interaction with an FPGA. The implementation includes a digital design for the FPGA that is completed by a Python framework. Programming and interacting with the FPGA does not require leaving the Python environment. The extensible approach allows multiple implementations, resulting in a similar workflow for each implementation. For evaluation, I compare the results of my implementation with a known neural network framework. / Includes bibliography. / Thesis (M.S.)--Florida Atlantic University, 2020. / FAU Electronic Theses and Dissertations Collection