This thesis deals with synthesis and characterization of newoligothiophenes and derivatives thereof, for use as organicsemiconductors in optical and electronic applications, such asfield-effect transistors and light-emitting diodes. Much workis devoted to the development of new synthetic strategies forinteresting building blocks, to beused for synthesizing suchmaterials. One series of regio-defined oligothiophenes, up tothe octamer, has been prepared and evaluated. Photoluminescencequantum efficiencies of these were 22-31 % in solution, butdropped to 2-5 % in the solid state. Another project deals withthe development of oligothiophenes with in-chain chirality.These may find use in polarized lightemitting diodes. Finally,two oligothienyl-substituted porphyrins have been synthesizedand are currently evaluated for use in light-emitting diodesand possibly in solar cells. / NR 20140805

<p>  </p> <p>Organic semiconductors have been considered a promising candidate to replace Silicon-based inorganic semiconductors in our electronics due to their lightweight, high flexibility, and solution processability. Recently, conjugated polymers were shown to be functional at up to 200°C, expanding organic semiconductors application territory into high-temperature electronics, which sorely depends on wide-bandgap semiconductors. To push the operational temperature boundary of polymer transistors even further than 200°C, our understanding of temperature impacts on the materials and charge transport mechanism in such harsh conditions needs to be improved. Here, we study the high temperature effect on polymer transistors from two main directions: via molecular design and via device engineering. First, via sidechain design, we explored the impact of close π-π packing on the thermal stability of semiconducting polymers. We discovered that maintaining close π-π packing can lead to lower chain distortion, thus improving the polymer transistors' operational stability at high temperatures. Then we study the impact from device factor, specifically contact resistance in device behavior at extreme conditions. We found that the contact area is more susceptible to high temperatures than other regions in the channels and is the main reason for the degraded performance. We then propose a facile method to minimize the contact problem, to achieve stable devices at above 200°C. And last, we proposed a simple method to attain quasi-temperature independent charge transport in polymer transistors from room temperature to 140°C by simply applying a prolonged bias gate voltage before heating. This research expands our knowledge on charge transport in conjugated polymers at high temperatures and provides a guide to make conjugated polymer transistors for extreme conditions in the future.</p>

En dépit d'une amélioration remarquable de la performance des composants électroniques organiques, il y a encore un manque de compréhension théorique rigoureux sur le fonctionnement du composant. Cette thèse est consacrée à la création de modèles pratiques pour composants électroniques organiques à base physique complet, à savoir un modèle compact à base physique. Un modèle compact à base physique d'un élément de circuit est une équation mathématique qui décrit le fonctionnement du composant, et est généralement évaluée par trois critères: si elle est suffisamment simple pour être incorporé dans des simulateurs de circuits, précise pour rendre le résultat des simulateurs utile les concepteurs de circuits et rigoureux pour capturer des phénomènes physiques se produisant dans le composant. Dans ce contexte, les caractéristiques distinctives de l'injection de porteurs de charge et de transport dans les semi-conducteurs organiques sont incorporés dans les modèles avec un effort particulier pour maintenir la simplicité mathématique. L'effet concomitant sur les caractéristiques courant-tension des diodes et des transistors organiques prototypiques sont étudiés. Les méthodes d'extraction des paramètres cohérents aux modèles sont présentés qui permettent la détermination univoque des paramètres de le composant utilisé pour le fonctionnement du composant de modélisation et l'évaluation des performances de le composant et les propriétés des couches minces et des interfaces organiques. Les approches englobent le developement analytique des équations physiques, la simulation numérique à deux dimensions basé sur la méthode des éléments finis et la validation expérimentale. Les modèles compacts originaux et entièrement analytiques et des méthodes d'extraction de paramètres fournissent une compréhension fondamentale sur la façon dont le désordre énergétique dans une couche mince de semi-conducteur organique, décrit par la densité d’etats Gaussienne, affecte les caractéristiques courant-tension observables des composants.Mots-clés : Electronique organique, physique des composants électroniques, modélisation analytique, diodes, transistors à effet de champ, densité d’etats Gaussienne / In spite of a remarkable improvement in the performance of organic electronic devices, there is still a lack of rigorous theoretical understanding on the device operation. This thesis is dedicated to establishing practical models of organic electronic devices with a full physical basis, namely a physically-based compact model. A physically-based compact model of a circuit element is a mathematical equation that describes the device operation, and is generally assessed by three criteria: whether it is sufficiently simple to be incorporated in circuit simulators, accurate to make the outcome of the simulators useful to circuit designers, and rigorous to capture physical phenomena occuring in the device. In this context, distinctive features of charge carrier injection and transport in organic semiconductors are incorporated in the models with a particular effort to maintain mathematical simplicity. The concomitant effect on the current-voltage characteristics of prototypical organic diodes and transistors are studied. Parameter extraction methods consistent to the models are presented which enable unambiguity determination of device parameters used for modeling device operation and assessing device performance and properties of organic thin-films and interfaces. The approaches encompass analytical developement of physical equations, two-dimensional numerical simulation based on finite-element method and experimental validation. The original and fully analytical compact models and parameter extraction methods provide fundamental understanding on how energetic disorder in an organic semiconductor thin-film, described by the Gaussian density of states, affects the observable current-voltage characteristics of the devices.Keywords : Organic electronics, device physics, analytical modeling, diodes, field-effect transistors, Gaussian density-of-states

The conformational dynamics of RNA are crucial to its role in numerous essential biological functions, requiring a comprehensive view of masses of individual molecular motions in order to fully understand these processes. Obtaining such a unified view, however, presents many challenges. Even the simplest RNA structures undergo rearrangements within an intricate three-dimensional network of secondary and tertiary interactions, resulting in motions that span a broad range of timescales. This complexity gives rise to a large number of experimental techniques sampling different aspects of the folding process, leaving a rather fragmented picture of RNA folding overall. In order to address the divergence and limitations of existing ensemble and single-molecule methods, this work describes the application of carbon nanotube (CNT)-based single-molecule field-effect transistors (smFET) as a platform for studying the folding and unfolding dynamics of RNA. smFET is capable of measuring individual biomolecular dynamics for long durations, while at a sufficiently high time resolution to capture the relevant timescales for RNA folding. This technique, moreover, avoids potential sources of interference or damage to the molecule as found in other available methods, and capitalizes on the detailed information that can be garnered from studying a single molecule as opposed to an ensemble. By taking advantage of the highly sensitive electronic properties and nanoscale dimensions of CNTs, and tethering a comparably sized and charged single biomolecule like RNA, it is possible to monitor the folding and unfolding of the molecule and characterize the kinetics associated with these motions. This thesis describes the optimization and application of such smFET technology to RNA stem-loops, which are extremely prevalent and thermodynamically stable elements of RNA secondary structure. Chapter 1 introduces the biological context of these molecules as well as the mechanisms of CNT-based smFET sensing. In Chapter 2, the methods used to fabricate smFET devices are described along with the experiments conducted to optimize single-molecule tethering. These methods and protocols were then applied to the studies detailed in Chapter 3, which examines the implications of the thermodynamic and kinetic analyses of RNA stem-loop folding and unfolding as investigated with smFET. Chapter 4 concludes with a brief overview of what has been accomplished and potential future directions for this platform. The work expressed here thus presents a cohesive view of RNA stem-loop folding, integrating the past results of both experimental and computational studies. With this improved smFET methodology, this technique can be applied to many other essential and increasingly complex biological systems to achieve a fuller and richer understanding of the processes that govern life.

This master´s thesis deals with possibilities of application of new organic molecular materials for electronic devices. Nowadays it is a very attractive field of research, because of the tendencies in industry to miniaturize, reduce production costs and develop new, eco-friendlier, processes of production. The theoretical part of the thesis provides a short overview of organic materials suitable for smart applications and thin films issues including their characterization. The experimental part is dedicated to means how to prepare thin-film electronic components to silicon wafers for thin films field effect transistors. The obtained results in the last part of thesis are discussed about properties of prepared thin films, in the concrete about the electrical transport properties, in the connection with the condition of preparation.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第21110号 / 工博第4474号 / 新制||工||1695(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 教授 白石 誠司 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

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Single electron transistors (SET) have attracted significant attention as a potential building block for post CMOS nanoelectronic devices. However, lack of reproducible and parallel fabrication approach and room temperature operation are the two major bottlenecks for practical realization of SET based devices. In this thesis, I demonstrate large scale single electron transistors fabrication techniques using solution processed single wall carbon nanotubes (SWNTs) and studied their electron transport properties. The approach is based on the assembly of individual SWNTs via dielectrophoresis (DEP) at the selected position of the circuit and formation of tunnel barriers on SWNT. Two different techniques: i) metal-SWNT Schottky contact, and ii) mechanical templating of SWNTs were used for tunnel barrier creation. Low temperature (4.2K) transport measurement of 100 nm long metal-SWNT Schottky contact devices show that 93% of the devices with contact resistance (RT) > 100 K? show SET behavior. Majority (90%) of the devices with 100 K? < RT < 1 M?, show periodic, well-de?ned Coulomb diamonds with a charging energy ~ 15 meV, represents single electron tunnelling through a single quantum dot (QD), defined by the top contact. For high RT (> 1M?), devices show multiple QDs behaviors, while QD was not formed for low RT ( < 100 K?) devices. From the transport study of 50 SWNT devices, a total of 38 devices show SET behavior giving an yield of 76%. I also demonstrate room temperature operating SET by using mechanical template technique. In mechanical template method individual SWNT is placed on top of a Al/Al2O3 local gate which bends the SWNT at the edge and tunnel barriers are created. SET devices fabricated with a template width of ~20 nm shows room temperature operation with a charging energy of ~150 meV. I also discussed the detailed transport spectroscopy of the devices.

Fabrication of high-performance electronic devices using the novel semiconductors is essential for developing future electronics which can be applicable in large-area, flexible and transparent displays, sensors and solar cells. One of the major bottlenecks in the fabrication of high-performance devices is a large interfacial barrier formation at metal/semiconductor interface originated from Schottky barrier and interfacial dipole barrier which causes inefficient charge injection at the interface. Therefore, having a favorable contact at electrode/semiconductor is highly desirable for high-performance devices fabrication. In this dissertation, the fabrication of nanoelectronic devices and investigation of their transport properties using carbon nanotubes (CNTs) and graphene as electrode materials will be shown. I investigated two types of devices using (i) semiconducting CNTs, and (ii) organic semiconductors (OSC). In the first part of this thesis, I will demonstrate the fabrication of high-performance solution-processed highly enriched (99%) semiconducting CNT thin film transistors (s-CNT TFTs) using densely aligned arrays of metallic CNTs (m-CNTs) for source/drain electrodes. From the electronic transport measurements at room temperature, significant improvements of field-effect mobility, on-conductance, transconductance and current on/off ratio for m-CNT/s-CNT devices were found compared to control palladium (Pd contacted s-CNT devices. From the temperature dependent transport investigation, a lower Schottky barrier height for the m-CNT/s-CNT devices was found compared to the devices with control metal electrodes. The enhanced device performance can be attributed to the unique device geometry as well as strong ?- ? interaction at m-CNT/s-CNT interfaces. In addition, I also investigated s-CNT TFTs using reduced graphene oxide (RGO) electrodes. In the second part of my thesis, I will demonstrate high-performance organic field-effect transistors (OFETs) using different types of graphene electrodes. I show that the performance of OFETs with pentacene as OSC and RGO as electrode can be continuously improved by increasing the carbon sp2 fraction of RGO. The carbon sp2 fractions of RGO were varied by controlling the reduction time. When compared to control Pd electrodes, the mobility of the OFETs shows an improvement of ?200% for 61% sp2 fraction RGO, which further improves to ?500% for 80% RGO electrode. Similarly, I show that when the chemical vapor deposition (CVD) graphene film is used as electrodes in fabricating OFET, the better performance is observed in comparison to RGO electrodes. Our study suggests that, in addition to ?-? interaction at graphene/pentacene interface, the tunable electronic properties of graphene as electrode have a significant role in OFETs performance. For a fundamental understanding of the interface, we fabricated short-channel OFETs with sub-100nm channel length using graphene electrode. From the low temperature electronic transport measurements, a lower charge injection barrier was found compared to control metal electrode. The detailed investigations reported in this thesis clearly indicated that the use of CNT and graphene as electrodes can improve the performance of future nanoelectronic devices.

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XLI