No description available.

Im Laufe der Verkleinerungen integrierter Schaltungen ergab sich die Notwendigkeit der alternativen dielektrischen Materialen. Hohe Polarisierbarkeiten in diesen dielektrischen Dünnfilmen treten erst in hoch direktionalen kristallinen Phasen auf. Aufgrund der erschwerten Integrierbarkeit von epitaktischen, einkristallinen Oxidfilmen können nur poly-, beziehungsweise nanokristalle Filme eingesetzt werden. Diese sind jedoch mit hohen Leckströmen behaftet. Weil die Information in einer DRAM-Zelle als Ladung in einem Kondensator gespeichert wird ist der Verlust dieser Ladung durch Leckströme die Ursache für Informationsverluste. Die Frequenz der notwendigen Auffrischungszyklen einer DRAM-Zelle wird direkt durch die Leckströme bestimmt. Voraussetzungen für die Entwicklung neuer dielektrischer Materialien ist das Verständnis der zugrunde liegenden Ladungsträgertransportmechanismen und ein Verständnis der strukturellen Schichteigenschaften, welche zu diesen Leckströmen führen. Conductive atomic force Microscopy ist ein Rastersondenmethode mit der strukturelle Eigenschaften mit lokaler elektrischer Leitfähigkeit korreliert wird. Mit dieser Methode wurde in einer vergleichenden Studie die räumlichen Leckstromverteilungen untersucht. Und es wurde gezeigt, dass es genügt eine nicht geschlossene Zwischenschicht Aluminiumoxid in eine Zirkoniumdioxidschicht zu integrieren um die Leckströme signifikant zu reduzieren während eine ausreichend hohe Kapazität erhalten bleibt. Darüberhinaus wurde ein CAFM modifiziert und benutzt um das Schaltverhalten eines Siliziumnanodrahtschottkybarrierenfeleffektransistor in Abhängigkeit der Spitzenposition zu untersuchen. Es konnte experimentell bestätigt werden das die Schottkybarrieren den Ladungstransport in diesen Bauteilen kontrollieren. Darüber hinaus wurde ein proof-of-concept für eine umprogrammierbaren nichtflüchtigen Speicher, der auf Ladungsakkumulation und der resultierenden Bandverbiegung an den Schottkybarrieren basiert, gezeigt. / In the course of the ongoing downscaling of integrated circuits the need for alternative dielectric materials has arisen. The polarizability of these dielectric thin-films is highest in highly directional crystalline phases. Since epitaxial single crystalline oxide films are very difficult to integrate into the complex DRAM fabrication process, poly- or nanocrystalline thin-films must be used. However these films are prone to very high leakage currents. Since the information is stored as charge on a capacitor in the DRAM cell, the loss of this charge through leakage currents is the origin of information loss. The rate of the necessary refresh cycles is directly determined by these leakage currents. A fundamental understanding of the underlying charge carrier transport mechanisms and an understanding of the structural film properties leading to such leakage currents are essential to the development of new, dielectric thin-film materials. Conductive Atomic Force Microscopy (CAFM) is a scanning probe based technique which correlates structural film properties with local electrical conductivity. This method was used to examine the spatial distribution of leakage currents in a comparative study. I was shown that it is sufficient to include an unclosed interlayer of Aluminium oxide into a Zirconium dioxide film to significantly reduce leakage currents while maintaining a sufficiently high capacitance. Moreover, a CAFM was modified and used to examine the switching behavior of a silicon nanowire Schottky barrier field effect transistors in dependence of the probe position. It was proven experimentally that Schottky barriers control the charge carrier transport in these devices. In addition, a proof of concept for a reprogrammable nonvolatile memory device based on charge accumulation and band bending at the Schottky barriers was shown.

Durch Multiskalensimulationen wird der Ladungstransport in nanodrahtbasierten Schottky-Barrieren-Feldeffekt-Transistoren im Materialsystem Ni2Si/Si untersucht. Die Bedingungen an die Genauigkeit der verwendeten Eingangsparameter werden bestimmt und Vorhersagen über optimale Material- und Geräteparameter werden getroffen. Es wird die Frage beantwortet, ob die Bestimmung von physikalischen Parametern aus einzelnen gemessenen Strom-Spannungs-Kennlinie möglich ist. Der Feldeffekt wird durch Berechnungen auf Basis der Finiten-Elemente-Methode und die resultierenden Stromflüsse durch ein quantenmechanisches Transportmodell ermittelt. In der Untersuchung der geometrischen Eingangsparameter wird gezeigt, dass bis auf den Radius des Nanodrahtes die in einem Experiment zu erwartenden Messfehler keinen drastischen Einfluss auf die Strom-Spannungs-Kennlinie haben. Signifikant ist hingegen der Einfluss der Temperatur, der effektiven Ladungsträgermassen und der Höhe der Schottky-Barriere. Da diese drei Eingangsparameter des betrachteten Systems mit relativ großen Ungenauigkeiten behaftet sind, ist die Bestimmung von physikalischen Parametern aus einzelnen gemessenen Strom-Spannungs-Kennlinien auf die erhoffte Weise nicht möglich. Die Arbeit zeigt auch, dass bereits moderate Veränderungen der Arbeitstemperatur einen bedeutenden Einfluss auf die Strom-Spannungs-Kennlinie haben. Für die Konstruktion von Transistoren mit hoher Stromdichte kann anhand der ermittelten Daten die Verkleinerung der aktiven Region durch Oxidation vorgeschlagen werden. / Charge transport in nanowire-based Schottky-barrier field-effect transistors in the material system Ni2Si/Si is examined by multi-scale simulations. The requirements for the accuracy of the input parameters are determined and predictions about optimum material and device parameters are made. The question is answered, whether the determination of physical parameters from individual measured current-voltage curves is possible? The field effect is described by calculations based on the finite element method and the resulting currents are calculated with a quantum mechanical transport model. In the study of the geometric input parameters it is shown that experimental uncertainties do not drastically affect the current-voltage characteristic, except from the nanowire radius. However, significant is the influence of the temperature, the effective charge carrier mass and the height of the Schottky-barrier. Since these three input parameters are known only with low experimental accuracy for the considered system, the determination of physical parameters from individual measured current-voltage curves is not possible in the expected way. The results also show that moderate changes of the working temperature have a significant influence on the current-voltage characteristic. For the construction of transistors with high current density the reduction of the active region by oxidation is proposed.

High power Gallium Nitride (GaN) based field effect transistors are used in many high power applications from RADARs to communications. These devices dissipate a large amount of power and sustain high electric fields during operation. High power dissipation occurs in the form of heat generation through Joule heating which also results in localized hot spot formation that induces thermal stresses. In addition, because GaN is strongly piezoelectric, high electric fields result in large inverse piezoelectric stresses. Combined with residual stresses due to growth conditions, these effects are believed to lead to device degradation and reliability issues. This work focuses on studying these effects in detail through modeling of Heterostructure Field Effect Transistors (HFETs) and metal oxide semiconductor hetero-structure field effect transistor (MOSHFETs) under various operational conditions. The goal is to develop a thorough understanding of device operation in order to better predict device failure and eventually aid in device design through modeling. The first portion of this work covers the development of a continuum scale model which couples temperature and thermal stress to find peak temperatures and stresses in the device. The second portion of this work focuses on development of a micro-scale model which captures phonon-interactions at the device scale and can resolve local perturbations in phonon population due to electron-phonon interactions combined with ballistic transport. This portion also includes development of phonon relaxation times for GaN. The model provides a framework to understand the ballistic diffusive phonon transport near the hotspot in GaN transistors which leads to thermally related degradation in these devices.

MEMS microphones have been a research topic for the last two and half decades. The state-of-the-art comprises surface mount MEMS microphones in laptops, mobile phones and tablets, etc. The popularity and the commercial success of MEMS microphones is largely due to the steep cost reduction in manufacturing afforded by the mass scale production with microfabrication technology. The current MEMS microphones are de-signed along the lines of traditional microphones that use capacitive transduction with or without permanent charge (electret type microphones use permanent charge of their sensor element). These microphones offer high sensitivity, stability and reasonably at frequency response while reducing the overall size and energy consumption by exploiting MEMS technology. Conceptually, microphones are simple transducers that use a membrane or diaphragm as a mechanical structure which deflects elastically in response to the incident acoustic pressure. This dynamic deflection is converted into an electrical signal using an appropriate transduction technique. The most popular transduction technique used for this application is capacitive, where an elastic diaphragm forms one of the two parallel plates of a capacitor, the fixed substrate or the base plate being the other one. Thus, there are basically two main elements in a microphone { the elastic membrane as a mechanical element, and the transduction technique as the electrical element. In this thesis, we propose and study novel design for both these elements. In the mechanical element, we propose a simple topological change by introducing slits in the membrane along its periphery to enhance the mechanical sensitivity. This simple change, however, has significant impact on the microphone design, performance and its eventual cost. Introduction of slits in the membrane makes the geometry of the structural element non-trivial for response analysis. We devote considerable effort in devising appropriate modeling techniques for deriving lumped parameters that are then used for simulating the system response. For transduction, we propose and study an FET (Field Effect Transistor) coupled micro-phone design where the elastic diaphragm is used as the moving (suspended) gate of an FET and the gate deflection modulated drain current is used in the subthreshold regime of operation as the output signal of the microphone. This design is explored in detail with respect to various design parameters in order to enhance the electrical sensitivity. Both proposed changes in the microphone design are motivated by the possibilities that the microfabrication technology offers. In fact, the design proposed here requires further developments in MEMS technology for reliably creating gaps of 50-100 nm between the substrate and a large 2D structure of the order of a few hundred microns in diameter. In the First part of the thesis, we present detailed simulations of acoustic and squeeze lm domain to understand the effect slits could bring upon the behaviour of the device as a microphone. Since the geometry is nontrivial, we resort to Finite element simulations using commercial packages such as COMSOL Multiphysics and ANSYS in the structural, acoustic and Fluid-structure domains to analyze the behaviour of a microphone which has top plate with nontrivial geometry. On the simulated Finite element data, we conduct low and high frequency limit analysis to extract expressions for the lumped parameters. This technique is well known in acoustics. We borrow this technique of curve Fitting from the acoustics domain and apply it in modified form into the squeeze lm domain. The dynamic behaviour of the entire device is then simulated using the extracted parameters. This helps to simulate the microphone behaviour either as a receiver or as a transmitter. The designed device is fabricated using MEMSCAP PolyMUMPS process (a foundry Polysilicon surface micromachining process). We conduct vibrometer (electrostatic ex-citation) and acoustic characterization. We also study the feasibility of a microphone with slits and the issues involved. The effect of the two dissipation modes (acoustic and squeeze lm ) are quantified with the experimentally determined quality factor. The experimentally measured values are: Resonance is 488 kHz (experimentally determined), low frequency roll-off is 796 Hz (theoretical value) and is 780 Hz as obtained by electrical characterization. The first part of this thesis focusses on developing a comprehensive understanding of the effect of slits on the performance of a MEMS microphone. The presence of slits near the circumference of the clamped plate cause reduction in its rigidity. This leads to an increase in the sensitivity of the device. Slits also cause pressure equalization between the top and bottom of the diaphragm if the incoming sound is at relatively low frequencies. At this frequency, also known as the lower cutoff frequency, the microphone's response starts dropping. The presence of slits also changes the radiation impedance of the plate as well as the squeeze lm damping below the plate. The useful bandwidth of the microphone changes as a consequence. The cavity formed between the top plate and the bottom fixed substrate increases the stiffness of the device significantly due to compression of the trapped air. This effect is more pronounced here because unlike the existing capacitive MEMS microphones, there is no backchamber in the device fabricated here. In the second part of the thesis, we present a novel subthreshold biased FET based MEMS microphone. This biasing of the transistor in the subthreshold region (also called as the OFF-region) offers higher sensitivity as compared to the above threshold region (also called as the ON-region) biasing. This is due to the exponentially varying current with change in the bias voltage in the OFF-region as compared to the quadratic variation in the ON-region. Detailed simulations are done to predict the behaviour of the device. A lumped parameter model of the mechanical domain is coupled with the drain current equations to predict the device behaviour in response to the deflection of the moving gate. From the simulations, we predict that the proposed biasing offers a device sensitive to even sub-nanometer deflection of the flexible gate. As a proof of concept, we fabricate fixed-fixed beams which utilize CMOS-MEMS fabrication. The process involves six lithography steps which involve two CMOS and the remaining MEMS fabrication. The fabricated beams are mechanically characterized for resonance. Further, we carry out electrical characterization for I-V (current-voltage) characteristics. The second part of the thesis focusses on a novel biasing method which circumvents the need of signal conditioning circuitry needed in a capacitive based transduction due to inbuilt amplification. Extensive simulations with equivalent circuit has been carried out to determine the increased sensitivity and the role of various design variables.

There is a compelling need to explore different material options as well as device structures to facilitate smooth transistor scaling for higher speed, higher density and lower power. The enormous potential of nanoelectronics, and nanotechnology in general, offers us the possibility of designing devices with added functionality. However, at the same time, the new materials come with their own challenges that need to be overcome. In this work, we have addressed some of these challenges in the context of quasi-2D Silicon, III-V semiconductor and graphene. Bulk Si is the most widely used semiconductor with an indirect bandgap of about 1.1 eV. However, when Si is thinned down to sub-10nm regime, the quasi-2D nature of the system changes the electronic properties of the material significantly due to the strong geometrical confinement. Using a tight-binding study, we show that in addition to the increase in bandgap due to quantization, it is possible to transform the original in direct bandgap to a direct one. The effective masses at different valleys are also shown to vary uniquely in an anisotropic way. This ultra-thin Si, when used as a channel in a double gate MOSFET structure, creates so called “volume in version” which is extensively investigated in this work. It has been found that the both the quantum confinement as well as the gating effect play a significant role in determining the spatial distribution of the charge, which in turn has an important role in the characteristics of transistor. Compound III-V semiconductors, like Inx Ga1-xAs, provide low effective mass and low density of states. This, when coupled with strong confinement in a nanowire channel transistor, leads to the “Ultimate Quantum Capacitance Limit” (UQCL) regime of operation, where only the lowest subband is occupied. In this regime, the channel capacitance is much smaller than the oxide capacitance and hence dominates in the total gate capacitance. It is found that the gate capacitance change qualitatively in the UQCL regime, allowing multi-peak, non-monotonic capacitance-voltage characteristics. It is also shown that in an ideal condition, UQCL provides improved current saturation, on-off ratio and energy-delay product, but a degraded intrinsic gate delay. UQCL shows better immunity towards series resistance effect due to increased channel resistance, but is more prone to interfacial traps. A careful design can provide a better on-off ratio at a given gate delay in UQCL compared to conventional MOSFET scenario. To achieve the full advantages of both FinFET and HEMT in III-V domain, a hybrid structure, called “HFinFET” is proposed which provides excellent on performance like HEMT with good gate control like FinFET. During on state, the carriers in the channel are provided using a delta-doped layer(like HEMT) from the top of a fin-like non-planar channel, and during off state, the gates along the side of the fin(like FinFET) help to pull-off the carriers from the channel. Using an effective mass based coupled Poisson-Schrodinger simulation, the proposed structure is found to outperform the state of the art planar and non-planar MOSFETs. By careful optimization of the gate to source-drain underlap, it is shown that the design window of the device can be increased to meet ITRS projections at similar gate length. In addition, the performance degradation of HFinFET in presence of interface traps has been found to be significantly mitigated by tuning the underlap parameter. Graphene is a popular 2D hexagonal carbon crystal with extraordinary electronic, mechani-cal and chemical properties. However, the zero band gap of grapheme has limited its application in digital electronics. One could create a bandgap in grapheme by making quasi-1D strips, called nanoribbon. However, the bandgap of these nanoribbons depends on the the type of the edge, depending on which, one can obtain either semiconducting or metallic nanoribbon. It has been shown that by the application of an external transverse field along the sides of a nanoribbon, one could not only modulate the magnitude of the bandgap, but also change it from direct to indirect. This could open up interesting possibilities for novel electronic and optoelectronic applications. The asymmetric potential distribution inside the nanoribbon is found to result in such direct to indirect bandgap transition. The corresponding carrier masses are also found to be modulated by the external field, following a transition from a“slow”electron to a“fast” electron and vice-versa. Experimentally, it is difficult to control the bandgap in nanoribbons as precise edge control at nanometer scale is nontrivial. One could also open a bandgap in a bilayer graphene, by the application of vertical electric field, which has raised a lot of interest for digital applications. Using a self-consistent tight binding theory, it is found that, inspite of this bandgap opening, the intrinsic bias dependent electronic structure and the screening effect limit the subthreshold slope of a metal source drain bilayer grapheme transistor at a relatively higher value-much above the Boltzmann limit. This in turn reduces the on-off ratio of the transistor significantly. To overcome this poor on-off ratio problem, a semiconductor source-drain structure has been proposed, where the minority carrier injection from the drain is largely switched off due to the bandgap of the drain. Using a self-consistent Non-Equilibrium Green’s Function(NEGF) approach, the proposed device is found to be extremely promising providing unipolar grapheme devices with large on-off ratio, improved subthreshold slope and better current saturation. At high drain bias, the transport properties of grapheme is extremely intriguing with a number of nontrivial effects. Optical phonons in monolayer grapheme couple with carriers in a much stronger way as compared to a bilayer due to selection rules. However, it is difficult to experimentally probe this through transport measurements in substrate supported grapheme as the surface polar phonons with typical low activation energy dominates the total scattering. However, at large drain field, the carriers obtain sufficient energy to interact with the optical phonons, and create so called ‘hot phonons’ which we have experimentally found to result in a negative differential conductance(NDC). The magnitude of this NDC is found to be much stronger in monolayer than in bilayer, which agrees with theoretical calculations. This NDC has also been shown to be compensated by extra minority carrier injection from drain at large bias resulting in an excellent current saturation through a fundamentally different mechanism as compared to velocity saturation. A transport model has been proposed based on the theory, and the experimental observations are found to be in agreement with the model.

This thesis describes the conductivity fluctuations or noise measurements in graphenebased field effect transistors. The main motivation was to study the effect of disorder on the electronic transport in graphene. In chapter 4, we report the noise measurements in graphene field effect (GraFET) transistors with varying layer numbers. We found that the density dependence of noise behaves oppositely for single and multilayer graphene. An analytical model has been proposed to understand the microscopic mechanism of noise in GraFETs, which reveals that noise is intimately connected to the band structure of graphene. Our results outline a simple portable method to separate the single layer devices from multi layered ones. Chapter 5 discusses the noise measurements in two systems with a bandgap: biased bilayer graphene and graphene nanoribbon. We show that noise is sensitive to the presence of a bandgap and becomes minimum when the bandgap is zero. At low temperature, mesoscopic graphene devices exhibit universal conductance fluctuations (UCF) arising due to quantum interference effect. In chapter 6, we have studied UCF in single layer graphene and show that it can be sensitive to the presence of various physical symmetries. We report that time reversal symmetry exists in graphene at low temperature and, for the first time, we observed enhanced UCF at lower carrier density where the scattering is dominated by the long-range Coulomb scattering. Chapter 7 presents the transport and noise measurements in single layer graphene in the quantum Hall regime. At ultra-low temperature several broken symmetry states appear in the lowest Landau level, which originate possibly due to strong electron-electron interactions. Our preliminary noise measurements in the quantum Hall regime reveal that the noise is sensitive to the bulk to edge transport and can be a powerful tool to investigate these new quantum states.

This thesis work contains electrical transport and low frequency (1/f) noise measurements in ultrathin graphene and Molybdenum disulphide (MoS2) field effect transistors (FET). From the measurements, We mainly focus on the origin of disorder in both the materials. To address the orgin of disorder in graphene, we study single and bilayer graphene-FET devices on SiO2 substrate. We observe that both conductivity and mobility are mainly determined by substrate induced long range, short range, and polar phonon scattering. For further confirmation, we fabricate suspended graphene devices which show extremely high mobility. We find that, in contrast to substrate-supported graphene, conductivity and mobility in suspended graphene are governed by the longitudinal acoustic phonon scattering at high temperature and the devices reach a ballistic limit at low temperature. We also conduct low frequency 1/f noise measurements, known to be sensitive to disorder dynamics, to extract more information on the nature of disorder. The measurements are carried out both in substrate-supported and suspended graphene devices. We find that 1/f noise in substarted graphene is mainly determined by the trap charges in the SiO2 substrate. On the other hand, noise behaviour in suspended graphene devices can not be explained with trap charge dominated noise model. More-over, suspended devices exhibit one order of magnitude less noise compared to graphene on SiO2 substrate. We believe noise in suspended graphene devices probably originate from metal-graphene contact regions. In the second part of our work, We present low temperature electrical transport in ultrathin MoS2 fields effect devices, mechanically exfoliated onto Si/SiO2 substrate. Our experiments reveal that the electronic states in MoS2 are localized well up to the room temperature over the experimentally accessible range of gate voltage. This manifests in two dimensional (2D) variable range hopping (VRH) at high temperatures, while below ~ 30 K the conductivity displays oscillatory structures in gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T0) of VRH and gate voltage dependence of conductivity, we suggest that the charged impurities are the dominant source of disorder in MoS2. To explore the origin of the disorder, we perform temperature dependent I - V measurements at high source-drain bias. These measurements indicate presence of an exponentially distributed trap states in MoS2 which originate from the structural inhomogeneity. For more detailed investigation, we employ 1/f noise which further confirms possible presence of structural disorder in the system. The origin of the localized states is also investigated by spectroscopic studies, which indicate a possible presence of metallic 1T-patches inside semiconducting 2H phase. From all these evidences, we suggest that the disorder is internal, and achieving high mobility in MoS2 FET requires a greater level of crystalline homogeneity.

No description available.

Thesis (PhD (Electric and Electronic Engineering))--University of Stellenbosch, 2007. / There is increasing use of commercial components in space technology and it is important to recognize that the space radiation environment poses the risk of permanent malfunction due to radiation. Therefore, the integrated circuits used for spacecraft electronics must be resistant to radiation. The effect of using the MOSFET device in a radiation environment is that the gate oxide becomes ionized by the dose it absorbs due to the radiation induced trapped charges in the gate-oxide. The trapped charges in the gate-oxide generate additional space charge fields at the oxide-substrate interface. After a sufficient dose, a large positive charge builds up, having the same effect as if a positive voltage was applied to the gate terminal. Therefore, the transistor source to drain current can no longer be controlled by the gate terminal and the device remains on permanently resulting in device failure. There are four processes involved in the radiation response of MOS devices. First, the ionizing radiation acts with the gate oxide layer to produce electron-hole pairs. Some fraction of the electron-hole pairs recombine depending on the type of incident particle and the applied gate to substrate voltage, i.e. the electric field. The mobility of the electron is orders of magnitude larger than that of the holes in the gate oxide, and is swept away very quickly in the direction of the gate terminal. The time for the electrons to be swept away is on the order of 1ps. The holes that escape recombination remain near their point of origin. The number of these surviving holes determines the initial response of the device after a short pulse of radiation. The cause of the first process, i.e. the presence of the electric field, is the main motivation for design method described in this dissertation. The second process is the slow transport of holes toward the oxide-silicon interface due to the presence of the electric field. When the holes reach the interface, process 3, they become captured in long term trapping sites and this is the main cause of the permanent threshold voltage shift in MOS devices. The fourth process is the buildup of interface states in the substrate near the interface The main contribution of this dissertation is the development of the novel Switched Modular Redundancy (SMR) method for mitigating the effects of space radiation on satellite electronics. The overall idea of the SMR method is as follows: A charged particle is accelerated in the presence of an electric field. However, in a solid, electrons will move around randomly in the absence of an applied electric field. Therefore if one averages the movement over time there will be no overall motion of charge carriers in any particular direction. On applying an electric field charge carriers will on average move in a direction aligned with the electric field, with positive charge carriers such as holes moving in the direction of field, and negative charge carriers moving in the opposite direction. As is the case with process one and two above. It is proposed in this dissertation that if we apply the flatband voltage (normaly a zero bias for the ideal NMOS transistor) to the gate terminal of a MOS transistor in the presence of ionizing radiation, i.e. no electric field across the gate oxide, both the free electrons and holes will on average remain near their point of origin, and therefore have a greater probability of recombination. Thus, the threshold voltage shift in MOS devices will be less severe for the gate terminal in an unbiased condition. The flatband conditions for the real MOS transistor is discussed in appendix E. It was further proposed that by adding redundancy and applying a resting policy, one can significantly prolong the useful life of MOS components in space. The fact that the rate of the threshold voltage shift in MOS devices is dependant on the bias voltage applied to the gate terminal is a very important phenomenon that can be exploited, since we have direct control and access to the voltage applied to the gate terminal. If for example, two identical gates were under the influence of radiation and the gate voltage is alternated between the two, then the two gates should be able to withstand more total dose radiation than using only one gate. This redundancy could be used in a circuit to mitigate for total ionizing dose. The SMR methodology would be to duplicate each gate in a circuit, then selectively only activating one gate at a time allowing the other to anneal during its off cycle. The SMR algorithm was code in the “C” language. In the proposed design methodology, the design engineer need not be concerned about radiation effects when describing the hardware implementation in a hardware description language. Instead, the design engineer makes use of conventional design techniques. When the design is complete, it is synthesized to obtain the gate level netlist in edif format. The edif netlist is converted to structural VHDL code during synthesis. The structural VHDL netlist is fed into the SMR “C” algorithm to obtain the identical redundant circuit components. The resultant file is also a structural VHDL netlist. The generated VHDL netlist or SMR circuit can then be mapped to a Field Programmable Gate Array (FPGA). Spacecraft electronic designers increasingly demand high performance microprocessors and FPGAs, because of their high performance and flexibility. Because FPGAs are reprogrammable, they offer the additional benefits of allowing on-orbit design changes. Data can be sent after launch to correct errors or to improve system performance. System including FPGAs covers a wide range of space applications, and consequently, they are the object of this study in order to implement and test the SMR algorithm. We apply the principles of reconfigurable computing to implement the Switched Modular Redundancy Algorithm in order to mitigate for Total Ionizing Dose (TID) effects in FPGA’s. It is shown by means of experimentation that this new design technique provides greatly improved TID tolerance for FPGAs. This study was necessary in order to make the cost of satellite manufacturing as low as possible by making use of Commercial off-the-shelf (COTS) components. However, these COTS components are very susceptible to the hazards of the space environment. One could also make use of Radiation Hard components for the purpose of satellite manufacturing, however, this will defeat the purpose of making the satellite manufacturing cost as low as possible as the cost of the radiation hard electronic components are significantly higher than their commercial counterparts. Added to this is the undesirable fact that the radiation hard components are a few generations behind as far as speed and performance is concerned, thus providing even greater motivation for making use of Commercial components. Radiation hardened components are obtained by making use of special processing methods in order to improve the components radiation tolerance. Modifying the process steps is one of the three ways to improve the radiation tolerance of an integrated circuit. The two other possibilities are to use special layout techniques or special circuit and system architectures. Another method, in which to make Complementary Metal Oxide Silicon (CMOS) circuits tolerant to ionizing radiation is to distribute the workload among redundant modules (called Switched Modular Redundancy above) in the circuit. This new method will be described in detail in this thesis.