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This dissertation will outline solution processable materials and fabrication techniques to manufacture flexible electronic devices from them. Conductive ink formulations and inkjet printing of gold and silver on plastic substrates were examined. Line patterning and mask printing methods were also investigated as a means of selective metal deposition on various flexible substrate materials. These solution-based manufacturing methods provided deposition of silver, gold and copper with a controlled spatial resolution and a very high electrical conductivity. All of these procedures not only reduce fabrication cost but also eliminate the time-consuming production steps to make basic electronic circuit components. Solution processable semiconductor materials and their composite films were also studied in this research. Electrically conductive, ductile, thermally and mechanically stable composite films of polyaniline and sulfonated poly (arylene ether sulfone) were introduced. A simple chemical route was followed to prepare composite films. The electrical conductivity of the films was controlled by changing the weight percent of conductive filler. Temperature dependent DC conductivity studies showed that the Mott three dimensional hopping mechanism can be used to explain the conduction mechanism in composite films. A molecular interaction between polyaniline and sulfonated poly (arylene ether sulfone) has been proven by Fourier Transform Infrared Spectroscopy and thermogravimetric analysis. Inkjet printing and line patterning methods also have been used to fabricate polymer resistors and field effect transistors on flexible substrates from poly-3-4-ethyleneoxythiophene/poly-4-sytrensulfonate. Ethylene glycol treatment enhanced the conductivity of line patterned and inkjet printed polymer thin films about 900 and 350 times, respectively. Polymer field effect transistors showed the characteristics of traditional p-type transistors. Inkjet printing technology provided the transfer of semiconductor polymer on to flexible substrates including paper, with high resolution in just seconds. / Ph. D.

Gallium arsenide MESFETS require protective passivation at several steps in their fabrication. A common film used for device passivation is silicon nitride. This passivation film is deposited on gallium arsenide substrates by chemical vapor deposition techniques and possesses high intrinsic stress. The stresses arise from the difference in the gallium arsenide and silicon nitride material properties, such as coefficient of expansion, density, modulus, and deposition temperature. The stress has been shown to cause electrical performance shifts in GaAs MESFET structures due to the piezoelectric nature of the gallium arsenide lattice. This work develops a framework of mathematical models and experimental techniques by which the intrinsic stresses in the film and the GaAs substrate can be evaluated. Specifically, this work details the stress field and the electrical performance shifts in fully planarized self aligned gate GaAs MESFETS. The devices were 10 micron gate periphery FET devices with a 0.4 micron etched gate length. The test devices included both enhancement mode and depletion mode structures. The major contributors to the stress in GaAs devices was found to be the intrinsic stress effects of the silicon nitride passivation film. An externally applied stress, such as that applied to a package base that a typical GaAs device would be mounted into for actual service, was found to be insufficient to cause significant shifts in the device performance. The package body effectively reduces the transfer of stress to the device body and thereby minimizes the piezoelectric effect. The intrinsic stress effects are due to the deposition of the film itself. This intrinsic stress was found to have a significant effect on the device electrical characteristics. The stress was found to permanently shift the threshold voltage and current in 10 micron self aligned gate MESFETS. The shift was measured at 26 millivolts per 100 MPa film stress for depletion mode devices and 23 millivolts per 100 MPa for enhancement mode devices. For the maximum measured biaxial stress of -0.54 MPa in the gallium arsenide, the total measured shift was 140 millivolts. The level of shift is similar to that reported by earlier researchers. This piezoelectric shift has been modeled, with model predictions within 50/0 of the experimental values for the DFET devices and 11 % for the EFET devices. / Ph. D.

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D.

Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for next-generation Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C's fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for high-performance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. / Master of Science

The continued scaling of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has led to a rapid increase in compute power. Resulting from increases in device densities and advances in materials and transistor design, integrated circuit (IC) performance has continued to improve while operational power (VDD) has been substantially reduced. However, as feature sizes approach the atomic length scale, fundamental limitations in switching characteristics (such as subthreshold slope, SS, and OFF-state power dissipation) pose key technical challenges moving forward. Novel material innovations and device architectures, such as group IV and III-V materials and tunnel field-effect transistors (TFETs), have been proposed as solutions for the beyond Si era. TFETs benefit from steep switching characteristics due to the band-to-band tunneling injection of carriers from source to channel. Moreover, the narrow bandgaps of III-V and germanium (Ge) make them attractive material choices for TFETs in order to improve ON-state current and reduce SS. Further, Ge grown on InₓGa₁₋ₓAs experiences epitaxy-induced strain (ε), further reducing the Ge bandgap and improving carrier mobility. Due to these reasons, the ε-Ge/InₓGa₁₋ₓAs system is a promising candidate for future TFET architectures. In addition, the ability to tune the bandgap of Ge via strain engineering makes ε-Ge/InₓGa₁₋ₓAs heterostructures attractive for nanoscale group IV-based photonics, thereby benefitting the monolithic integration of electronics and photonics on Si. This research systematically investigates the material, optical, and heterointerface properties of ε-Ge/InₓGa₁₋ₓAs heterostructures on GaAs and Si substrates. The effect of strain on the heterointerface band alignment is comprehensively studied, demonstrating the ability to modulate the effective tunneling barrier height (Ebeff) and thus the threshold voltage (VT), ON-state current, and SS in future ε-Ge/InₓGa₁₋ₓAs TFETs. Further, band structure engineering via strain modulation is shown to be an effective technique for tuning the emission properties of Ge. Moreover, the ability to heterogeneously integrate these structures on Si is demonstrated for the first time, indicating their viability for the development of next-generation high performance, low-power logic and photonic integrated circuits on Si. / Master of Science

京都大学 / 新制・課程博士 / 博士(工学) / 甲第25303号 / 工博第5262号 / 京都大学大学院工学研究科物質エネルギー化学専攻 / (主査)教授 陰山 洋, 教授 作花 哲夫, 教授 田中 勝久 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

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