The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

<p>The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.</p><p>Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.</p>

The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs. Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

No description available.

This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V. / text

No description available.

La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz. / Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz.

<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p> / Report code: LiU-Tek-Lic-2005:68.