This thesis presents the design of a 2.4 GHz sub-integer-N PLL for IEEE 802.llb/g WLAN applications. The proposed PLL not only acquires the advantages of the integer-N PLL, such as simple structure and good spurious performance, but also offers some benefits (for example, faster settling time and better phase noise performance) as in the fractional-N PLL design. In this design, a novel quadrature-input programmable fractional frequency divider provides fractional division ratio in steps of 0.5 by the phase-switching technique. Its key building block is a dual divide-by-4 injection-locked frequency divider (ILFD), which is realized by coupling two conventional divide-by-4 ILFDs. Two different coupling schemes are introduced, namely the cross-coupling type and coherent-coupling type. In both schemes, symmetric configuration is maintained and hence does not degrade the PLL output phase quadrature accuracy. Furthermore, the generated phase pattern for phase switching is uniquely defined, which simplifies the phase-switching circuitry and suppresses the possibility of incorrect frequency division due to glitches. / To demonstrate the feasibility of the two proposed coupling methodologies, two subinteger-N PLLs with different fractional frequency dividers have been fabricated in a 0.35 11m standard CMOS process. In design 1, the dual divide-by-4 ILFD in the fractional frequency divider is implemented with the cross-coupling scheme while the coherent-coupling scheme is used in design 2. The measured spurious tones of both designs are under -64 dBc and their measured phase noise at 1 MHz frequency offset is less than -115 dBc/Hz. The two proposed frequency synthesizers settle at approximately 32 us and their phase mismatches of the quadrature outputs are better than 38 dB (characterized by image rejection ratio). Moreover, both designs individually occupy a chip area as small as 0.70 mm2. At a supply of 1.5 V, the total power consumption for each design is below 24.1 mW. / Wireless local area networks (WLANs) are being extensively deployed since their introduction in the late 1990s. Low cost, high performance frequency synthesizers are indispensable in WLAN telecommunication systems. Meanwhile, integer-N phase-locked loop (PLL) architecture is commonly chosen due to its low circuit complexity and clean output spectrum with few spurs. However, designers have to face the tradeoffs between frequency resolution, phase noise performance and switching time. To solve the above dilemma, fractional-N PLL architecture is proposed, but fractional spurs emerge in the output spectrum, degrading the spectrum purity. Sub-integer-N PLL is thus a compromise between the integer-N and fractional-N PLL. Its structure is same as that of the integer-N while fractional division is achieved by a fractional frequency divider that is not relied on time-varying modulus control as in the fractional-N PLL. / Chang, Ka Fai. / Adviser: Kwok-Keung Cheng. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 176-188). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Today a growing number of applications in design engineering, production and environmental testing, and system service require specific analog waveforms and digital patterns. Such requirements are neither satisfactorily nor easily met by the use of standard function or single purpose, custom generators. Traditional methods of waveform generation suffer from undesirable complexity or mediocre performance and are otherwise limited. For the majority of arbitrary waveform generation applications, including medical engineering, modal analysis and electronic engineering, direct digital synthesis techniques are satisfactory. Direct digital synthesis, based generally on periodic retrieval of predetermined amplitude values, may be used to 2 generate such waveforms. Within the limits imposed by the system's maximum sample rate and the Nyquist criteria, any waveform may be produced using these techniques. The objective of this inquiry, within a particular set of constraints, is to extend the cost/performance envelope of direct digital synthesis techniques for the generation of arbitrary waveforms. Performance is enhanced, particularly in the areas of output bandwidth and signal purity.

Silicon Germanium BiCMOS technology has been demonstrated as an ideal platform for highly integrated systems requiring both high performance analog and RF circuits as well as large-scale digital functionality. Frequency synthesizers are ideal candidates for this technology because the mixed-signal nature of modern frequency synthesis designs fundamentally requires both digital and analog signal processing. This research targets three areas to improve SiGe frequency synthesizers. A majority of this work focuses on applying SiGe frequency synthesizers to extreme environment applications such as space, where low temperatures and ionizing radiation are significant design issues to contend with. A second focus area involves using SiGe HBTs to minimize noise in frequency synthesizer circuits. Improved low frequency "pink" noise in SiGe HBTs provide a significant advantage over CMOS devices, and frequency synthesis circuits are significantly affected by this type of noise. However, improving thermal "white" noise is also considered. Finally, an analysis of AM-PM distortion is considered for SiGe HBTs. The studies presented focus on identifying the physical mechanisms of observed phenomena, such as single event transients or phase noise characteristics in oscillators. The ultimate goal of this research is to provide a reference of effective design parameters for circuit and system designers seeking to take advantage of the properties of SiGe device physics.

In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).

Thesis (M.App.Sc.) - Carleton University, 2002. / Includes bibliographical references (p. 215-223). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 143-146). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 130-137). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 54). Also available in electronic format on the Internet.

Thesis (M.S.)--Oregon State University, 2004. / Typescript (photocopy). Includes bibliographical references (leaves 61-63). Also available on the World Wide Web.

Thesis (Ph. D.)--Carleton University, 1999. / Also available in electronic format on the Internet.