Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.

Neste trabalho é desenvolvida uma ferramenta de dimensionamento de portas lógicas para circuitos integrados, utilizando técnicas de otimização de problemas baseadas em Programação Geométrica (PG). Para dimensionar as portas lógicas de um circuito, primeiramente elas são modeladas usando o modelo de chaves RC e o atraso é calculado usando o modelo de Elmore, que produz funções posinomiais possibilitando a resolução do problema por programação geométrica. Para cada porta é utilizado um fator de escala que multiplica a largura dos seus transistores, onde as variáveis que representam os fatores de escala são as variáveis de otimização do problema. O dimensionador de portas desenvolvido neste trabalho é para circuitos CMOS e é parametrizável para diversas tecnologias de fabricação CMOS. Além disso, a otimização pode ser feita de duas maneiras, minimizando o atraso restringindo a área do circuito ou, minimizando a área e restringindo o atraso do circuito. Para testar o dimensionador de portas foram consideradas duas tecnologias de fabricação diferentes, 45nm e 350nm, onde os resultados foram comparados com o dimensionamento fornecido em uma típica biblioteca de células. Para a tecnologia de 45nm, o dimensionamento de portas minimizando o atraso, fornecido pelo método proposto neste trabalho, obteve uma redução, em média, de 21% no atraso, mantendo a mesma área e potência do dimensionamento fornecido pela biblioteca de standard cells. Após, fez-se uma otimização de área, ainda considerando a tecnologia de 45nm, onde o atraso é restrito ao valor encontrado na minimização de atraso. Essa otimização secundária resultou em uma redução média de 28,2% em área e 27,3% em potência, comparado aos valores dados pela minimização de atraso. Isso mostra que, ao fazer a minimização de atraso seguida da minimização de área, ou vice-versa, encontra-se o menor atraso e a menor área para o circuito, onde uma otimização não impede a outra. As mesmas otimizações foram feitas para a tecnologia de 350nm, onde o dimensionamento de portas considerando a minimização de atraso obteve uma redução, em média, de 4,5% no atraso, mantendo os valores de consumo de potência e área semelhantes aos valores dados pelo dimensionamento fornecido em uma biblioteca comercial de células em 350nm. A minimização de área, feita em seguida, restringindo o atraso ao valor dado pela minimização de atraso foi capaz de reduzir a área em 29,9%, em média, e a potência em 28,5%, em média. / In this work a gate sizing tool is developed using problem optimization techniques based on Geometric Programming. To size the gates in a circuit, first, the logic gates are modeled using the RC switch model and the delay is calculated using Elmore delay model, which produces posynomial functions, enabling the problem solution by geometric programming. For each port a scale factor is set that multiplies the transistors width, where the variables that represent the scale factors are the problem optimization variables. Gate sizing developed in this work is for CMOS circuits and is configurable to several CMOS manufacturing technologies. Moreover, the optimization can be done in two ways, minimizing delay restricting area or by minimizing area restricting circuit delay. In this work, gate sizing tests were made considers two different technologies, 45nm and 350nm, where the results were compared with the sizing available in a typical standard-cell library. For 45nm technology, the gate sizing proposed in this work considering delay minimization, obtained a reduction, in average, of 21% in delay, keeping the same area and power values of the sizing provided by standard-cells library. After, it was made an area optimization restricting delay to the value found at delay minimization. This optimization allowed an average reduction of 28.2% in area and 27.3% in power consumption, compared to the values obtained by delay minimization. This shows that by making the minimization of delay followed by the minimization of area, the smallest delay and the smallest area for the circuit is found, where an optimization does not prevent the other. The same optimizations were made for 350nm technology, where gate sizing considering delay minimization achieved a reduction, on average, of 4.5% in delay, keeping power consumption and area values similar to the values given using the sizes found in a commercial standard-cell library in 350nm. The area minimization, restricting delay to the value given by delay minimization, was able to reduce the area in 29.9% and power at 28.5%, on average.

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In the field of VLSI circuit optimization, the scaling of semiconductor devices has led to the miniaturization of the feature sizes resulting in a significant increase in the integration density and size of the circuits. At the nanometer level, due to the effects of manufacturing process variations, the design optimization process has transitioned from the deterministic domain to the stochastic domain, and the inter-relationships among the specification parameters like delay, power, reliability, noise and area have become more intricate. New methods are required to examine these metrics in a unified manner, thus necessitating the need for multi-metric optimization. The optimization algorithms need to be accurate and efficient enough to handle large circuits. As the size of an optimization problem increases significantly, the ability to cluster the design metrics or the parameters of the problem for computational efficiency as well as better analysis of possible trade-offs becomes critical. In this dissertation research, several utilitarian methods are investigated for variation aware multi-metric optimization in VLSI circuit design and spatial pattern clustering. A novel algorithm based on the concepts of utility theory and risk minimization is developed for variation aware multi-metric optimization of delay, power and crosstalk noise, through gate sizing. The algorithm can model device and interconnect variations independent of the underlying distributions and works by identifying a deterministic linear equivalent model from a fundamentally stochastic optimization problem. Furthermore, a multi-metric gate sizing optimization framework is developed that is independent of the optimization methodology, and can be implemented using any mathematical programming approach. It is generalized and reconfigurable such that the metrics can be selected, removed, or prioritized for relative importance depending upon the design requirements. In multi-objective optimization, the existence of multiple conflicting objectives makes the clustering problem challenging. Since game theory provides a natural framework for examining conflicting situations, a game theoretic algorithm for multi-objective clustering is introduced in this dissertation research. The problem of multi-metric clustering is formulated as a normal form multi-step game and solved using Nash equilibrium theory. This algorithm has useful applications in several engineering and multi-disciplinary domains which is illustrated by its mapping to the problem of robot team formation in the field in multi-emergency search and rescue. The various algorithms developed in this dissertation achieve significantly better optimization and run times as compared to other methods, ensure high utility levels, are deterministic in nature and hence can be applied to very large designs. The algorithms have been rigorously tested on the appropriate benchmarks and data sets to establish their efficacy as feasible solution methods. Various quantitative sensitivity analysis have been performed to identify the inter-relationships between the various design parameters.

Technology scaling has increased the transistor's susceptibility to process variations in nanometer very large scale integrated (VLSI) circuits. The effects of such variations are having a huge impact on performance and hence the timing yield of the integrated circuits. The circuit optimization objectives namely power, area, and delay are highly correlated and conflicting in nature. The inception of variations in process parameters have made their relationship intricate and more difficult to optimize. Traditional deterministic methods ignoring variation effects negatively impacts timing yield. A pessimistic worst case consideration of variations, on the other hand, can lead to severe over design. In this context, there is a strong need for re-invention of circuit optimization methods with a statistical perspective. In this dissertation, we model and develop novel variation aware solutions for circuit optimization methods such as gate sizing, timing based placement and buffer insertion. The uncertainty due to process variations is modeled using interval valued fuzzy numbers and a fuzzy programming based optimization is proposed to improve circuit yield without significant over design. In addition to the statistical optimization methods, we have proposed a novel technique that dynamically detects and creates the slack needed to accommodate the delay due to variations. The variation aware gate sizing technique is formulated as a fuzzy linear program and the uncertainty in delay due to process variations is modeled using fuzzy membership functions. The timing based placement technique, on the other hand, due to its quadratic dependence on wire length is modeled as nonlinear programming problem. The variations in timing based placement are modeled as fuzzy numbers in the fuzzy formulation and as chance constraints in the stochastic formulation. Further, we have proposed a piece-wise linear formulation for the variation aware buffer insertion and driver sizing (BIDS) problem. The BIDS problem is solved at the logic level, with look-up table based approximation of net lengths for early variation awareness.In the context of dynamic variation compensation, a delay detection circuit is used to identify the uncertainty in critical path delay. The delay detection circuit controls the instance of data capture in critical path memory flops to avoid a timing failure in the presence of variations. In summary, the various formulation and solution techniques developed in this dissertation achieve significantly better optimization compared to related works in the literature. The proposed methods have been rigorously tested on medium and large sized benchmarks to establish the validity and efficacy of the solution techniques.

The continuous scaling of interconnect wires in deep submicron (DSM)circuits result in increased interconnect delay, power and crosstalk noise. In this dissertation, we address the problem of multi-metric optimization at post layout level in the design of deep submicron designs and develop a game theoretic framework for its solution. Traditional approaches in the literature can only perform single metric optimization and cannot handle multiple metrics. However, in interconnect optimization, the simultaneous optimization of multiple parameters such as delay, crosstalk noise and power is necessary and critical. Thus, the work described in this dissertation research addressing multi-metric optimization is an important contribution.Specifically, we address the problems of simultaneous optimization of interconnect delay and crosstalk noise during (i) wire sizing (ii) gate sizing (iii) integrated gate and wire sizing, and (iv) gate sizing considering process variations. Game the ory provides a natural framework for handling conflicting situations and allows optimization of multiple parameters. This property is exploited in modeling the simultaneous optimization of various design parameters such as interconnect delay, crosstalk noise and power, which are conflicting in nature. The problem of multi-metric optimization is formulated as a normal form game model and solved using Nash equilibrium theory. In wire sizing formulations, the net segments within a channel are modeled as the players and the range of possible wire sizes forms the set of strategies. The payoff function is modeled as (i) the geometric mean of interconnect delay andcrosstalk noise and (ii) the weighted-sum of interconnect delay, power and crosstalk noise, in order to study the impact of different costfunctions with two and three metrics respectively. In gate sizing formulations, the range of possible gate sizes is modeled as the set of strategies and the payoff function is modeled as the geome tric mean of interconnect delay and crosstalk noise. The gates are modeled as the players while performing gate sizing, whereas, the interconnect delay and crosstalk noise are modeled as players for integrated wire and gate sizing framework as well as for statistical gate sizing under the impact of process variations.The various algorithms proposed in this dissertation (i) perform multi-metric optimization (ii) achieve significantly better optimization and run times than other methods such as simulated annealing, genetic search, and Lagrangian relaxation (iii) have linear time and space complexities, and hence can be applied to very large SOC designs, and (iv) do not require rerouting or incur any area overhead. Thecomputational complexity analysis of the proposed algorithms as well as their software implementations are described, and experimental results are provided that establish the efficacy of the proposed algorithms.