No description available.

Using GaAs HBT provided by AWSC to construct Gummel Poon static model.then using the GaAs HBT processing of GCS to design MMIC power amplifier for the 1.9~2.0 GHz PCS system. This power amplifier exhibits an output power of 27dBm and a power added efficiency as high as 32% at an operation voltage of 3.4V.

Dissertation (Ph.D.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.

No description available.

No description available.

No description available.

This thesis researchs the design of quadrature modulator consists of 120MHz quadrature modulator that is fabricated using hybrid elements and print circuit board (PCB) technology for digital signal generator and quadrature modulator monolithic-microwave integrated-circuit (MMIC) that is fabricated using GaAs heterojunction bipolar transistor (HBT) technology for Personal Communication Service (PCS) applications. The 120MHz quadrature modulator incorporates power divider/combiner, phase shifter and doubly balanced mixer; the design architecture, principle and measurement results of division are presented in this thesis. A quadrature modulator is implemented by combining every division and measures specifications accurately, comparing with that of Agilent ESG-D series digital signal generator with the same carrier frequency and digital modulation. The quadrature modulator MMIC for PCS applications incorporates phase shifter, Gilbert cell mixer, differential to single-ended converter and RF amplifier at output; the design architecture, principle and simulation results of division are presented in this thesis. A quadrature modulator is integrated by combining every division and simulates parameters strictly.For troublesome specification measurement of quadrature modulator, this thesis also presents measurement method and instrument setup detailedly.

This thesis proposes a modified inductively degenerated common-emitter low-noise amplifier. To add a series-shunt feedback capacitance in series to the base of the cascode transistor for increasing the load impedance of the common-emitter transistor and enhancing the Miller effect, it is applied to improve the circuit¡¦s performance. By thoroughly studying the Miller effect for the input matching, noise, and linearity analysis and derivation of the modified structure, the theoretical analysis and experiments demonstrate the improved linearity and well noise performance. In addition, the proposed method is presented with the good figure of merit. The proposed method is presented in a hybrid circuit with the NEC 2S5010 NPN transistor for 900 MHz applications. It demonstrates that this method improves the linearity and the figure of merit has been increased by 50 to 70 percent. Moreover, the novel low noise amplifier is designed with a 0.35£gm SiGe BiCMOS process supported by the TSMC for 5.7 GHz WLAN band applications. It is found that the circuit has the characteristic of IM3 nonlinearity cancellation because the cascode transistor eliminates the third-order intermodulation genaerated by the common-emitter transistor. This thesis establishes a realizable method for high-linearity low-noise amplifier.

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographic references (p.64-66).

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第16862号 / 工博第3583号 / 新制||工||1541(附属図書館) / 29537 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 准教授 浅野 卓 / 学位規則第4条第1項該当