Recent advances in medical imaging have greatly improved the success of cardiovascular and intracardiac interventions. This research aims to improve capacitive micromachined ultrasonic transducers (CMUT) based imaging catheters for intravascular ultrasound (IVUS) and intra-cardiac echocardiography (ICE) for 3-D volumetric imaging through integration of high-k thin film material into the CMUT fabrication and array design. CMUT-on-CMOS integration has been recently achieved and initial imaging of ex-vivo samples with adequate dynamic range for IVUS at 20MHz has been demonstrated; however, for imaging in the heart, higher sensitivities are needed for imaging up to 4-5 cm depth at 20MHz and deeper at 10MHz. Consequently, one research goal is to design 10-20MHz CMUT arrays using integrated circuit (IC) compatible micro fabrication techniques and optimizing transducer performance through high-k dielectrics such as hafnium oxide (HfO2). This thin film material is electrically characterized for its dielectric properties and thermal mechanical stress is measured. Experiments on test CMUTs show a +6dB improvement in receive (Rx) sensitivity, and +6dB improvement in transmit sensitivity in (Pa/V) as compared to a CMUT using silicon nitride isolation (SixNy) layer. CMUT-on-CMOS with HfO2 insulation is successfully integrated and images of a pig-artery was successfully obtained with a 40dB dynamic range for 1x1cm2 planes. Experimental demonstration of side looking capability of single chip CMUT on CMOS system based FL dual ring arrays supported by large signal and FEA simulations was presented. The experimental results which are in agreement with simulations show promising results for the viability of using FL-IVUS CMUT-on-CMOS device with dual mode side-forward looking imaging. Three dimensional images were obtained by the CMUT-on-CMOS array for both a front facing wire and 4 wires that are placed perpendicular to the array surface and ~4 mm away laterally. For a novel array design, a dual gap, dual frequency 2D array was designed, fabricated and verified against the large signal model for CMUTs. Three different CMUT element geometries (2 receive, 1 transmit) were designed to achieve ~20MHz and ~40MHz bands respectively in pulse-echo mode. A system level framework for designing CMUT arrays was described that include effects from imaging design requirements, acoustical cross-talk, bandwidths, signal-to-noise (SNR) optimization and considerations from IC limitations for pulse voltage. Electrical impedance measurements and hydrophone measurements comparisons between design and experiment show differences due to inaccuracies in using SixNy homogenous material in simulation compared to fabricated thin-film stacks (HfO2-AlSi-SixNy). It is concluded that for “thin” membranes the effect of stiffness and mass of HfO2 and AlSi (top electrode) cannot be ignored in the simulation. Also, it is understood that aspect ratio (width to height) <10 will have up to 15% error for center frequency predicted in air when the thin-plate approximation is used for modelling the bending stiffness of the CMUT membrane.

Charge trapping dynamics in Si/SiO2/Hf(1-x)SixO2 and III-V film stack systems are characterized using spectroscopic ellipsometry (SE) and second harmonic generation (SHG). For the first time, discrete absorption features within the bandgap of the SiO2 interfacial layer are identified using SE, and their relation to both intrinsic and process-induced defects is proposed. Sensitivity of the absorption features to process conditions is demonstrated and evidence that these defects contribute to Vfb roll-off is presented. Defects in the Hf(1-x)SixO2 films are probed with fs laser-induced internal multi-photon photo-excitation (IMPE) and time dependent electrostatic field induced second harmonic (TD-EFISH) generation. For the as deposited HfO2 films, a unique TD-EFISH response is identified and explained by resonant two photon ionization of a specific point defect and subsequent tunneling of the photoelectrons to the Si substrate. Charge trapping kinetics for all Hf(1-x)SixO2 films are investigated. Two characteristic trap cross sections are identified and found to be insensitive to dielectric film and process conditions, and associated with a surface “harpooning” mechanism. EFISH from non-centrosymmetric III-V media, including GaAs and In0.53Ga0.47As, is also studied. The anisotropic and time dependent SHG response from different chemically treated In0.53Ga0.47As surfaces is clearly distinguishable and associated with a process-induced change in the surface depletion field. / text

As technologies continue advancing, semiconductor devices with dimensions in nanometers have entered all spheres of human life. This research deals with both the statistical aspect of reliability and some electrical aspect of reliability characterization. As an example of nano devices, TaO_x-based high k dielectric thin &#64257;lms are studied on the failure mode identi&#64257;cation, accelerated life testing, lifetime projection, and failure rate estimation. Experiment and analysis on dielectric relaxation and transient current show that the relaxation current of high k dielectrics is distinctive to the trapping/detrapping current of SiO₂; high k &#64257;lms have a lower leakage current but a higher relaxation current than SiO₂. Based on the connection between polarization-relaxation and &#64257;lm integrity demonstrated in ramped voltage stress tests, a new method of breakdown detection is proposed. It monitors relaxation during the test, and uses the disappearing of relaxation current as the signal of a breakdown event. This research develops a Bayesian approach which is suitable to reliability estimation and prediction of current and future generations of nano devices. It combines the Weibull lifetime distribution with the empirical acceleration relationship, and put the model parameters into a hierarchical Bayesian structure. The value of the Bayesian approach lies in that it can fully utilize available information in modeling uncertainty and provide cogent prediction with limited resources in a reasonable period of time. Markov chain Monte Carlo simulation is used for posterior inference of the reliability projection and for sensitivity analysis over a variety of vague priors. Time-to-breakdown data collected in the accelerated life tests also are modeled with a bathtub failure rate curve. The decreasing failure rate is estimated with a non-parametric Bayesian approach, and the constant failure rate is estimated with a regular parametric Bayesian approach. This method can provide a fast and reliable estimation of failure rate for burn-in optimization when only a small sample of data is available.

High electron mobility transistors (HEMTs) have long been studied for high frequency and high-power application. Among widely known high electron mobility transistors, AlGaN/GaN HEMTs are having the upper hand due to high electron mobility of the GaN channel. Over the times, issues like current collapse, gate leakage, self-heating and gate lag have questioned the performance and reliability of these devices. In the recent years, engineers have come up with newer architectures to address some of these issues. Inserting a high-k dielectric oxide layer in the gate stack proved to be an effective solution to mitigate gate leakage, reduce interfacial traps and improve optimal working conditions. This work aims to study the reliability aspect of these so-called metal-oxide-semiconductor high electron mobility transistors (MOS-HEMT) specifically, HfO2 and HfZrO2 MOS-HEMTs. It was found through numerical simulations that though HfO2 and HfZrO2 dielectrics were able to mitigate gate leakage current, they tend to accumulate more heat in the channel region with respect to the conventional silicon nitride (SiN) passivated counterparts. Moreover, few asymmetric structures were proposed where silicon nitride was placed in the dielectric layer along with HfO2/HfZrO2. In this study it was found that these asymmetric structures showed superior thermal performance while showing near-zero gate leakage current.

No description available.

Metal oxide thin films serve as critical components in many modern technologies, including microelectronic devices. Industrial state-of-the-art production utilizes vapor-phase techniques to make high-quality (dense, smooth, uniform) thin film materials. However, vapor-phase techniques require large energy inputs and expensive equipment and precursors. Solution-phase routes to metal oxides have attracted great interest as cost-effective alternatives to vapor-phase methods and also offer the potential of large-area coverage, facile control of metal composition, and low-temperature processing. Solution deposition has previously been dominated by sol-gel routes, which utilize organic ligands, additives, and/or solvents. However, sol-gel films are often porous and contain residual carbon impurities, which can negatively impact device properties. All-inorganic aqueous routes produce dense, ultrasmooth films without carbon impurities, but the mechanisms involved in converting aqueous precursors to metal oxides are virtually unexplored. Understanding these mechanisms and the parameters that influence them is critical for widespread use of aqueous approaches to prepare microelectronic components. Additionally, understanding (and controlling) density and composition inhomogeneities is important for optimizing electronic properties. An overview of deposition approaches and the challenges facing aqueous routes are presented in Chapter I. A summary of thin film characterization techniques central to this work is given in Chapter II. This dissertation contributes to the field of solution-phase deposition by focusing on three areas. First, an all-inorganic aqueous route to high-κ metal oxide dielectrics is developed for two ternary systems. Chapters III and IV detail the film formation chemistry and film properties of lanthanum zirconium oxide (LZO) and zirconium aluminum oxide (ZAO), respectively. The functionality of these dielectrics as device components is also demonstrated. Second, the impact of steam annealing on the evolution of aqueous-derived films is reported. Chapter V demonstrates that steam annealing lowers processing temperatures by effectively reducing residual counterion content, improving film stability with respect to water absorption, and enhancing dielectric properties of LZO films. Third, density and composition inhomogeneities in aqueous-derived films are investigated. Chapters VI and VII examine density inhomogeneities in single- and multi-metal component thin films, respectively, and show that these density inhomogeneities are related to inhomogeneous metal component distributions. This dissertation includes previously published coauthored material.

Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.

L'objectif de cette thèse était l’étude de dispositifs électroniques à base de pérovskites hybrides. Dans ce cadre nous avons développé et fabriqué des transistors à effet de champ (FET) ainsi que des cellules solaires à base de perovskite. Dans le cas des transistors, en utilisant des couches minces de pérovskites hybride hautement cristallisées nous avons réalisé des transistors ambipolaires fonctionnant à la température ambiante et présentant une hystérésis faible, une transconductance élevée (pour ce type de matériau), et un rapport Ion / Ioff> 104. Dans le cadre de cette thèse l’utilisation de plusieurs diélectriques nous a permis d’obtenir une forte modulation de la conductance du canal avec des tensions de grille relativement faibles (4-6V). Dans ce cadre l’oxyde d’Hafnium de permittivité relative er=23.5 a montré de très bonnes performances et une très bonne compatibilité pour la croissance de pérovskite hybride. Après plusieurs étapes de polarisation les dispositifs ont présenté un fonctionnement stabilisé et ont été mesurés au cours des cycles consécutifs pendant 14 heures avec peu de changement dans leurs performances. Nous avons mis en évidence que l’augmentation du champ électrique a permis la formation d’un canal de trous à l’interface. La polarisation consécutive des dispositifs à base de HfO2/pérovskite a amené à la création d’un second courant d’électrons et a mis en évidence un fonctionnement ambipolaire final. L’ensemble des dispositifs ont présenté une hystérésis dont l’amplitude était parfois non négligeable. Cela a démontré la présence de charges mobiles ioniques aux interfaces qui influence les courants de sorties du dispositif. Dans la dernière partie de la thèse nous nous sommes intéressés à la croissance de pérovskite hybride pour la production de cellules solaires. Nous avons étudié les deux conditions de croissance suivantes : conditions sous air normal (humidité relative> 60%) et en atmosphère d’azote en boites à gants (humidité relative <0.1 ppm). Par ces deux voies nous avons obtenu respectivement des rendements de conversion photovoltaïque respectivement de 5% et 8%. / The objective of this thesis was the study of electronic devices based on hybrid perovskites. In this context we have developed and produce field effect transistors (FETs) and solar cells based on hybrid perovskite material. In the case of transistors, using thin layers of highly crystallized hybrid perovskites we have made ambipolar transistors operating at room temperature and having low hysteresis, high transconductance (for this type of material) and a ratio of Ion / Ioff > 104. In the context of this thesis, the use of several dielectrics allowed us to obtain a high modulation of the channel conductance with relatively low gate voltages (4-6V). Hafnium oxide with relative permittivity er = 23.5 showed very good performances and a very good compatibility for the hybrid perovskite growth. After several polarization steps the devices exhibited stabilized operation and were measured in consecutive cycles for 14 hours with small change in their performance. We have shown that the increase of the electric field allowed the formation of a hole channel at the interface. The successive polarization of HfO2 / perovskite-based devices led to the creation of a second electron current and demonstrated a final ambipolar device. All the devices presented a hysteresis with amplitude sometimes not negligible. This demonstrated the presence of mobile ion charges at the interfaces that influence the output currents of the device. In the last part of the thesis we focused our work in hybrid perovskite growth for the production of solar cells. We have studied two growth conditions: conditions under normal air (relative humidity> 60%) and nitrogen atmosphere in glove boxes (relative humidity <0.1 ppm). By these two paths we obtained photovoltaic conversion efficiencies of 5% and 8% respectively.

Challenges with integrating high-κ gate dielectric,retrograde Si1-xGexchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si1-xGex surface-channel and different high-κgate dielectric are examined. Si1-xGex ρMOSFETs with an Al2O3/HfAlOx/Al2O3nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si1-xGexρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si1-xGexρMOSFETs. Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si1-xGexincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si1-xGex/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi2-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi1-xGex is found to form on selectively grown p-typeSi1-xGexused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi1-xGex/p-type Si1-xGexcontacts is 5´10-8Ωcm2, which satisfies the requirement for the 45-nmtechnology node in 2010. When the Si1-xGexchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi1-xGexretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled. Key Words:MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.

<p>Challenges with integrating high-κ gate dielectric,retrograde Si_1-xGe_xchannel and silicided contacts in future CMOStechnologies are investigated experimentally and theoreticallyin this thesis. ρMOSFETs with either Si or strained Si_1-xGex surface-channel and different high-κgate dielectric are examined. Si_1-xGex ρMOSFETs with an Al₂O₃/HfAlO_x/Al₂O₃nano-laminate gate dielectric prepared by means ofAtomic Layer Deposition (ALD) exhibit a great-than-30% increasein current drive and peak transconductance compared toreference Si ρMOSFETs with the same gate dielectric. Apoor high-κ/Si interface leading to carrier mobilitydegradation has often been reported in the literature, but thisdoes not seem to be the case for our Si ρMOSFETs whoseeffective mobility coincides with the universal hole mobilitycurve for Si. For the Si_1-xGe_xρMOSFETs, however, a high density ofinterface states giving riseto reduced carrier mobility isobserved. A method to extract the correct mobility in thepresence of high-density traps is presented. Coulomb scatteringfrom the charged traps or trapped charges at the interface isfound to play a dominant role in the observed mobilitydegradation in the Si_1-xGe_xρMOSFETs.</p><p>Studying contacts with metal silicides constitutes a majorpart of this thesis. With the conventional device fabrication,the Si_1-xGe_xincorporated for channel applications inevitablyextends to the source-drain areas. Measurement and modelingshow that the presence of Ge in the source/drain areaspositively affects the contact resistivity in such a way thatit is decreased by an order of magnitude for the contact of TiWto p-type Si_1-xGe_x/Si when the Ge content is increased from 0 to 30at. %. Modeling and extraction of contact resistivity are firstcarried out for the traditional TiSi₂-Si contact but with an emphasis on the influenceof a Nb interlayer for the silicide formation. Atwo-dimensional numerical model is employed to account foreffects due to current crowding. For more advanced contacts toultra-shallow junctions, Ni-based metallization scheme is used.NiSi_1-xGex is found to form on selectively grown p-typeSi_1-xGe_xused as low-resistivity source/drain. Since theformed NiSi1-xGex with a specific resistivity of 20 mWcmreplaces a significant fraction of the shallow junction, athree-dimensional numerical model is employed in order to takethe complex interface geometry and morphology into account. Thelowest contact resistivity obtained for our NiSi_1-xGe_x/p-type Si_1-xGe_xcontacts is 5´10^-8Ωcm², which satisfies the requirement for the 45-nmtechnology node in 2010.</p><p>When the Si_1-xGe_xchannel is incorporated in a MOSFET, it usuallyforms a retrograde channel with an undoped surface region on amoderately doped substrate. Charge sheet models are used tostudy the effects of a Si retrograde channel on surfacepotential, drain current, intrinsic charges and intrinsiccapacitances. Closed-form solutions are found for an abruptretrograde channel and results implicative for circuitdesigners are obtained. The model can be extended to include aSi_1-xGe_xretrograde channel. Although the analytical modeldeveloped in this thesis is one-dimensional for long-channeltransistors with the retrograde channel profile varying alongthe depth of the transistor, it should also be applicable forshort-channel transistors provided that the short channeleffects are perfectly controlled.</p><p><b>Key Words:</b>MOSFET, SiGe, high-k dielectric, metal gate,mobility, charge sheet model, retrograde channel structure,intrinsic charge, intrinsic capacitance, contactresistivity.</p>