<p>In communication systems, the need for high bandwidth interconnects and</p><p>efficient distribution of large amount of data is very essential. This thesis work</p><p>addresses all-optical packet switching issues in the field of reconfigurable optical</p><p>interconnection networks for high performance embedded systems. The recent</p><p>research conducted at the Halmstad University, on high performance embedded</p><p>systems, focuses on the optical interconnection techniques to achieve ultra high</p><p>throughputs and reconfigurability at the system level.</p><p>Recent research in the field of optical interconnection networks for applications</p><p>like switches and routers for data and telecommunication industry and parallel</p><p>computing architectures for embedded signal processing use optical to electrical</p><p>conversion to switch packets. This conversion scales down the enormous bandwidth</p><p>capacity of the optical communication channels to electronic processing rates. To</p><p>maintain the high throughputs all over the interconnection networks, the optical</p><p>packets need to be maintained in optical state and switched to different part of the</p><p>interconnection network. To achieve this goal, all-optical packet switching</p><p>architectures are studied. The study is concluded with a positive outlook towards alloptical</p><p>switching technologies, and it will play a very important role in the near</p><p>future in the field of optical communication, telecommunication and embedded</p><p>systems.</p>

<p>We study the problem of scheduling applications composed of a large number of tasks on heterogeneous clusters. Tasks are identical, independent from each other, and can hence be computed in any order. The goal is to execute all the tasks as quickly as possible. We use the Master-Worker paradigm, where tasks are maintained by the master which will hand out batches of a variable amount of tasks to requesting workers. We introduce a new scheduling strategy, the Monitor strategy, and compare it to other strategies suggested in the literature. An image filtering application, known as matched filtering, has been used to compare the different strategies. Our implementation involves datastaging techniques in order to circumvent the possible bottleneck incurred by the master, and multi-threading to prevent possible processor idleness.</p>

We consider the often-studied problem of sorting, for a parallel computer. Given an input array distributed evenly over p processors, the task is to compute the sorted output array, also distributed over the p processors. Many existing algorithms take the approach of approximately load-balancing the output, leaving each processor with Θ(n/p) elements. However, in many cases, approximate load-balancing leads to inefficiencies in both the sorting itself and in further uses of the data after sorting. We provide a deterministic parallel sorting algorithm that uses parallel selection to produce any output distribution exactly, particularly one that is perfectly load-balanced. Furthermore, when using a comparison sort, this algorithm is 1-optimal in both computation and communication. We provide an empirical study that illustrates the efficiency of exact data splitting, and shows an improvement over two sample sort algorithms. / Singapore-MIT Alliance (SMA)

Variations between the software environments(e.g., installed applications, versions of libraries) on different high-performance computing (HPC) systems lead to a heterogeneity problem. Therefore, we design an optimized, homogeneous virtual machine (VM) called a virtual application appliance (VAA). Scientists can package scientific applications, and all supporting software components, as VAAs and run them independently from the underlying heterogeneous HPC systems. However, securely moving data in and out of the VAA and controlling the execution of applications are not trivial for a non-computer scientist. Consequently, we develop two automated stage-in/stage-out secure data movement mechanisms. We also explore a migration mechanism to further simplify the control of the VAA execution. Empirical evaluation results show that VAAs achieve near-native performance in widely used bioinformatics applications that we tested. Data movement, VM boot up, shutdown and migration overheads of VAAs are negligible with respect to total run-times.

Scientific computing often requires solving systems of linear equations. Most software pack- ages for solving large-scale linear systems use Gaussian elimination methods such as LU- decomposition. An alternative method, recently introduced by K. Habgood and I. Arel, involves an application of Cramer’s Rule and Chio’s condensation to achieve a better per- forming system for solving linear systems on parallel computing platforms. This thesis describes an implementation of this algorithm on an nVidia graphics processor card us- ing the CUDA language. Increased performance, relative to the serial implementation, is demonstrated, paving the way for future parallel realizations of the scheme.

This PhD thesis is divided into two parts. Part one dealswith the development of the material and the mechanicalproperties of Steel Fibrous Cement Based Composites (SFCBC) forimproving bridge design and construction. It familiarizes thehydration mechanisms of the high performance concrete with thehelp of Powers´ and Jensen´s models. Concretes withdifferent water-cement ratio were compared with each other withrespect to degree of hydration and hydration products. Thisanalysis showed that high performance concrete has higherstrengths not because it has more gel solid, but due to ithaving less porosity and higher filler content compared toordinary concrete. A number of experiments were performed to achieve a mixdesign method for a SFCBC, which has good workability, highearly and long-term strength and good durabilitycharacteristics. A Self-compacting and self-leveling fibrouscomposite, which has ultra high strengths (Compressive strengthfc= 180 ~ 220MPa and flexural tensile strengthfföi= 14 ~ 32MPa depending on the volumefraction of fibers) was produced. This composite was alsotested under different curing conditions in order toinvestigate the effect of curing on hydration andself-desiccation shrinkage. These tests showed that SFCBCshould not be water-cured under a long period andself-desiccation influences the compressive strengthnegatively. Test of scaling at freezing showed that SFCBC hasvery good durability characteristics. Part two deals with the behavior of SFCBC in the anchoragezones of prestressed bridges. The prismatic composite specimenswere tested for different volume fractions of fibers underdifferent concentrations ratios of strip loading. The resultsof these tests showed that the ultimate strength of the SFCBCspecimens was approximately twice that of ordinary concretewith the same size (fc= 60MPa reinforced with stirrups). Therefore,SFCBC has good possibility to replace the traditional rebars inthe anchorage zones of prestressed bridges. This composite has different behavior than the traditionalconcrete e.g. crack formation, failure criteria, effectivestrength and angle of friction. A vertical crack on thecenterline was occurred while wedge developed under the loadingplate. In contrast to ordinary concrete, the cracks could notreach to the bottom of the blocks. The tests results gave the ideas of that this material actslike metals or plastics in the high fiber content. Thismaterial is neither very brittle as concrete nor very ductileas metals but it is somewhere between them. Upper-bound plasticity solutions were utilized for modelingthe bearing capacity of SFCBC. Predictions of this method aregood enough to estimate the bearing capacity of SFCBC in theanchorage zones of prestressed bridges. <b>Keywords:</b>Process improvement of bridges, Prestressedconcrete, High performance concrete, Ultra high performanceconcrete, Hydration, Cement based composites, Fibers,Self-compacting concrete, Bearing capacity, Anchorage zones,Tests

Date : June, 2008. Level : Master Thesis EF0705, 10 points (15credits) Authors : Amalokwu Obiajulum John (820821) Lawrence Njilefack Ngoasong (770901) Title : Budgetary and Management control Process in a Manufacturing Organization. Supervisor: Roland Almqvist. Problem : What is the budgeting practice in the Nigerian Manufacturing companies? Purpose : The aim of this study is to investigate the management control practice (budget being the tool for management control) in Guinness Nigeria Plc and to suggest what seems to us the most appropriate practice based on findings from literatures and empirics Method : The study was described based on a qualitative approach. Furthermore, we described why we chose the company, sources of literature, techniques employed in data collection (primary data), research purpose, data analysis as well as critiques to the method use. Conclusion : The Integration of strategic Management and Budgeting enhances competitiveness which when attained is translated as high performance. Keywords : Management Control, Budgeting, strategy, High performance and Competitive advantage.

Performance projections of High Performance Computing (HPC) applications onto various hardware platforms are important for hardware vendors and HPC users. The projections aid hardware vendors in the design of future systems and help HPC users with system procurement and application refinements. In this dissertation, we present an efficient method to project the performance of HPC applications onto Chip Multiprocessor (CMP) based systems using widely available standard benchmark data. The main advantage of this method is the use of published data about the target machine; the target machine need not be available. With the current trend in HPC platforms shifting towards cluster systems with chip multiprocessors (CMPs), efficient and accurate performance projection becomes a challenging task. Typically, CMP-based systems are configured hierarchically, which significantly impacts the performance of HPC applications. The goal of this research is to develop an efficient method to project the performance of HPC applications onto systems that utilize CMPs. To provide for efficiency, our projection methodology is automated (projections are done using a tool) and fast (with small overhead). Our method, called the surrogate-based workload application projection method, utilizes surrogate benchmarks to project an HPC application performance on target systems where computation component of an HPC application is projected separately from the communication component. Our methodology was validated on a variety of systems utilizing different processor and interconnect architectures with high accuracy and efficiency. The average projection error on three target systems was 11.22 percent with standard deviation of 1.18 percent for twelve HPC workloads.

One of the most critical blocks in a wide-band continuous time sigma delta (CTSD) analog-to-digital converter (ADC) is the loop filter. For most loop filter topologies, the performance of the filter depends largely on the performance of the operational amplifiers (op-amps) used in the filter. The op-amps need to have high linearity, low noise and large gain over a wide bandwidth. In this work, the impact of op-amp parameters like noise and linearity on system level performance of the CTSD ADC is studied, and the design specifications are derived for the op-amps. A new class-AB bias scheme, which is more robust to process variations and has an improved high frequency response over the conventional Monticelli bias scheme, is proposed. A biquadratic filter which forms the input stage of a 5th order low pass CTSD ADC is used as a test bench to characterize the op-amp performance. The proposed class-AB output stage is compared with the class-AB output stage with Monticelli bias scheme and a class-A output stage with bias current reuse. The filter using the new op-amp architecture has lower power consumption than the other two architectures. The proposed class AB bias scheme has better process variation and mismatch tolerance compared to the op-amp that uses conventional bias scheme.

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of adoption is due to the fact that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can take advantage of the inherent parallelism in neural networks is desired. This thesis investigates how the Restricted Boltzmann machine, a popular type of neural network, can be effectively mapped to a high-performance hardware architecture on FPGA platforms. The proposed, modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100MHz through a variety of different configurations. The maximum performance was obtained by instantiating a Restricted Boltzmann Machine of 256x256 nodes distributed across four FPGAs, which results in a computational speed of 3.13 billion connection-updates-per-second and a speed-up of 145-fold over an optimized C program running on a 2.8GHz Intel processor.