The invention of medical imaging technology revolved the process of diagnosing diseases and opened a new world for better studying inside of the human body. In order to capture images from different human organs, different devices have been developed. Gastro-Endoscopy is an example of a medical imaging device which captures images from human gastrointestinal. With the advancement of technology, the issues regarding such devices started to get rectified. For example, with the invention of swallow-able pill photographer which is called Wireless Capsule Endoscopy (WCE); pain, time, and bleeding risk for patients are radically decreased. The development of such technologies and devices has been increased and the demands for instruments providing better performance are grown along the time. In case ofWCE, the special feature requirements such as a small size (as small as an ordinary pill) and wireless transmission of the captured images dictate restrictions in power consumption and area usage. In this research, the reduction of image encoder hardware cost for endoscopic imaging application has been focused. Several encoding algorithms have been studied and the comparative results are discussed. An efficient data encoder based on Lempel-Ziv-Welch (LZW) algorithm is presented. The encoder is a library-based one where the size of library can be modified by the user, and hence, the output data rate can be controlled according to the bandwidth requirement. The simulation is carried out with several endoscopic images and the results show that a minimum compression ratio of 92.5 % can be achieved with a minimum reconstruction quality of 30 dB. The hardware architecture and implementation result in Field-Programmable Gate Array (FPGA) for the proposed window-based LZW are also presented. A new lossy LZW algorithm is proposed and implemented in FPGA which provides promising results for such an application.

The invention of medical imaging technology revolved the process of diagnosing diseases and opened a new world for better studying inside of the human body. In order to capture images from different human organs, different devices have been developed. Gastro-Endoscopy is an example of a medical imaging device which captures images from human gastrointestinal. With the advancement of technology, the issues regarding such devices started to get rectified. For example, with the invention of swallow-able pill photographer which is called Wireless Capsule Endoscopy (WCE); pain, time, and bleeding risk for patients are radically decreased. The development of such technologies and devices has been increased and the demands for instruments providing better performance are grown along the time. In case ofWCE, the special feature requirements such as a small size (as small as an ordinary pill) and wireless transmission of the captured images dictate restrictions in power consumption and area usage. In this research, the reduction of image encoder hardware cost for endoscopic imaging application has been focused. Several encoding algorithms have been studied and the comparative results are discussed. An efficient data encoder based on Lempel-Ziv-Welch (LZW) algorithm is presented. The encoder is a library-based one where the size of library can be modified by the user, and hence, the output data rate can be controlled according to the bandwidth requirement. The simulation is carried out with several endoscopic images and the results show that a minimum compression ratio of 92.5 % can be achieved with a minimum reconstruction quality of 30 dB. The hardware architecture and implementation result in Field-Programmable Gate Array (FPGA) for the proposed window-based LZW are also presented. A new lossy LZW algorithm is proposed and implemented in FPGA which provides promising results for such an application.

Data compression is a vast subject with a lot of different algorithms. All algorithms are not good at every task and this thesis takes a closer look on compression of small files in the range of 100-300 bytes having in mind that the compressed output are to be sent over the Short Messaging System (SMS). Some well-known algorithms are tested for compression ratio and two of them, the Algorithm Λ, and the Adaptive Arithmetic Coding, are chosen to get a closer understanding of and then implement in the Java language. Those implementations are tested alongside the first tested implementations and one of the algorithms are chosen to answer the question ”Which compression algorithm is best suited for compression of data for use in Short Messaging System messages?”. / Datakompression är ett brett område med ett stort antal olika algoritmer. Alla algoritmer är inte bra för alla tillfällen och denna rapport tittar i huvudsak på kompression av små filer i intervallet 100-300 byte tänkta att skickas komprimerade över SMS. Ett antal välkända algoritmers kompressionsgrad är testade och två av dem, Algorithm Λ och Adaptiv Aritmetisk Kodning, väljs ut och studeras närmre samt implementeras i Java. Dessa implementationer är sedan testade tillsammans med tidigare testade implementationer och en av algoritmerna väljs ut för att besvara frågan "Vilken kompressionsalgoritm är best lämpad för att komprimerad data för användning i SMS-meddelanden?".

This thesis describes the design of fast JPEG processing accelerators for a DSP processor. Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed. First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog. Extension of the accelerator instructions was given following a custom design flow.

Syftet med detta examensarbete är att med avseende på Snow Softwares databas försöka att effektivisera samt omstrukturera de procedurer som hanterar deras regelverk. Den är ej inriktad på att utvärdera eller förändra de algoritmer som redan finns i Microsoft SQL Server. Ett flertal olika prototyper framställdes och utvärderades. Dessa var ej specifika för just denna databas och kan därför vara intressanta även i andra sammanhang. Den prototyp som visade sig vara mest effektiv implementerades så att den enkelt skulle kunna tas i bruk i det nuvarande systemet. Prototypen gav en ungefärlig förbättring i söktid på 18,8 %

Dynamic Huffman compression algorithms operate on data-streams with a bounded symbol list. With these algorithms, the complete list of symbols must be contained in main memory or secondary storage. A horizontal format transaction database that is streaming can have a very large item list. Many nodes tax both the processing hardware primary memory size, and the processing time to dynamically maintain the tree. This research investigated Huffman compression of a transaction-streaming database with a very large symbol list, where each item in the transaction database schema’s item list is a symbol to compress. The constraint of a large symbol list is, in this research, equivalent to the constraint of a memory-limited machine. A large symbol set will result if each item in a large database item list is a symbol to compress in a database stream. In addition, database streams may have some temporal component spanning months or years. Finally, the horizontal format is the format most suited to a streaming transaction database because the transaction IDs are not known beforehand This research prototypes an algorithm that will compresses a transaction database stream. There are several advantages to the memory limited dynamic Huffman algorithm. Dynamic Huffman algorithms are single pass algorithms. In many instances a second pass over the data is not possible, such as with streaming databases. Previous dynamic Huffman algorithms are not memory limited, they are asymptotic to O(n), where n is the number of distinct item IDs. Memory is required to grow to fit the n items. The improvement of the new memory limited Dynamic Huffman algorithm is that it would have an O(k) asymptotic memory requirement; where k is the maximum number of nodes in the Huffman tree, k < n, and k is a user chosen constant. The new memory limited Dynamic Huffman algorithm compresses horizontally encoded transaction databases that do not contain long runs of 0’s or 1’s.

Nous considérons dans cette thèse le problème dotpimisation dun schéma de codage/décodage JPEG et le post-traitement de réduction des effets de blocs dans les images codées par JPEG.<br />Nous proposons tout dabord le filtrage de Wiener comme optimisation du banc de filtres de synthèse pour une distorsion minimale et nous cherchons par la suite une quantifcation optimisée. Lalgorithme itératif A1 réalise une optimisation conjointe des quantificateurs et du banc de filtres de synthèse. Les résultats experimentaux sur quelques images montrent que le gain total en terme de PSNR peut atteindre 1,36dB et les améliorations visuelles confirment ces résultats.<br />Enfin, nous proposons une nouvelle technique de réduction des effets de blocs basée sur la minimisation de lénergie haute fréquence du bruit de quantification. Lévaluation de lalgorithme B1montre une diminution des effets de blocs, et de nombreuses illustrations permettent dappréhender visuellement les performances de cette méthode.

Submitted by Marcio Filho (marcio.kleber@ufba.br) on 2017-06-02T13:48:59Z No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / Approved for entry into archive by Vanessa Reis (vanessa.jamile@ufba.br) on 2017-06-08T11:16:24Z (GMT) No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / Made available in DSpace on 2017-06-08T11:16:24Z (GMT). No. of bitstreams: 1 Dissertação - Eder Santana Freire - Revisão Final.pdf: 2884218 bytes, checksum: 8fe133e4eb9b646336edaa01f6baba6a (MD5) / O projeto de hardware especializado para detecção de intrusão em redes de computadores tem sido objeto de intensa pesquisa ao longo da última década, devido ao seu desempenho consideravelmente maior, comparado às implementações em software. Nesse contexto, um dos fatores limitantes é a quantidade finita de recursos de memória embarcada, em contraste com o crescente número de padrões de ameaças a serem analisados. Este trabalho propõe uma arquitetura baseada no algoritmo de Huffman para codificação, armazenamento e decodificação paralela de tais padrões, a fim de reduzir o consumo de memória embarcada em projetos de hardware destinado à detecção de intrusão em redes. Experimentos foram realizados através de simulação e síntese em FPGA de conjuntos de regras atuais do sistema de detecção de intrusão Snort, e os resultados indicaram uma economia de até 73% dos recursos de memória embarcada do chip. Adicionalmente, a utilização de uma estrutura paralelizada apresentou ganhos de desempenho significantes durante o processo de decodificação das regras.

No description available.

Thesis (Ph.D.)--University of Wollongong, 2003. / Typescript. Includes bibliographical references: leaf 191-198.