This thesis presents an investigation into the characteristics of and driving methods for light emitting diode (LED) lamp system. A comprehensive overview on the lighting development is proposed. The characteristic of the light emitting diode (LED) lamp is described and the requirements of the ballast for the light emitting diode (LED) lamp are presented. Although LED lamps have longer lifetime than fluorescent lamps, the short lifetime limitation of LED driver imposed by electrolytic capacitor has to be resolved. Therefore, an LED driver without electrolytic capacitor in the whole power conversion process is preferred. In this thesis, a single phase, power factor correction converter without electrolytic capacitors for LED lighting applications is proposed, which is a modified SEPIC converter working in discontinuous conduction mode (DCM). Different with a conventional SEPIC converter, the middle capacitor is replaced with a valley-fill circuit. The valley-fill circuit could reduce the voltage stress of output diode and middle capacitor under the same power factor condition, thus achieving higher efficiency. Instead of using an electrolytic capacitor for the filter, a polyester capacitor of better lifetime expectancy is used. An interleaved power factor correction SEPIC with valley fill circuit is proposed to further increase the efficiency and to reduce the input and output filter size and cost. The interleaved converter shows the features such as ripple cancellation, good thermal distribution and scalability. / Master of Science

The critical conduction mode (CRM) power factor correction converters (PFC) are widely used in industry for low power offline switching mode power supplies. For the CRM PFC, the main advantage is to reduce turn-on loss of the main switch. However, the large inductor current ripple in CRM PFC creates huge DM EMI noise, which requires a big EMI filter. The switching frequency of the CRM PFC is variable in half line cycle which makes the EMI characteristics of the CRM PFC are not clear and have not been carefully investigated. The worst case of the EMI noise, which is the baseline to design the EMI filter, is difficult to be identified. In this paper, an approximate mathematical EMI noise model based on the investigation of the principle of the quasi-peak detection is proposed to predict the DM EMI noise of the CRM PFC. The developed prediction method is verified by measurement results and the predicted DM EMI noise is good to evaluate the EMI performance. Based on the noise prediction, the worst case analysis of the DM EMI noise in the CRM PFC is applied and the worst case can be found at some line and load condition, which will be a great help to the EMI filter design and meanwhile leave an opportunity for the optimization of the whole converter design. What is more, the worst case analysis can be extended to 2-channel interleaved CRM PFC and some interesting characteristics can be observed. For example, the great EMI performance improvement through ripple current cancellation in traditional constant frequency PFC by using interleaving techniques will not directly apply to the CRM PFC due to its variable switching frequency. More research needs to be done to abstract some design criteria for the boost inductor and EMI filter in the interleaved CRM PFC. / Master of Science

The popularity of the internal combustion engine (ICE) vehicles has contributed to global warming problem and degradation of air quality around the world. Furthermore, the vehicles??? massive demand on gas has played a role in the depletion of fossil fuel reserves and the considerable rise in the gas price over the past twenty years. Those existing challenges force the auto-industry to move towards the technology development of vehicle electrification. An electrified vehicle is driven by one or more electric motors. And the electricity comes from the onboard energy storage system (ESS). Currently, no single type of green energy source could meet all the requirements to drive a vehicle. A hybrid energy storage system (HESS), as a combination of battery and ultra-capacitor units, is expected to improve the overall performance of vehicles??? ESS. This thesis focuses on the design of HESS and the development of a HESS prototype for electric vehicles (EVs) and hybrid electric vehicles (HEVs). Battery unit (BU), ultra-capacitor unit (UC) and a DC/DC converter interfacing BU and UC are the three main components of HESS. The research work first reviews literatures regarding characteristics of BU, UC and power electronic converters. HESS design is then conducted based on the considerations of power capability, energy efficiency, size and cost optimization. Besides theoretical analysis, a HESS prototype is developed to prove the principles of operation as well. The results from experiment are compared with those from simulation.

This thesis proposes innovative methods to extract information embedded in the frequency and time domain response of the transformer winding, and utilizes them to suggest solutions to a few tasks that have until now been thought difficult, if not impossible, to resolve. Pursuing this philosophy originated from the basic under- standing that the response of any physical system (behaving largely as a linear time invariant system) has embedded information that characterizes it completely. So, the prerequisite is to evolve ways to extract this information from measured responses. Once that is done, a variety of interesting applications can be envisaged. The two applications considered in this thesis are- •Investigate indirect measurement of the series capacitance of a transformer winding using the measured frequency or time domain response •Explore the possibility of increasing the physical resolution of the ladder network used to model a fully interleaved-disk winding In the former application, since direct measurement of series capacitance is impossible, alternatives based on indirect measurement were also not attempted. Similarly, in the latter application, the upper limit is known to be fixed by the number of distinctly observable peaks in the magnitude frequency response, so the question of increasing this limit was also never explored. Solutions to these tasks are proposed after a systematic analysis of frequency/time domain responses of a winding, initially modeled as a lumped parameter ladder network, to extract correlations that exist between them and winding parameters, and finally examine how these relations can be exploited together with the measured responses. Each of the five chapters is dedicated to describe the solution to one task. In each chapter, analytical formulation is presented first, followed by experimental results. Good agreement with the predicted results demonstrates its practicability. In final summary, indirect measurement of the series capacitance of a winding and en- hancing physical resolution of a ladder network model to represent a fully interleaved- disk winding was successfully demonstrated and they are the main contributions of this thesis.

The Modular Multilevel Converter (MMC) is one of the most commonly used active converters in the high-/medium-voltage sector due to its many advantages such as high scalability, high efficiency, modularity and low harmonic contents. However, in low-voltage and high-current applications, classical MMC designs are not very economical. Recently there has been interest in a new design of modular multilevel converter with interleaved submodules (ISM-MMC) capable of using lower cost, lower current switches. The aim of this study is to compare several different design configurations for a given ISM-MMC topology including classical MMC and to give the best design approach taking into account the efficiency and energy density of the system. The power loss of ISM-MMC influence the final efficiency. The loss studied in this thesis mainly consists of conduction losses and switching losses in the semiconductor devices and inductor losses. An analytical calculation method is summarized and validated by the simulation result. The simulation result is carried out in PLECS model with different system components. Power density is determined by the output power and the converter dimension. The volume of semiconductor devices and passive components determine the general dimension of the converter. This thesis discusses the selection of semiconductor devices, inductor and capacitor in the system, with semiconductor devices constraining interleaved leg current and submodule voltage, inductor constraining output current ripple and capacitor constraining capacitor voltage fluctuation. After the specific components are designed, their dimensions are evaluated, and thus the power density of different configurations can be compared. / Den modulära multinivåomvandlaren (modular multilevel converter, MMC) är en av de mest använda aktiva omvandlarna inom hög-/mellanspänningssektorn på grund av dess många fördelar som hög skalbarhet, hög verkningsgrad, modularitet och lågt övertonsinnehåll. Men i lågspännings- och högströmsapplikationer är konventionella MMC-konstruktioner inte särskilt ekonomiska. Nyligen har det funnits intresse för en ny design av modulär flernivåomvandlare med interfolierade submoduler (ISM-MMC) som kan uppnå lägre kostnad, och använda mindre halvledarelement. Syftet med denna studie är att jämföra flera olika designkonfigurationer för en given ISM-MMC-topologi inklusive konventionell MMC och att ge den bästa designmetoden med hänsyn till systemets verkningsgrad och energitäthet. Effektförlusten för ISM-MMC påverkar den slutliga verkningsgraden. Förluster som studeras i denna avhandling består huvudsakligen av ledningsförluster och kopplingsförluster i halvledarenheterna och induktorförluster. En analytisk beräkningsmetod sammanfattas och valideras av simuleringsresultatet. Simuleringsresultatet utförs men en PLECS-modell med olika systemkomponenter. Effekttätheten bestäms av uteffekten och omvandlardimensionen. Volymen av halvledarenheter och passiva komponenter bestämmer omvandlarens allmänna dimension. Denna avhandling diskuterar valet av halvledarenheter, induktor och kondensator i systemet, med halvledarenheter som begränsar interfolierad benström och submodulspänning, induktor som begränsar utströmsrippel och kondensatorbegränsande kondensatorspänningsfluktuationer. Efter att de specifika komponenterna har valts utvärderas deras storlek, och därmed kan effekttätheten för olika konfigurationer jämföras.

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

<p>Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially.</p><p>Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.</p>

A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

Nonuniform sampling occurs in many practical applications either intentionally or unintentionally. This thesis deals with the reconstruction of two-periodic nonuniform signals which is of great importance in two-channel time-interleaved analog-to-digital converters. In a two-channel time-interleaved ADC, aperture delay mismatch between the channels gives rise to a two-periodic nonuniform sampling pattern, resulting in distortion and severely affecting the linearity of the converter. The problem is solved by digitally recovering a uniformly sampled sequence from a two-periodic nonuniformly sampled set. For this purpose, a time-varying FIR filter is employed. If the sampling pattern is known and fixed, this filter can be designed in an optimal way using least-squares or minimax design. When the sampling pattern changes now and then as during the normal operation of time-interleaved ADC, these filters have to be redesigned. This has implications on the implementation cost as general on-line design is cumbersome. To overcome this problem, a novel time-varying FIR filter with polynomial impulse response is developed and characterized in this thesis. The main advantage with these filters is that on-line design is no longer needed. It now suffices to perform only one design before implementation and in the implementation it is enough to adjust only one variable parameter when the sampling pattern changes. Thus the high implementation cost is decreased substantially. Filter design and the associated performance metrics have been validated using MATLAB. The design space has been explored to limits imposed by machine precision on matrix inversions. Studies related to finite wordlength effects in practical filter realisations have also been carried out. These formulations can also be extended to the general M - periodic nonuniform sampling case.

At a time where almost 1.75 billion people around the world use the Internet on a regular basis, optical communication over optical fibers that is used in long distance and high demand applications has to be capable of providing higher communication speed and re-liability. In recent years, strong demand is driving the dense wavelength division multip-lexing network upgrade from 10 Gb/s per channel to more spectrally-efficient 40 Gb/s or 100 Gb/s per wavelength channel, and beyond. The 100 Gb/s Ethernet is currently under standardization, and in a couple of years 1 Tb/s Ethernet is going to be standardized as well for different applications, such as the local area networks (LANs) and the wide area networks (WANs). The major concern about such high data rates is the degradation in the signal quality due to linear and non-linear impairments, in particular polarization mode dispersion (PMD) and intrachannel nonlinearities. Moreover, the higher speed transceivers are expensive, so the alternative approaches of achieving the required rates is preferably done using commercially available components operating at lower speeds.In this dissertation, different LDPC-coded modulation techniques are presented to offer a higher spectral efficiency and/or power efficiency, in addition to offering aggregate rates that can go up to 1Tb/s per wavelength. These modulation formats are based on the bit-interleaved coded modulation (BICM) and include: (i) three-dimensional LDPC-coded modulation using hybrid direct and coherent detection, (ii) multidimensional LDPC-coded modulation, (iii) subcarrier-multiplexed four-dimensional LDPC-coded modulation, (iv) hybrid subcarrier/amplitude/phase/polarization LDPC-coded modulation, and (v) iterative polar quantization based LDPC-coded modulation.