Multilevel inverters play a major role in the modern day medium and high power energy conversion processes. The classic two level voltage source inverter generates PWM pole voltage output having two levels with strong fundamental component and harmonics centered around the switching frequency and its multiples. With higher switching frequency, its components can be easily filtered and results in better Total harmonic distortion (THD) output voltage and current. But with higher switching frequency, switching loss of power devices increases and electromagnetic interferences also increases. Also in two level inverter, pole voltage switches between zero and DC bus volt-age Vdc. This switching results in high dv=dt and causes EMI and increased stress on the motor winding insulation. The attractive features of multilevel inverters compared to a two level inverter are reduced switching frequency, reduced switching loss, improved volt-age and current THD, reduced dv=dt, etc. Because of these reasons, multilevel invertersultilevelinvertersplayamajorroleinthemoderndaymediumandhighpower find application in electric motor drives, transmission and distribution of power, transportation, traction, distributed generation, renewable energy systems like photo voltaic, hydel power, energy management, power quality, electric vehicle applications, etc. AC motor driven applications are consuming the significant part of the generated electrical energy (more than 60%) around the world. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low with lower out-put voltage dv=dt. Also by using multilevel inverters, the common mode voltage (CMV) switching can be made zero and associated motor bearing failure can be mitigated. For multilevel inverter topologies, as the number of level increases, the power circuit becomes more complex by the increase in the number of DC power supplies, capacitors, switching devices and associated control circuitry. The main focus of development in multilevel inverter for medium and high power applications is to obtain an optimized number of voltage levels with reduced number of switching devices, capacitors and DC power sources. In this thesis, a new hybrid seven level inverter topology with a single DC supply is proposed with reduced switch count. The inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. Compared to the conventional seven level inverter topologies, the proposed inverter topology uses lesser number of semiconductor devices, capacitors and DC power supplies for its operation. For this topology, capacitor voltage balancing is possible for entire modulation range irrespective of the load power factor. Also capacitor voltage can be controlled over a switching cycle and this result in lowering the capacitor sizing for the proposed topology. A simple hysteresis band based capacitor voltage balancing scheme is implemented for the inverter topology. For a voltage source inverter fed induction motor drive system, the inverter pole voltage is the sum of motor phase voltage and common mode voltage. In induction motors, there exists a parasitic capacitance between stator winding and stator iron, and between stator winding and rotor iron. Common mode voltage with significant magnitude and high frequency switching causes leakage current through these parasitic capacitances and motor bearings. This leakage current can cause ash over of bearing lubricant and corrosion of ball bearings, resulting in an early mechanical failure of the drive system. In this thesis, analysis of extending the linear modulation range of a general n-level inverter by allowing reduced magnitude of common mode voltage (CMV) switching (only Vdc/18) is presented. A new hybrid seven level inverter topology, with a single DC supply and with reduced common mode voltage (CMV) switching is presented in this thesis for the first time. Inverter is operated with zero CMV for modulation index less than 86% and is operated with a CMV magnitude of Vdc/18 to extend the linear modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilizing the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology. In recent years, model predictive control (MPC) using the system model has proved to be a good choice for the control of power converter and motor drive applications. MPC predicts system behavior using a system model and current system state. For cascaded multilevel inverter topologies with a single DC supply, closed loop capacitor voltage control is necessary for proper operation. This thesis presents zero and reduced common mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state which minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96% the inverter can operate with reduced CMV magnitude ( Vdc/18) and reduced CMV switching frequency using the new space-vector PWM (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop V/f control scheme. The operation of a two level inverter in the over-modulation region (maximum peak phase fundamental output of inverter is greater than 0:577Vdc) results in lower order harmonics in the inverter output voltage. This lower order harmonics (mainly 5th, 7th, 11th, and 13th) causes electromagnetic torque ripple in motor drive applications. Also these harmonics causes extra losses and adversely affects the efficiency of the drive system. Also inverter control becomes non linear and special control algorithms are required for inverter operation in the over modulation region. In conventional schemes, maximum fundamental output voltage possible is 0:637Vdc. In that case inverter is operated in a square wave mode, also called six-step mode. This operation results in high dv=dt for the inverter output voltage. With multilevel inverters also, the inverter operation with peak phase fundamental output voltage above 0:577Vdc results in lower order harmonics in the inverter output voltage and results in electromagnetic torque pulsation. In this thesis, a new space vector PWM (SVPWM) method to extend the linear modulation range of a cascaded five level inverter topology with a single DC supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0:577Vdc to 0:637Vdc without increasing the DC bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0 Hz to 50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The ve level topology presented in this thesis is realized by cascading a two level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady state and dynamic operating conditions are presented. Zero common mode voltage (CMV) operation of multilevel inverters results in reduced DC bus utilization and reduced linear modulation range. In this thesis two reduced CMV SVPWM schemes are presented to extend the linear modulation range by allowing reduced CMV switching. But using these SVPWM schemes the peak phase fundamental output voltage possible is only 0:55Vdc in the linear region. In this thesis, a method to extend the linear modulation range of a CMV eliminated hybrid cascaded multilevel inverter with a single DC supply is presented. Using this method peak fundamental voltage can be increased from 0 to 0:637Vdc with zero CMV switching inside the linear modulation range. Also inverter can be controlled linearly for the entire modulation range. Also, various PWM switching sequences are analyzed in this thesis and the PWM sequence which gives minimum current ripple is used for the zero CMV operation of the inverter. The inverter topology with single DC supply is realized by cascading a two level inverter with two floating capacitor fed full bridge modules. Simulation and experimental results for steady state and dynamic operating conditions are presented to validate the proposed method. A three phase, 400 V, 3.7 kW, 50 Hz, two-pole induction motor drive with the open-loop V/f control scheme is implemented in the hardware for testing proposed inverter topology and proposed SVPWM algorithms experimentally. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V IGBT half-bridge modules (SKM-75GB-12T4). Optoisolated gate drivers with de-saturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation, TMS320F28335 DSP is used as the main controller and Xilinx SPARTAN-3 XC3S200 FPGA as the PWM signal generator with dead time of 2.5 s. Level shifted carrier-based PWM algorithm is implemented for the normal inverter operation and zero CMV operation. From the PWM algorithm, information about the pole voltage levels to be switched can be obtained for each phase. In the sampling period, for capacitor voltage balancing of each phase, the DSP selects a switching state using the capacitor voltage information, current direction and pole voltage data for each phase. This switching state information along with the PWM timing data is sent to an FPGA module. The FPGA module generates the gating signals with a dead time of 2.5 s for the gate driver module for all the three phases by processing the switching state information and PWM signals for the given sampling period. For fundamental frequencies above 10Hz, synchronous PWM technique was used for testing the inverter topology. For modulation frequencies 10Hz and below, a constant switching frequency of 900 Hz was used. Various steady state and transient operation results are provided to validate the proposed inverter topology and the zero and reduced CMV operation schemes and extending the linear modulation scheme presented in this thesis. With the advantages like reduced switch count, single DC supply requirement, zero and reduced CMV operation, extension of linear modulation range, linear control of induction motor over the entire modulation range with zero CMV, lesser dv=dt stresses on devices and motor phase windings, lower switching frequency, inherent capacitor balancing, the proposed inverter power circuit topologies, and the SVPWM methods can be considered as good choice for medium voltage, high power motor drive applications.

Electromagnetic interference (EMI) is a major concern in inverter motor drive systems. The sources of EMI have been commonly identified as high switching dv/dt and di/dt rates interacting with inverter parasitic components. The reduction of parasitic components relies on highly integrated circuit layout and packaging. This is the way to deal with noise path. On the other hand, switching dv/dt and di/dt can be potentially reduced by soft-switching techniques; thus the intensity of noise source is reduced. In this paper, the relation between the dv/dt di/dt and the EMI generation are discussed. The EMI sources of a hard-switching single-phase PWM inverter are identified and measured with separation of common-mode and differential-mode noises. The noise reduction in an auxiliary resonant snubber inverter (RSI) is presented. The observation of voltage ringing and current ringing and the methods to suppress these ringing in the implementation of RSI are also discussed. The test condition and circuit layout are described as the basis of the study. And the experimental EMI spectra of both hard- and soft-switching inverter are compared. The effectiveness and limitation of the EMI reduction of the ZVT-RSI are also discussed and concluded. The control interface circuit and gate driver design are described in the appendix. The implementation of variable charging time control of the resonant inductor current is also explained in the appendix. / Master of Science

The increased integration of distributed and renewable energy resources (DERs) has motivated the evolution of new standards in grid interconnection requirements. New standards have the requirement for the DERs to remain connected during the transient grid fault conditions and to offer support to the grid. This requirement is known as the fault ride-through (FRT) capability of the inverter-based DERs and is an increasingly important issue. This dissertation presents the FRT capability of the DERs that employ a voltage control strategy in their control systems. The voltage control strategy is increasingly replacing the current control strategy in the DERs due to the fact that it provides direct voltage support. However, the voltage control technique limits the ability of direct control over the inverter current. This presents a challenge in addressing the FRT capability where the problem is originally formulated in terms of the current control. This dissertation develops a solution for the FRT capability of inverters that use a voltage control strategy. The proposed controller enables the inverter to ride through the grid faults and support the grid by injecting a balanced current with completely controlled real and reactive power components. The proposed controller is flexible and can be used in connection with various voltage control strategies. Stability analysis of the proposed control structure is performed based on a new linear time-invariant model developed in this dissertation. This model significantly facilitates the stability and design of such control loops. Detailed simulation, real-time and experimental results are presented to evaluate the performance of the proposed control strategy in various operating conditions. Desirable transient and steady-state responses of the proposed controller are observed. Furthermore, the newly established German and Danish grid fault ride-through standards are implemented in this research as two application examples and the effectiveness of the dissertation results are illustrated in the context of those two examples.

No description available.

No description available.

No description available.

No description available.

No description available.

Renewable energy and distributed generation are getting more and more popular, including photovoltaic modules (PV), wind turbines, and fuel cells. The renewable energy sources need the power electronics interface to the utility grid because of different characteristics between the sources and the grid. No matter what renewable energy source is utilized, inverters are essential in the microgrid system. Thanks to flexible modular design, transformerless connection, extended voltage and power output, less maintenance and higher fault tolerance, the cascade inverters are good candidates for utility interface of various renewable energy sources. This dissertation proposes a new type of cascade inverters based on dual-buck topology and phase-shift control scheme. Compared to traditional cascade inverters, they have enhanced system reliability thanks to no shoot-through problems and lower switching loss with the help of using power MOSFETs. With phase-shift control, it theoretically eliminates the inherent current zero-crossing distortion of the single-unit dual-buck type inverter. In addition, phase-shift control can greatly reduce the ripple current or cut down the size of passive components by increasing the equivalent switching frequency. An asymmetrical half-cycle unipolar (AHCU) PWM technique is proposed for dual-buck full-bridge inverter. The proposed approach is to cut down the switching loss of power MOSFETs by half. At the same time, this AHCU PWM leads to current ripple reduction, and thus reducing ripple-related loss in filter components. Therefore, the proposed PWM strategy results in significant efficiency improvement. Additionally, the AHCU PWM also compensates for the zero-crossing distortion problem of dual-buck full-bridge inverter. Several PWM techniques are analyzed and compared, including bipolar PWM, unipolar PWM and phase-shifted PWM, when applied to the proposed cascade dual-buck full-bridge inverter. It has been found out that a PWM combination technique with the use of two out of the three PWMs leads to better performance in terms of less output current ripple and harmonics, no zero-crossing distortion, and higher efficiency. A grid-tie control system is proposed for cascade dual-buck inverter with both active and reactive power flow capability in a wide range under two types of renewable energy and distributed generation sources. Fuel cell power conditioning system (PCS) is Type I system with active power command generated by balance of plant (BOP) of each unit; and photovoltaic or wind PCS is Type II system with active power harvested by each front-end unit through maximum power point tracking (MPPT). Reactive power command is generated by distributed generation (DG) control site for both systems. Selective harmonic proportional resonant (PR) controller and admittance compensation controller are first introduced to cascade inverter grid-tie control to achieve better steady-state and dynamic performances. / Ph. D.

Due to the loose coupling nature and separated primary/secondary side, achieving tight load regulation or implementing closed-loop control of output voltage/current is nontrivial in a wireless power transfer (WPT) system. Previously presented methods for regulating or controlling the output of a WPT system include incorporating either post-regulator stage, wireless communication from secondary to primary side, primary side sensing and modulation scheme, or dual active bridge type of topology. However, all existing methods have limitations and disadvantages in terms of increased size/cost, control complexity, or reliability in electrically noisy environments. This dissertation proposes a single switch control and regulation mechanism based on the secondary side of the WPT system. Specifically, the duty cycle of the secondary side synchronous rectifier (SR) switch is modulated to control the output voltage or current. By modulating the SR duty cycle, output of the WPT system can be controlled without requiring additional regulator stages/power devices, a primary side sensing mechanism, or secondary to primary communication. The proposed control method lowers cost and simplifies the design of WPT systems while improving reliability in noisy environments. The proposed control and modulation mechanism maintains zero voltage switching of all power semiconductor switches so efficiency of the WPT system would not be compromised by implementing the proposed control scheme. The proposed secondary side SR based control method can be applied to dc-dc WPT systems to control output voltage or current, or it could be used in a dc-ac WPT system to generate and regulate ac output if combined with an unfolding stage. When used in dc-ac WPT systems, the bulky output filter stage usually required in conventional dc-ac inverters is eliminated. The proposed control scheme is evaluated with computer simulation as well as hardware implementation and testing. / Doctor of Philosophy / Wireless power transfer (WPT) is an emerging technology that supplies electric power to loads without using wires or electrical contacts. WPT technology has many promising uses in consumer, industrial, transportation, biomedical, and other applications. However, unlike controlling the output voltage of a conventional power supply or power converter, controlling the output of a WPT system is not a simple task due to the physical separation between the transmitting and receiving sides. State-of-the-art methods for controlling the output of a WPT system include adding another power regulator stage to regulate output, incorporating secondary side (power receiver) to primary side (power transmitter) communication so that output information can be passed back to the primary side where that information is used to monitor and regulate output. In some systems, output information may also be estimated indirectly from primary side voltage/current information. However, all these methods have significant disadvantages. Adding another power converter stage increases cost and efficiency loss of the WPT system. Incorporating secondary to primary communication for output control is detrimental to the reliability of the PWT system because communication may be impacted by external noise. The reliability of primary side sensing and regulation is also severely impacted by component parameter variations in the WPT system. This dissertation proposes a new mechanism that controls output of a WPT system at the receiver or secondary side without needing another power conversion stage, communication or any cooperation from primary side. The proposed control mechanism controls the turn on duration of the synchronous rectifier (SR) switch at the receiver side to modulate output voltage or current. Since SR technology is already prevalently used in power electronics systems, including WPT systems, to efficiently convert high frequency ac to dc before delivering power to the load, implementing the proposed control mechanism does not increase complexity or cost of the WPT system. The proposed control mechanism is useful in both dc-dc and dc-ac WPT systems. In a dc-dc WPT system, the proposed mechanism can control or regulate output voltage or current independently from the primary side, while in a dc-ac WPT system the proposed mechanism can generate and regulate ac output. If used in a dc-ac WPT system an unfolding stage needs to be added, but the bulky output filter stage required in conventional pulse width modulation (PWM) dc-ac inverters for suppressing switching ripple is not needed. The proposed mechanism is verified with computer simulation as well as hardware prototyping in this dissertation.