More and more embedded systems choose ARM-based micro-controllers as CPU. If no embedded OS built with the system, the application scope will be restricted. Therefore, the need of embedded OS is vital. There are many embedded OS¡¦s in the market, but the embedded Linux has many advantages and is widely accepted. Commercial embedded Linux takes less refund than other embedded OS¡¦s. The kernel and most applications are distributed in GPL open source copyright, and is highly portable to many machine platforms. Presently, the hardware key-technology is highly skilled. The margin of 3C industrial has gone down rapidly. Therefore, people focus on adapting integrated technology to practicality and innovation to make cost down. Developers choose appropriate ARM micro-controllers according to demanding functionality of their products. The microcontroller is not necessary running with Linux distribution. Two approaches can be used to resolve the embedded OS issue. The first approach is porting Linux to the platform without any refund. The second approach is to pay for commercial Linux. Embedded system peripheral devices aim at powerful functionalities and economy. For instance, UART interface is cheap and low data transfer rate. The target board communicates with host via RS-232. RS-232 acts as serial console to play dumb terminal under Linux. Industrial applications often make use of RS-xxx for UART physical transmission layer. For instance, RS-485 applies modbus protocol to build cheap monitor systems. Network transmission is a necessary function, and it generally achieves high data transfer rate application through Ethernet. The UNIX-like network socket has served network application very well. Embedded systems are usually diskless systems. In order to keep permanent data, using flash memory as block disk system is a widely adapted strategy and which operates flash memory through MTD subsystems¡][28]¡^. An MTD subsystem contains two different modules, ¡§user¡¨and ¡§driver¡¨. In the driver module, CFI¡][40]¡^ is applied to probe flash chip, partition it and provide operating function. Flash translation layer and file-system are applied in the user module. MTD BLOCK is used to emulate the flash partitions as block devices which are then mounted into Linux virtual file system¡]VFS¡^with JFFS2 type, designed according to the feature of flash devices. In this thesis, we will describe in detail the procedure of porting Linux to ARM micro-controllers. The motivation of the work is introduced in chapter 1. In chapter 2, we introduce development tools and the main flow of the porting procedure. In chapter 3, we describe the LH79525 platform and the main perepherals on the target board, then introduce the ARM programmer model. In chapter 4, we examine the required knowledge and the important issues for porting ARM Linux. In chapter 5, we describe the details of porting Linux to run with Sharp LH79525, including modifying the key source codes and adjusting kernel configuration for embedding the UART, ethernet MAC, and MTD subsystem. In chapter 6, we do step-by-step validation and apply an integrated application with the LF-314CP temperature controller¡][46]¡^ by law-chain technology for the LH79525 target board running with the ported ARM Linux. In chapter 7, we present some issues for future work and improvement, then make a conclusion for the thesis.

The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

This master thesis deals with the implementation of the control system for the forming machine used in producing of confectionery forms. The introductory part describes the forming machine from the point of important control elements. The second part is associated with the hardware design of the control automat and description of main functional units on the control PCB, as well as on other PCBs. The following text presents the communication protocol between the control automat and PC and after that there is a description of the CPU firmware. The final section brings the characteristics of the PC application for a connection with the automat.

Jusqu'à présent, le test de circuits intégrés et des systèmes au niveau wafer est basé sur un contact physique entre l'équipement de test et les circuits sur le wafer. Cette méthode basée sur le contact est limitée par plusieurs facteurs, tels que le nombre de circuits testés en parallèle, la réduction de la taille et de l'espacement entre les plots de contact, le nombre de contact avant que les plots soient endommagés, le coût des opérations de test, entre autres. Pour résoudre ces problèmes, nous proposons une nouvelle approche de test basée sur la communication sans fil entre le testeur et les circuits à tester (DUT). Pour cela, un Wireless Test Control Bloc (WTCB) est ajouté à chaque DUT sur le wafer comme une interface sans fil entre le testeur et les structures de test internes du DUT. Ce WTCB intègre une pile protocolaire de communication pour gérer la communication avec le testeur, et un Test Control Bloc (TCB) pour gérer l'application de test au niveau DUT. Profitant d'une transmission sans fil, le testeur peut diffuser les données de test à tous les DUT sur le wafer , maximisant le test simultané et réduisant donc le temps de test. En outre, notre architecture de WTCB permet une comparaison locale de la réponse de DUT avec la réponse correcte attendue par le testeur. En effectuant cette comparaison dans le WTCB du DUT, le testeur recueille de chaque DUT 1 seul bit comme résultat de la comparaison, au lieu d'une réponse complète, conduisant à un test sans fil plus rapide qui réduit le temps d'essai. Le WTCB a été mis en oeuvre sur FPGA, et une épreuve de test sans fil d'un circuit réel a été réalisée, prouvant la conception efficace de notre WTCB, et soulignant le potentiel de notre méthode de test sans fil, où elle peut être étendue et utilisée pour des applications de test in situ à distance. / So far, the test of integrated circuits and systems at wafer level relies on a physical contact between the test equipment and the devices under test on the wafer. This contact-based method is limited by several factors, such as the number of devices tested in parallel, the reduction of the size and the pitch of the bond pads, the number of touchdowns before bond pads are damaged, the cost of the test operations, among others. To solve these issues, we propose a novel test approach and architecture based on wireless communication between the tester and the devices under test (DUT). For that, a Wireless Test Control Block (WTCB) is added to every DUT on the wafer as a wireless interface between the tester and the internal test structures of the DUT. This WTCB embeds a communication protocol stack to manage the communication with the tester, and a Test Control Block to manage the test application at DUT level. Taking advantage of a wireless transmission, the tester can broadcast the test data to all DUT on the wafer in one path, maximizing the concurrent test, and reducing therefore the test time. Moreover, our WTCB architecture allows a local comparison of the DUT response with the correct response expected by the tester. By performing this comparison in the WTCB of the DUT, the tester collects from every DUT its 1-bit comparison result instead of a complete response, leading to a faster wireless test and extremely reduced test time. The WTCB has been implemented on FPGA, and a successful wireless test of a real circuit was performed, proving the efficient design of our WTCB, and highlighting the potential of our wireless test method, where it can be extended and used to perform a remote in-situ test.

This master's thesis deals with designing and implementation of universal programmer with JTAG interface. The project consists of a hardware and software part. Theoretical part discusses actual state in using the standards for programming and testing electronic devices, with special emphasis on JTAG implementation. Next part deals with programming ARM and FPGA devices through JTAG. The programming of this devices using available software is described in the practical part of this document. Final product of this work is the programmer itself. The programmer consists of the hardware and supplement software. At the end of this thesis there is a conclusion about possible improvements and development in the future.

Author concerns with SD memory cards and microcontroller Atmel ATmega128. He describes their architecture, features, properties and technology used in devices. He is mentioning principle of communication protocols used by SD card, through that cards can communicate with other connected devices. He analyzes the functionality of FAT file system. He describes the design and implementation of interfaces to connect the SD cards to microcontroller. He explains software solutions of this project and gives impartial view to usage and comparisons of implemented modes of communication witch card.

Ce travail de thèse a pour cadre le projet Trusted Environment Execution eVAluation (TEEVA) (projet français FUI n°20 de Janvier 2016 à Décembre 2018) qui vise à évaluer deux solutions alternatives de sécurisation des plateformes mobiles, l’une est purement logicielle, la Whitebox Crypto, alors que l’autre intègre des éléments logiciels et matériels, le Trusted Environment Execution (TEE). Le TEE s’appuie sur la technologie TrustZone d’ARM disponible sur de nombreux chipsets du marché tels que des smartphones et tablettes Android. Cette thèse se concentre sur l’architecture TEE, l’objectif étant d’analyser les menaces potentielles liées aux infrastructures de test/debug classiquement intégrées dans les circuits pour contrôler la conformité fonctionnelle après fabrication.Le test est une étape indispensable dans la production d’un circuit intégré afin d’assurer fiabilité et qualité du produit final. En raison de l’extrême complexité des circuits intégrés actuels, les procédures de test ne peuvent pas reposer sur un simple contrôle des entrées primaires avec des patterns de test, puis sur l’observation des réponses de test produites sur les sorties primaires. Les infrastructures de test doivent être intégrées dans le matériel au moment du design, implémentant les techniques de Design-for-Testability (DfT). La technique DfT la plus commune est l’insertion de chaînes de scan. Les registres sont connectés en une ou plusieurs chaîne(s), appelé chaîne(s) de scan. Ainsi, un testeur peut contrôler et observer les états internes du circuit à travers les broches dédiées. Malheureusement, cette infrastructure de test peut aussi être utilisée pour extraire des informations sensibles stockées ou traitées dans le circuit, comme par exemple des données fortement corrélées à une clé secrète. Une attaque par scan consiste à récupérer la clé secrète d’un crypto-processeur grâce à l’observation de résultats partiellement encryptés.Des expérimentations ont été conduites sur la carte électronique de démonstration avec le TEE afin d’analyser sa sécurité contre une attaque par scan. Dans la carte électronique de démonstration, une contremesure est implémentée afin de protéger les données sensibles traitées et sauvegardées dans le TEE. Les accès de test sont déconnectés, protégeant contre les attaques exploitant les infrastructures de test, au dépend des possibilités de test, diagnostic et debug après mise en service du circuit. Les résultats d’expérience ont montré que les circuits intégrés basés sur la technologie TrustZone ont besoin d’implanter une contremesure qui protège les données extraites des chaînes de scan. Outre cette simple contremesure consistant à éviter l’accès aux chaînes de scan, des contremesures plus avancées ont été développées dans la littérature pour assurer la sécurité tout en préservant l’accès au test et au debug. Nous avons analysé un état de l’art des contremesures contre les attaques par scan. De cette étude, nous avons proposé une nouvelle contremesure qui préserve l’accès aux chaînes de scan tout en les protégeant, qui s’intègre facilement dans un système, et qui ne nécessite aucun redesign du circuit après insertion des chaînes de scan tout en préservant la testabilité du circuit. Notre solution est basée sur l’encryption du canal de test, elle assure la confidentialité des communications entre le circuit et le testeur tout en empêchant son utilisation par des utilisateurs non autorisés. Plusieurs architectures ont été étudiées, ce document rapporte également les avantages et les inconvénients des solutions envisagées en terme de sécurité et de performance. / This work is part of the Trusted Environment Execution eVAluation (TEEVA) project (French project FUI n°20 from January 2016 to December 2018) that aims to evaluate two alternative solutions for secure mobile platforms: a purely software one, the Whitebox Crypto, and a TEE solution, which integrates software and hardware components. The TEE relies on the ARM TrustZone technology available on many of the chipsets for the Android smartphones and tablets market. This thesis focuses on the TEE architecture. The goal is to analyze potential threats linked to the test/debug infrastructures classically embedded in hardware systems for functional conformity checking after manufacturing.Testing is a mandatory step in the integrated circuit production because it ensures the required quality and reliability of the devices. Because of the extreme complexity of nowadays integrated circuits, test procedures cannot rely on a simple control of primary inputs with test patterns, then observation of produced test responses on primary outputs. Test facilities must be embedded in the hardware at design time, implementing the so-called Design-for-Testability (DfT) techniques. The most popular DfT technique is the scan design. Thanks to this test-driven synthesis, registers are connected in one or several chain(s), the so-called scan chain(s). A tester can then control and observe the internal states of the circuit through dedicated scan pins and components. Unfortunately, this test infrastructure can also be used to extract sensitive information stored or processed in the chip, data strongly correlated to a secret key for instance. A scan attack consists in retrieving the secret key of a crypto-processor thanks to the observation of partially encrypted results.Experiments have been conducted during the project on the demonstrator board with the target TEE in order to analyze its security against a scan-based attack. In the demonstrator board, a countermeasure is implemented to ensure the security of the assets processed and saved in the TEE. The test accesses are disconnected preventing attacks exploiting test infrastructures but disabling the test interfaces for testing, diagnosis and debug purposes. The experimental results have shown that chips based on TrustZone technology need to implement a countermeasure to protect the data extracted from the scan chains. Besides the simple countermeasure consisting to avoid scan accesses, further countermeasures have been developed in the literature to ensure security while preserving test and debug facilities. State-of-the-art countermeasures against scan-based attacks have been analyzed. From this study, we investigate a new proposal in order to preserve the scan chain access while preventing attacks, and to provide a plug-and-play countermeasure that does not require any redesign of the scanned circuit while maintaining its testability. Our solution is based on the encryption of the test communication, it provides confidentiality of the communication between the circuit and the tester and prevents usage from unauthorized users. Several architectures have been investigated, this document also reports pros and cons of envisaged solutions in terms of security and performance.

Embedded devices such as routers, switches, and firewalls commonly have sensitive information stored on them such as passwords, cryptographic keys, and information about the network around them and services that these device(s) provide. When disposing of or reselling this equipment in the secondary market it is crucial to erase this sensitive information. However, there is an important question that must be asked: Do the erase commands and routines offered by the device manufacturers actually erase the sensitive data? This thesis investigates methods and tools to determine the completeness of this erasure in some common network devices. These methods are used on a sample of networking equipment found to still contain sensitive information after being erased according to vendor recommendations. A computer program was developed to show how this information can be removed. The information in this document is useful for equipment owners, brokers and others looking to remarket their current equipment; all of whom want to minimize the risk of leaking sensitive data to other parties. / Nätverksutrustning såsom routrar, switchar och brandväggar har ofta känslig information lagrad internt, som lösenord, kryptografiska nycklar, information om nätverket runt dem samt tjänster de tillhandahåller. Om denna utrustning ska säljas på andrahandsmarkanden eller på annat sätt byta ägare är det viktigt att all känslig information raderas.  Men kan man lita på att raderings rutiner och metoder som tillhandahålls av tillverkaren verkligen raderar känslig data? Denna avhandling undersöker lämpliga verktyg och metoder för att granska vilken information som minnen i inbyggda system innehåller. Dessa metoder testas praktiskt på några system som visar sig ha kvar känslig information efter att de raderats enligt tillverkarens rekommendationer. Ett datorprogram som demonstrerar hur denna information kan undersökas och raderas finns med som en del av avhandlingen. Informationen i detta dokument är användbar för ägare av datakomutrustning, mäklare av sådana samt andra som vill minimera risken för att läcka känslig information vid återförsäljning av sin begagnade utrustning.

<p>Embedded and automated tests reduce maintenance costs for embedded systems installed in remote locations. Testing multiple components of an embedded system, connected on a scan chain, using deterministic test patterns stored in a system provide high fault coverage but require large system memory. This thesis presents an approach to reduce test data memory requirements by the use of a test controller program, utilizing the observation of that there are multiple components of the same type in a system. The program use deterministic test patterns specific to every component type, which is stored in system memory, to create fully defined test patterns when needed. By storing deterministic test patterns specific to every component type, the program can use the test patterns for multiple tests and several times within the same test. The program also has the ability to test parts of a system without affecting the normal functional operation of the rest of the components in the system and without an increase of test data memory requirements. Two experiments were conducted to determine how much test data memory requirements are reduced using the approach presented in this thesis. The results for the experiments show up to 26.4% reduction of test data memory requirements for ITC´02 SOC test benchmarks and in average 60% reduction of test data memory requirements for designs generated to gain statistical data.</p>

Embedded and automated tests reduce maintenance costs for embedded systems installed in remote locations. Testing multiple components of an embedded system, connected on a scan chain, using deterministic test patterns stored in a system provide high fault coverage but require large system memory. This thesis presents an approach to reduce test data memory requirements by the use of a test controller program, utilizing the observation of that there are multiple components of the same type in a system. The program use deterministic test patterns specific to every component type, which is stored in system memory, to create fully defined test patterns when needed. By storing deterministic test patterns specific to every component type, the program can use the test patterns for multiple tests and several times within the same test. The program also has the ability to test parts of a system without affecting the normal functional operation of the rest of the components in the system and without an increase of test data memory requirements. Two experiments were conducted to determine how much test data memory requirements are reduced using the approach presented in this thesis. The results for the experiments show up to 26.4% reduction of test data memory requirements for ITC´02 SOC test benchmarks and in average 60% reduction of test data memory requirements for designs generated to gain statistical data.