abstract: The fundamental building blocks for constructing complex synthetic gene networks are effective biological parts with wide dynamic range, low crosstalk, and modularity. RNA-based components are promising sources of such parts since they can provide regulation at the level of transcription and translation and their predictable base pairing properties enable large libraries to be generated through in silico design. This dissertation studies two different approaches for initiating interactions between RNA molecules to implement RNA-based components that achieve translational regulation. First, single-stranded domains known as toeholds were employed for detection of the highly prevalent foodborne pathogen norovirus. Toehold switch riboregulators activated by trigger RNAs from the norovirus RNA genome are designed, validated, and coupled with paper-based cell-free transcription-translation systems. Integration of paper-based reactions with synbody enrichment and isothermal RNA amplification enables as few as 160 copies/mL of norovirus from clinical samples to be detected in reactions that do not require sophisticated equipment and can be read directly by eye. Second, a new type of riboregulator that initiates RNA-RNA interactions through the loop portions of RNA stem-loop structures was developed. These loop-initiated RNA activators (LIRAs) provide multiple advantages compared to toehold-based riboregulators, exhibiting ultralow signal leakage in vivo, lacking any trigger RNA sequence constraints, and appending no additional residues to the output protein. Harnessing LIRAs as modular parts, logic gates that exploit loop-mediated control of mRNA folding state to implement AND and OR operations with up to three sequence-independent input RNAs were constructed. LIRA circuits can also be ported to paper-based cell-free reactions to implement portable systems with molecular computing and sensing capabilities. LIRAs can detect RNAs from a variety of different pathogens, such as HIV, Zika, dengue, yellow fever, and norovirus, and after coupling to isothermal amplification reactions, provide visible test results down to concentrations of 20 aM (12 RNA copies/µL). And the logic functionality of LIRA circuits can be used to specifically identify different HIV strains and influenza A subtypes. These findings demonstrate that toehold- and loop-mediated RNA-RNA interactions are both powerful strategies for implementing RNA-based computing systems for intracellular and diagnostic applications. / Dissertation/Thesis / Doctoral Dissertation Biochemistry 2019

Yes / Safety-critical systems are becoming larger and more complex to obtain a higher level of functionality. Hence, modeling and evaluation of these systems can be a difficult and error-prone task. Among existing safety models, Fault Tree Analysis (FTA) is one of the well-known methods in terms of easily understandable graphical structure. This study proposes a novel approach by using Machine Learning (ML) and real-time operational data to learn about the normal behavior of the system. Afterwards, if any abnormal situation arises with reference to the normal behavior model, the approach tries to find the explanation of the abnormality on the fault tree and then share the knowledge with the operator. If the fault tree fails to explain the situation, a number of different recommendations, including the potential repair of the fault tree, are provided based on the nature of the situation. A decision tree is utilized for this purpose. The effectiveness of the proposed approach is shown through a hypothetical example of an Aircraft Fuel Distribution System (AFDS). / DEIS H2020 Project under Grant 732242

No description available.

No / Synthetic Biology aspires to design, compose and engineer biological systems that implement specified behaviour. When designing such systems, hypothesis testing via computational modelling and simulation is vital in order to reduce the need of costly wet lab experiments. As a case study, we discuss the use of computational modelling and stochastic simulation for engineered genetic circuits that implement Boolean AND and OR gates that have been reported in the literature. We present performance analysis results for nine different state-of-the-art stochastic simulation algorithms and analyse the dynamic behaviour of the proposed gates. Stochastic simulations verify the desired functioning of the proposed gate designs.

Ion-selective polymeric optical sensors – ion optodes – are a promising alternative to ion-selective electrodes and fluorescent dyes for analytical and biological applications, e.g. extra- and intracellular measurements. They are non-toxic, highly selective robust probes for ionic fluxes monitoring. A large-scale fabrication of ion optodes using a solvent displacement method is introduced. This method is a single-batch process that does not require any additional steps. The influence of numerous parameters, e.g. surfactant concentration, solvent nature and membrane concentration, on the average size of the synthesized optodes was studied. The solvent displacement method allows control of the particle size in 200 nm to 30 μm range. Ion optodes selective for sodium, potassium, and calcium cations were prepared and calibrated for hydrogen (pH), sodium, potassium, and calcium. Fabricated sensors demonstrated excellent selectivity, low drift, high stability and reproducibility. Further studies of ion-optodes of different sizes but the same chemical composition revealed a significant shift in their response function. This bias is clearly seen for all fabricated optodes. A strong correlation between a calculated specific surface area and the apparent ion-exchange constant was observed. Considering this, it may be hypothesized that the surface phenomena are contributing to the overall optode response resulting in the observed effect. As a consequence, the response models, developed for the macroscopic ion optodes, cannot be easily applied to the probes at micron- and nano-scale. A primary concern for continuous sensing application of optical sensors is photobleaching of lipophilic fluorescent dye which prevents quantitative fluorescence measurements. Quantum dots, known for their high photostability, brightness and broad excitation spectra with narrow emission bands, were incorporated into polymeric matrix. They excited a fluorophore indirectly, thus, reducing its photobleaching and increasing sensors life-time. We created a composite, quantum dots doped, polymeric sensor that can be integrated into high-throughput detection platforms, such as flow cytometry, chip-based micro-total analysis system technologies, or bundled optical fiber arrays. Ultimately, a fabricated ion-optode was introduced into a Boolean logic gate serving as a reporting microparticle. It responded to the pH changes generated in situ by the enzyme logic system. The present work aimed scaling down the size of biocomputing functional units which might reach the information processing by single molecules associated with signal-transducing single nanoparticles. / Graduation date: 2012

Aborda-se, nesse trabalho, o fenômeno de envelhecimento de transistores MOS por bias temperature instability (BTI), relevante fator de degradação da confiabilidade e de redução do tempo de vida de circuitos integrados CMOS. Uma nova modelagem matemática determinística para BTI é introduzida, proporcionando, rapidamente, informação acerca do desvio na tensão de limiar de um transistor em decorrência da ação de BTI. O modelo é, então, implementado em uma ferramenta comercial SPICE, com o intuito de se verificarem, através de simulações transientes, os efeitos de BTI em circuitos CMOS; nesse sentido, a abordagem determinística representa um enorme avanço em relação à modelagem estocástica tradicional, que, muitas vezes, não pode ser aplicada em simulações transientes de circuitos complexos, devido ao seu vultoso custo computacional. O fenômeno de alargamento de pulso induzido pela propagação (PIPB) de single event transients (SETs), verificado experimentalmente na literatura, é estudado e tido como resultado da ação de BTI nas bordas de subida e descida do pulso transiente. À vista disso, simula-se a propagação de um pulso SET injetado na entrada de uma cadeia de 10000 inversores lógicos de tecnologia PTM bulk 90nm, verificando a dependência do alargamento de pulso com a tensão de alimentação, com o tempo de estresse DC anterior à aplicação do pulso e com a frequência do sinal de entrada. O aumento do atraso de portas lógicas em decorrência da ação de bias temperature instability é abordado, também, através da simulação da aplicação de um pulso nas entradas de uma porta NAND, medindo-se a variação do tempo de atraso de propagação devido à inserção da modelagem matemática para BTI. Utiliza-se novamente o modelo de transistores PTM bulk 90nm, e apuram-se os efeitos da variação da tensão de alimentação e do tempo de estresse DC no tempo de atraso de propagação. Por fim, as disparidades na variação do atraso para as bordas de subida e descida de pulsos lógicos de nível alto-baixo-alto (“101”) e baixo-alto-baixo (“010”) são verificadas, sendo explicadas em termos do diferente impacto de BTI para os períodos de estresse e de relaxação e, também, para transistores PMOS e NMOS. / This work addresses the aging of MOS transistors by bias temperature instability (BTI), which is a key factor to the degradation of the reliability and of the lifetime of CMOS integrated circuits. A novel deterministic mathematical model is presented, providing fast information about the impact of BTI in the transistors threshold voltage shifts. The model is implemented in a commercial SPICE tool, in order to verify the effects of BTI in CMOS circuits through transient simulations; in this sense, the deterministic approach represents a great advance compared to the traditional stochastic modelling, that may result in prohibitively long transient simulations for complex circuits, due to its huge computation cost. The phenomenon of propagation induced pulse broadening (PIPB) of single event transients (SETs), verified experimentally in the literature, is studied and understood as the result of the BTI effect on the rising and falling edges of the transient pulse. Therefore, the propagation of a SET injected in the input of a 10,000-inverters chain is simulated, using the PTM bulk 90nm technology model, verifying the dependence of the pulse broadening on the supply voltage, on the DC stress time previous to the application of the pulse and on the input signal frequency. The increase of the propagation delay of logic gates due the action of bias temperature instability is also studied through the simulation of the injection of a pulse in the inputs of a NAND gate, and the variation of the propagation delay time due to the BTI effect is evaluated. The PTM bulk 90nm model is used once again, and the outcome of variations on the supply voltage and on the DC stress time on the propagation delay is measured. Finally, the disparities on the delay variation for the rising and falling edges of high-low-high (“101”) and low-high-low (“010”) input logic pulses are verified, and they are explained as the result of the different impact of BTI for the stress and recovery periods and also for PMOS and NMOS transistors.

O emprego de ferramentas de automação de projetos de circuitos integrados permitiu que projetos complexos atingissem time-to-market e custos de produção factíveis. Neste contexto, o processo de síntese lógica é uma etapa fundamental no fluxo de projeto. O passo independente de tecnologia (parte do processo de síntese lógica, que é realizada sem considerar características físicas) é tradicionalmente realizado sobre equações. O desenvolvimento de novos algoritmos de otimização multi-nível recentemente migrou para o emprego de And-Inverter Graphs (AIGs). O número de nodos e a altura de um grafo apresentam melhor correlação com os resultados em área e atraso de um circuito, se comparados com as características de outras formas de representação. Neste trabalho, um algoritmo de síntese lógica independente de tecnologia, que funciona sobre uma estrutura de AIGs, é proposto. Uma nova abordagem para a construção de AIGs, baseada no novo paradigma de síntese chamado de composição funcional, é apresentado. Esta abordagem consiste em construir o AIG final através da associação de AIGs mais simples, em uma abordagem bottom-up. Durante a construção do grafo, o método controla as características dos grafos intermediários e finais, a partir da aplicação de uma função de custo, como forma de avaliação da qualidade desses AIGs. O objetivo é a minimização do número de nodos e da altura do AIG final. Este algoritmo de síntese lógica multi-objetivo apresenta características interessantes e vantagens quando comparado com abordagens tradicionais. Além disso, este trabalho apresenta a síntese de funções com múltiplas saídas em AIGs, o que melhora a característica de compartilhamento de estruturas, melhorando o circuito resultante. Resultados mostraram a melhora em torno de 5% em número de nodos, quando comparados com os resultados obtidos com a ferramenta ABC. / The use of design automation tools has allowed complex projects to reach feasible time-to-market and cost parameters. In this context, logic synthesis is a critical procedure in the design flow. The technology independent step (part of the logic synthesis which is performed regardless any physical property) is traditionally performed over equations. The development of new multi-level optimization algorithms has recently shifted towards the use of And-Inverter-Graphs (AIGs). The number of nodes and the graphs depth in AIGs present better correlation with resulting circuit area and delay than any characteristic of other representations. In this work, a technology independent synthesis algorithm that works on top of an AIG data structure is proposed. A novel approach for AIG construction, based on a new synthesis paradigm called functional composition, is introduced. This approach consists in building the final AIG by associating simpler AIGs, in a bottom-up approach. The method controls, during the graphs construction, the characteristics of final and intermediate graphs by applying a cost function as a way to evaluate the quality of those AIGs. The goal is to minimize the number of nodes and the depth of the final AIG. This multi-objective synthesis algorithm has presented interesting features and advantages when compared to traditional approaches. Moreover, this work presents a method for AIGs construction for multiple output functions, which enhances structural sharing, improving the resulting circuit. Results have shown an improvement of around 5% in number of nodes when compared to ABC tool.

MENEZES, José Wally Mendonça. Implementação de porta lógicas ópticas com acoplador direcional não linear triplo planar simétrico de fíbras ópticas. 2006. 111 f. Dissertação (Mestrado em Física) - Programa de Pós-Graduação em Física, Departamento de Física, Centro de Ciências, Universidade Federal do Ceará, Fortaleza, 2006. / Submitted by Edvander Pires (edvanderpires@gmail.com) on 2015-05-25T22:18:49Z No. of bitstreams: 1 2006_dis_jwmmenezes.pdf: 2170108 bytes, checksum: 0615686d0a317fa8d05e85006ca06e1b (MD5) / Approved for entry into archive by Edvander Pires(edvanderpires@gmail.com) on 2015-05-27T18:52:06Z (GMT) No. of bitstreams: 1 2006_dis_jwmmenezes.pdf: 2170108 bytes, checksum: 0615686d0a317fa8d05e85006ca06e1b (MD5) / Made available in DSpace on 2015-05-27T18:52:06Z (GMT). No. of bitstreams: 1 2006_dis_jwmmenezes.pdf: 2170108 bytes, checksum: 0615686d0a317fa8d05e85006ca06e1b (MD5) Previous issue date: 2006 / In this work, optical logical gates are proposed starting from the use of a symmetric three-core nonlinear directional coupler (NLDC) of fiber optic and with one of the guides operating as control. For such end, we obtain the characteristics of transmission of the coupler and, soon afterwards, we made an analysis of the extinction ratio and of the compression factor. Initially, we investigated the acting of the proposed coupler operating in the regime CW and later using ultra short pulses, type sóliton with 2ps of width. With the model proposed for the device, we got to execute logical gates AND, NAND, OR, XOR and NOT for a group of applied phases to the control pulse. The logical gates generated with the device operating with signs CW, they came more efficient than the same gates generated with soliton pulses. / Neste trabalho, portas lógicas ópticas são propostas a partir da utilização de um acoplador direcional não linear (NLDC) triplo planar simétrico de fibra óptica e com um dos guias operando como controle. Para tal fim, obtemos as características de transmissão do acoplador e, em seguida, fizemos uma análise do coeficiente de extinção e do fator de compressão. Inicialmente, investigamos o desempenho do acoplador proposto operando no regime CW e posteriormente utilizando pulsos ultracurtos, tipo sóliton com 2ps de largura. Com o modelo proposto para o dispositivo, conseguimos efetivar portas lógicas AND, NAND, OR, XOR e NOT para um conjunto de fases aplicadas ao pulso de controle. As portas lógicas geradas com o dispositivo operando com sinais CW, apresentaram-se mais eficientes que as mesmas portas geradas com sinais pulsados.

Aborda-se, nesse trabalho, o fenômeno de envelhecimento de transistores MOS por bias temperature instability (BTI), relevante fator de degradação da confiabilidade e de redução do tempo de vida de circuitos integrados CMOS. Uma nova modelagem matemática determinística para BTI é introduzida, proporcionando, rapidamente, informação acerca do desvio na tensão de limiar de um transistor em decorrência da ação de BTI. O modelo é, então, implementado em uma ferramenta comercial SPICE, com o intuito de se verificarem, através de simulações transientes, os efeitos de BTI em circuitos CMOS; nesse sentido, a abordagem determinística representa um enorme avanço em relação à modelagem estocástica tradicional, que, muitas vezes, não pode ser aplicada em simulações transientes de circuitos complexos, devido ao seu vultoso custo computacional. O fenômeno de alargamento de pulso induzido pela propagação (PIPB) de single event transients (SETs), verificado experimentalmente na literatura, é estudado e tido como resultado da ação de BTI nas bordas de subida e descida do pulso transiente. À vista disso, simula-se a propagação de um pulso SET injetado na entrada de uma cadeia de 10000 inversores lógicos de tecnologia PTM bulk 90nm, verificando a dependência do alargamento de pulso com a tensão de alimentação, com o tempo de estresse DC anterior à aplicação do pulso e com a frequência do sinal de entrada. O aumento do atraso de portas lógicas em decorrência da ação de bias temperature instability é abordado, também, através da simulação da aplicação de um pulso nas entradas de uma porta NAND, medindo-se a variação do tempo de atraso de propagação devido à inserção da modelagem matemática para BTI. Utiliza-se novamente o modelo de transistores PTM bulk 90nm, e apuram-se os efeitos da variação da tensão de alimentação e do tempo de estresse DC no tempo de atraso de propagação. Por fim, as disparidades na variação do atraso para as bordas de subida e descida de pulsos lógicos de nível alto-baixo-alto (“101”) e baixo-alto-baixo (“010”) são verificadas, sendo explicadas em termos do diferente impacto de BTI para os períodos de estresse e de relaxação e, também, para transistores PMOS e NMOS. / This work addresses the aging of MOS transistors by bias temperature instability (BTI), which is a key factor to the degradation of the reliability and of the lifetime of CMOS integrated circuits. A novel deterministic mathematical model is presented, providing fast information about the impact of BTI in the transistors threshold voltage shifts. The model is implemented in a commercial SPICE tool, in order to verify the effects of BTI in CMOS circuits through transient simulations; in this sense, the deterministic approach represents a great advance compared to the traditional stochastic modelling, that may result in prohibitively long transient simulations for complex circuits, due to its huge computation cost. The phenomenon of propagation induced pulse broadening (PIPB) of single event transients (SETs), verified experimentally in the literature, is studied and understood as the result of the BTI effect on the rising and falling edges of the transient pulse. Therefore, the propagation of a SET injected in the input of a 10,000-inverters chain is simulated, using the PTM bulk 90nm technology model, verifying the dependence of the pulse broadening on the supply voltage, on the DC stress time previous to the application of the pulse and on the input signal frequency. The increase of the propagation delay of logic gates due the action of bias temperature instability is also studied through the simulation of the injection of a pulse in the inputs of a NAND gate, and the variation of the propagation delay time due to the BTI effect is evaluated. The PTM bulk 90nm model is used once again, and the outcome of variations on the supply voltage and on the DC stress time on the propagation delay is measured. Finally, the disparities on the delay variation for the rising and falling edges of high-low-high (“101”) and low-high-low (“010”) input logic pulses are verified, and they are explained as the result of the different impact of BTI for the stress and recovery periods and also for PMOS and NMOS transistors.

O emprego de ferramentas de automação de projetos de circuitos integrados permitiu que projetos complexos atingissem time-to-market e custos de produção factíveis. Neste contexto, o processo de síntese lógica é uma etapa fundamental no fluxo de projeto. O passo independente de tecnologia (parte do processo de síntese lógica, que é realizada sem considerar características físicas) é tradicionalmente realizado sobre equações. O desenvolvimento de novos algoritmos de otimização multi-nível recentemente migrou para o emprego de And-Inverter Graphs (AIGs). O número de nodos e a altura de um grafo apresentam melhor correlação com os resultados em área e atraso de um circuito, se comparados com as características de outras formas de representação. Neste trabalho, um algoritmo de síntese lógica independente de tecnologia, que funciona sobre uma estrutura de AIGs, é proposto. Uma nova abordagem para a construção de AIGs, baseada no novo paradigma de síntese chamado de composição funcional, é apresentado. Esta abordagem consiste em construir o AIG final através da associação de AIGs mais simples, em uma abordagem bottom-up. Durante a construção do grafo, o método controla as características dos grafos intermediários e finais, a partir da aplicação de uma função de custo, como forma de avaliação da qualidade desses AIGs. O objetivo é a minimização do número de nodos e da altura do AIG final. Este algoritmo de síntese lógica multi-objetivo apresenta características interessantes e vantagens quando comparado com abordagens tradicionais. Além disso, este trabalho apresenta a síntese de funções com múltiplas saídas em AIGs, o que melhora a característica de compartilhamento de estruturas, melhorando o circuito resultante. Resultados mostraram a melhora em torno de 5% em número de nodos, quando comparados com os resultados obtidos com a ferramenta ABC. / The use of design automation tools has allowed complex projects to reach feasible time-to-market and cost parameters. In this context, logic synthesis is a critical procedure in the design flow. The technology independent step (part of the logic synthesis which is performed regardless any physical property) is traditionally performed over equations. The development of new multi-level optimization algorithms has recently shifted towards the use of And-Inverter-Graphs (AIGs). The number of nodes and the graphs depth in AIGs present better correlation with resulting circuit area and delay than any characteristic of other representations. In this work, a technology independent synthesis algorithm that works on top of an AIG data structure is proposed. A novel approach for AIG construction, based on a new synthesis paradigm called functional composition, is introduced. This approach consists in building the final AIG by associating simpler AIGs, in a bottom-up approach. The method controls, during the graphs construction, the characteristics of final and intermediate graphs by applying a cost function as a way to evaluate the quality of those AIGs. The goal is to minimize the number of nodes and the depth of the final AIG. This multi-objective synthesis algorithm has presented interesting features and advantages when compared to traditional approaches. Moreover, this work presents a method for AIGs construction for multiple output functions, which enhances structural sharing, improving the resulting circuit. Results have shown an improvement of around 5% in number of nodes when compared to ABC tool.