Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future technology generations. NBTI Aging of a Static Random Access Memory (SRAM) cell leads to a lower noise margin, thereby increasing the failure rate. The register file, which consists of an array of SRAM cells, can suffer from data loss, leading to a system failure. In this work, we study the source of NBTI stress in an architecture and physical register file. Based on our study, we modified the register file structure to reduce the NBTI degradation and improve the overall system reliability. Having evaluated new register file structures, we find that our techniques substantially improve reliability of the register files. The new register files have small overhead, while in some cases they provide saving in area and power.

Aplicações em ambientes expostos a elevados níveis de radiação ionizante impõem uma série de desafios ao desenvolvimento de projetos de circuitos integrados na tecnologia Complementary Metal–Oxide–Semiconductor (CMOS), uma vez que circuitos CMOS estão sujeitos às falhas transientes oriundas de radiação externa. Num circuito do tipo CMOS, as áreas sensíveis aos efeitos da incidência de partículas ionizantes são as regiões dreno-substrato reversamente polarizadas, existentes nos transistores em regime de corte (VARGAS; NICOLAIDIS, 1994). Com o avanço tecnológico e consequente diminuição das dimensões dos dispositivos semicondutores, estes efeitos degradantes tornam-se uma preocupação constante devido às menores características físicas dos transistores (WANG et al., 2007). Os circuitos integrados apresentam, durante a sua vida útil, um processo de degradação das suas características iniciais. Assim, a esse processo de degradação também chamamos de envelhecimento (aging). É um processo lento e cumulativo provocado por todos os mecanismos que acabam por alterar os parâmetros físicos e eléctricos dos circuitos, diminuindo o seu tempo de vida útil (FU; LI; FORTES, 2008). Dentre os efeitos de variabilidade temporal, os que mais têm causado interesse da comunidade científica são o Randon Telegraph Noise (RTN) com sua origem na atividade de traps (armadilhas) de interface e Single Event Transients (SET) com sua origem na radiação ionizante ao qual o circuito é exposto. Em relação aos efeitos de degradação destaca-se o efeito Bias Temperature Instability (BTI) (VALDUGA, 2012), que da mesma forma que o RTS, tem sua origem vinculada aos efeitos das traps.Modelos padrão para simulação elétrica de circuitos não levam em consideração os efeitos causados por armadilhas de cargas tais como Bias Temperature Instability (BTI) e Random Telegraph Noise (RTN). Tais variabilidades em nível de dispositivo podem causar perda de confiabilidade, como por exemplo, o surgimento de Propagation-Induced Pulse Broadening (PIPB). Conforme o escalonamento (scaling) tecnológico, a velocidade das portas lógicas aumenta e os SETs podem ser propagados através de circuito combinacional e, inclusive, sofrer alargamento, caso a largura do pulso transiente supere um valor mínimo crítico que depende da tecnologia (DODD et al., 2004), caracterizando assim um PIPB. Com base nisso, técnicas de injeção de falhas usadas em circuitos complexos não se mostram eficientemente previsíveis, levando a uma subestimativa da sensibilidade de circuitos à propagação de SETs. Com a utilização de um simulador elétrico que agrega a análise de BTI, temos melhores estimativas dos efeitos de PIPB na degradação de um circuito, que pode provocar violações de temporização em sistemas síncronos. Dessa forma, pode-se então trabalhar em uma projeção do circuito de forma a torná-lo mais robusto em relação aos efeitos de envelhecimento e na proteção às falhas transientes. Com base no que foi anteriormente apresentado, este trabalho analisa o comportamento de circuitos através de simulações elétricas de radiação ionizante, permitindo avaliações da suscetibilidade e confiabilidade de circuitos integrados aos efeitos de falhas transientes. Para a realização destes experimentos, foram realizadas simulações elétricas considerando-se os efeitos de envelhecimento. Para uma cadeia lógica de 2000 inversores sequencialmente dispostos na tecnologia 32nm pode-se prever que o pulso transiente está sujeito a um alargamento de sete vezes sua largura inicial no momento da incidência, para transistores em suas dimensões mínimas. A partir da proposta apresentada, pode-se determinar a possibilidade de alargamento ou atenuação de um SET ao longo do circuito de maneira eficiente para que as devidas precauções possam ser tomadas. / Applications in environments exposed to high levels of ionizing radiation impose a number of challenges for the development of integrated circuit designs in CMOS technology. CMOS circuits are vulnerable to transient faults from external radiation. In a CMOS circuit, areas sensitive to the effects of ionizing particle incidence are as reverse polarized drain-substrate regions in the transistors at cut-off (VARGAS; NICOLAIDIS, 1994). The technological advance and consequent downscaling of semiconductor devices, these degrading factors become a constant concern due to the higher vulnerability to transient faults (WANG et al., 2007). The integrated circuits have during their useful life a process of degradation of their initial characteristics. Thus, this process of degradation is also called aging. It is a slow and cumulative process caused by all the mechanisms that end up changing the physical and electrical parameters of the circuits, decreasing their useful timing life (FU; LI; FORTES, 2008). Among the temporal variability effects, the Randon Telegraph Noise (RTN) with its origin in the activity of traps (interface traps) and Single Event Transients (SET) with their origin in the ionizing radiation circuit is exposed. In terms of the effects of degradation, the Bias Temperature Instability (BTI) effect (VALDUGA, 2012) stands out, which, like the RTS, has its origin linked to the effects of the traps. Standard electrical simulation models do not take into account the effects caused by charged traps such as Bias temperature instability (BTI) and random telegraph noise (RTN). Such device-level variability can cause reduced reliability, for example, the Propagation-Induced Pulse Broadening (PIPB). According to the technological scaling, the speed of the logic gates increases and the SETs can be propagated through a combinational circuit and even may suffer broadening if the transient pulse width exceeds a critical minimum value that depends on the technology (DODD et al., 2004 ), characterizing a PIPB. Based on this, fault injection techniques in complex circuits are not efficiently in predicting, leading to an underestimation of circuit sensitivity to propagation of Single Event Transients (SETs). Using an electrical simulator that aggregates a BTI analysis, we have better estimates of PIPB effects on circuit degradation, which may lead to timing violations in synchronous systems. Then we can put effort in circuit design in order to make it more robust regarding to aging effects and transient faults protection. Based on what has been previously presented, this thesis analyzes the behavior of circuits through electrical simulations of ionizing radiation, allowing susceptibility and reliability evaluations of integrated circuits to the effects of transient faults using electrical simulations. For the accomplishment of these experiments, electrical simulations were performance considering the effects of aging. For a logic chain of 2000 inverters sequentially arranged in the 32nm technology it can be predicted that the transient pulse is subjected to a broadening of seven times its initial width at the time of incidence for transistors with minimum dimensions. From the analysis presented, we can evaluate the possibility of broadening or shrinking of SETs thought the circuit in an efficient way to improve radiation-hardening techniques.

Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to widen PMOS transistors later in a circuit?s life cycle to combat aging. Using HSPICE and 70nm BPTM process numbers, we simulated the technique on four circuits (a ring oscillator, a fan-out four circuit, an ISCAS c432 and c2670). Over the lifetime of the circuit, our simulations predict a 8.89% and a 13% improvement in power in the c432 and c2670 circuits respectively when compared to similarly performing traditional circuits.

With the gradual advance of the state-of-the-art VLSI manufacturing technology into the sub-45nm regime, engineering a reliable, high performance VLSI chip with economically attractive yield in accordance with Moore's law of scaling and integration has become extremely difficult. Some of the most serious challenges that make this task difficult are: a) the delay of a transistor is strongly dependent on process induced mechanical stress around it, b) the reliability of devices is affected by several aging mechanisms like Negative Bias Temperature Instability (NBTI), hot carrier injection (HCI), etc and c) the delay and reliability of any device are strongly related to lithographically drawn geometry of various features on wafer. These three challenges are the main focus of this dissertation. High performance fabrication processes routinely use embedded silicon-germanium (eSiGe) technology that imparts compressive mechanical stress to PMOS devices. In this work, cell level timing models considering flexibility to modulate active area to change mechanical stress, were proposed and exploited to perform timing optimization during circuit placement phase. Analysis of key physical synthesis optimization steps such as gate sizing and repeater insertion was done to understand and exploit mechanical stress to significantly improve delay of interconnect and device dominated circuits. Regarding circuit reliability, the proposed work is focused on reducing the clock skew degradation due to NBTI effect specially due to the use of clock gating technique for achieving low power operation. In addition, we also target the detrimental impact of burn-in testing on NBTI. The problem is identified and a runtime technique to reduce clock skew increase was proposed. For designs with predictable clock gating activities, a zero overhead design time technique was proposed to reduce clock skew increase over time. The concept of using minimum degradation input vector during static burn-in testing is proposed to reduce the impact of burn-in testing on parametric yield. Delay and reliability strongly depend on dimension of various features on the wafer such as gate oxide thickness, channel length and contact position. Increased variability of these dimensions can severely restrict ability to analyze or optimize a design considering mechanical stress and circuit reliability. One key technique to control physical variability is to move towards regular fabrics. However, to make implementation on regular fabrics attractive, high quality physical design tools need to be developed. This dissertation proposes a new circuit placement algorithm to place a design on a structured ASIC platform with strict site and clock constraints and excellent overall wirelength. An algorithm for reducing the clock and leakage power dissipation of a structured ASIC by reducing spine usage is then proposed to allow lower power dissipation of designs implemented using structured ASICs. / text

Aplicações em ambientes expostos a elevados níveis de radiação ionizante impõem uma série de desafios ao desenvolvimento de projetos de circuitos integrados na tecnologia Complementary Metal–Oxide–Semiconductor (CMOS), uma vez que circuitos CMOS estão sujeitos às falhas transientes oriundas de radiação externa. Num circuito do tipo CMOS, as áreas sensíveis aos efeitos da incidência de partículas ionizantes são as regiões dreno-substrato reversamente polarizadas, existentes nos transistores em regime de corte (VARGAS; NICOLAIDIS, 1994). Com o avanço tecnológico e consequente diminuição das dimensões dos dispositivos semicondutores, estes efeitos degradantes tornam-se uma preocupação constante devido às menores características físicas dos transistores (WANG et al., 2007). Os circuitos integrados apresentam, durante a sua vida útil, um processo de degradação das suas características iniciais. Assim, a esse processo de degradação também chamamos de envelhecimento (aging). É um processo lento e cumulativo provocado por todos os mecanismos que acabam por alterar os parâmetros físicos e eléctricos dos circuitos, diminuindo o seu tempo de vida útil (FU; LI; FORTES, 2008). Dentre os efeitos de variabilidade temporal, os que mais têm causado interesse da comunidade científica são o Randon Telegraph Noise (RTN) com sua origem na atividade de traps (armadilhas) de interface e Single Event Transients (SET) com sua origem na radiação ionizante ao qual o circuito é exposto. Em relação aos efeitos de degradação destaca-se o efeito Bias Temperature Instability (BTI) (VALDUGA, 2012), que da mesma forma que o RTS, tem sua origem vinculada aos efeitos das traps.Modelos padrão para simulação elétrica de circuitos não levam em consideração os efeitos causados por armadilhas de cargas tais como Bias Temperature Instability (BTI) e Random Telegraph Noise (RTN). Tais variabilidades em nível de dispositivo podem causar perda de confiabilidade, como por exemplo, o surgimento de Propagation-Induced Pulse Broadening (PIPB). Conforme o escalonamento (scaling) tecnológico, a velocidade das portas lógicas aumenta e os SETs podem ser propagados através de circuito combinacional e, inclusive, sofrer alargamento, caso a largura do pulso transiente supere um valor mínimo crítico que depende da tecnologia (DODD et al., 2004), caracterizando assim um PIPB. Com base nisso, técnicas de injeção de falhas usadas em circuitos complexos não se mostram eficientemente previsíveis, levando a uma subestimativa da sensibilidade de circuitos à propagação de SETs. Com a utilização de um simulador elétrico que agrega a análise de BTI, temos melhores estimativas dos efeitos de PIPB na degradação de um circuito, que pode provocar violações de temporização em sistemas síncronos. Dessa forma, pode-se então trabalhar em uma projeção do circuito de forma a torná-lo mais robusto em relação aos efeitos de envelhecimento e na proteção às falhas transientes. Com base no que foi anteriormente apresentado, este trabalho analisa o comportamento de circuitos através de simulações elétricas de radiação ionizante, permitindo avaliações da suscetibilidade e confiabilidade de circuitos integrados aos efeitos de falhas transientes. Para a realização destes experimentos, foram realizadas simulações elétricas considerando-se os efeitos de envelhecimento. Para uma cadeia lógica de 2000 inversores sequencialmente dispostos na tecnologia 32nm pode-se prever que o pulso transiente está sujeito a um alargamento de sete vezes sua largura inicial no momento da incidência, para transistores em suas dimensões mínimas. A partir da proposta apresentada, pode-se determinar a possibilidade de alargamento ou atenuação de um SET ao longo do circuito de maneira eficiente para que as devidas precauções possam ser tomadas. / Applications in environments exposed to high levels of ionizing radiation impose a number of challenges for the development of integrated circuit designs in CMOS technology. CMOS circuits are vulnerable to transient faults from external radiation. In a CMOS circuit, areas sensitive to the effects of ionizing particle incidence are as reverse polarized drain-substrate regions in the transistors at cut-off (VARGAS; NICOLAIDIS, 1994). The technological advance and consequent downscaling of semiconductor devices, these degrading factors become a constant concern due to the higher vulnerability to transient faults (WANG et al., 2007). The integrated circuits have during their useful life a process of degradation of their initial characteristics. Thus, this process of degradation is also called aging. It is a slow and cumulative process caused by all the mechanisms that end up changing the physical and electrical parameters of the circuits, decreasing their useful timing life (FU; LI; FORTES, 2008). Among the temporal variability effects, the Randon Telegraph Noise (RTN) with its origin in the activity of traps (interface traps) and Single Event Transients (SET) with their origin in the ionizing radiation circuit is exposed. In terms of the effects of degradation, the Bias Temperature Instability (BTI) effect (VALDUGA, 2012) stands out, which, like the RTS, has its origin linked to the effects of the traps. Standard electrical simulation models do not take into account the effects caused by charged traps such as Bias temperature instability (BTI) and random telegraph noise (RTN). Such device-level variability can cause reduced reliability, for example, the Propagation-Induced Pulse Broadening (PIPB). According to the technological scaling, the speed of the logic gates increases and the SETs can be propagated through a combinational circuit and even may suffer broadening if the transient pulse width exceeds a critical minimum value that depends on the technology (DODD et al., 2004 ), characterizing a PIPB. Based on this, fault injection techniques in complex circuits are not efficiently in predicting, leading to an underestimation of circuit sensitivity to propagation of Single Event Transients (SETs). Using an electrical simulator that aggregates a BTI analysis, we have better estimates of PIPB effects on circuit degradation, which may lead to timing violations in synchronous systems. Then we can put effort in circuit design in order to make it more robust regarding to aging effects and transient faults protection. Based on what has been previously presented, this thesis analyzes the behavior of circuits through electrical simulations of ionizing radiation, allowing susceptibility and reliability evaluations of integrated circuits to the effects of transient faults using electrical simulations. For the accomplishment of these experiments, electrical simulations were performance considering the effects of aging. For a logic chain of 2000 inverters sequentially arranged in the 32nm technology it can be predicted that the transient pulse is subjected to a broadening of seven times its initial width at the time of incidence for transistors with minimum dimensions. From the analysis presented, we can evaluate the possibility of broadening or shrinking of SETs thought the circuit in an efficient way to improve radiation-hardening techniques.

Aplicações em ambientes expostos a elevados níveis de radiação ionizante impõem uma série de desafios ao desenvolvimento de projetos de circuitos integrados na tecnologia Complementary Metal–Oxide–Semiconductor (CMOS), uma vez que circuitos CMOS estão sujeitos às falhas transientes oriundas de radiação externa. Num circuito do tipo CMOS, as áreas sensíveis aos efeitos da incidência de partículas ionizantes são as regiões dreno-substrato reversamente polarizadas, existentes nos transistores em regime de corte (VARGAS; NICOLAIDIS, 1994). Com o avanço tecnológico e consequente diminuição das dimensões dos dispositivos semicondutores, estes efeitos degradantes tornam-se uma preocupação constante devido às menores características físicas dos transistores (WANG et al., 2007). Os circuitos integrados apresentam, durante a sua vida útil, um processo de degradação das suas características iniciais. Assim, a esse processo de degradação também chamamos de envelhecimento (aging). É um processo lento e cumulativo provocado por todos os mecanismos que acabam por alterar os parâmetros físicos e eléctricos dos circuitos, diminuindo o seu tempo de vida útil (FU; LI; FORTES, 2008). Dentre os efeitos de variabilidade temporal, os que mais têm causado interesse da comunidade científica são o Randon Telegraph Noise (RTN) com sua origem na atividade de traps (armadilhas) de interface e Single Event Transients (SET) com sua origem na radiação ionizante ao qual o circuito é exposto. Em relação aos efeitos de degradação destaca-se o efeito Bias Temperature Instability (BTI) (VALDUGA, 2012), que da mesma forma que o RTS, tem sua origem vinculada aos efeitos das traps.Modelos padrão para simulação elétrica de circuitos não levam em consideração os efeitos causados por armadilhas de cargas tais como Bias Temperature Instability (BTI) e Random Telegraph Noise (RTN). Tais variabilidades em nível de dispositivo podem causar perda de confiabilidade, como por exemplo, o surgimento de Propagation-Induced Pulse Broadening (PIPB). Conforme o escalonamento (scaling) tecnológico, a velocidade das portas lógicas aumenta e os SETs podem ser propagados através de circuito combinacional e, inclusive, sofrer alargamento, caso a largura do pulso transiente supere um valor mínimo crítico que depende da tecnologia (DODD et al., 2004), caracterizando assim um PIPB. Com base nisso, técnicas de injeção de falhas usadas em circuitos complexos não se mostram eficientemente previsíveis, levando a uma subestimativa da sensibilidade de circuitos à propagação de SETs. Com a utilização de um simulador elétrico que agrega a análise de BTI, temos melhores estimativas dos efeitos de PIPB na degradação de um circuito, que pode provocar violações de temporização em sistemas síncronos. Dessa forma, pode-se então trabalhar em uma projeção do circuito de forma a torná-lo mais robusto em relação aos efeitos de envelhecimento e na proteção às falhas transientes. Com base no que foi anteriormente apresentado, este trabalho analisa o comportamento de circuitos através de simulações elétricas de radiação ionizante, permitindo avaliações da suscetibilidade e confiabilidade de circuitos integrados aos efeitos de falhas transientes. Para a realização destes experimentos, foram realizadas simulações elétricas considerando-se os efeitos de envelhecimento. Para uma cadeia lógica de 2000 inversores sequencialmente dispostos na tecnologia 32nm pode-se prever que o pulso transiente está sujeito a um alargamento de sete vezes sua largura inicial no momento da incidência, para transistores em suas dimensões mínimas. A partir da proposta apresentada, pode-se determinar a possibilidade de alargamento ou atenuação de um SET ao longo do circuito de maneira eficiente para que as devidas precauções possam ser tomadas. / Applications in environments exposed to high levels of ionizing radiation impose a number of challenges for the development of integrated circuit designs in CMOS technology. CMOS circuits are vulnerable to transient faults from external radiation. In a CMOS circuit, areas sensitive to the effects of ionizing particle incidence are as reverse polarized drain-substrate regions in the transistors at cut-off (VARGAS; NICOLAIDIS, 1994). The technological advance and consequent downscaling of semiconductor devices, these degrading factors become a constant concern due to the higher vulnerability to transient faults (WANG et al., 2007). The integrated circuits have during their useful life a process of degradation of their initial characteristics. Thus, this process of degradation is also called aging. It is a slow and cumulative process caused by all the mechanisms that end up changing the physical and electrical parameters of the circuits, decreasing their useful timing life (FU; LI; FORTES, 2008). Among the temporal variability effects, the Randon Telegraph Noise (RTN) with its origin in the activity of traps (interface traps) and Single Event Transients (SET) with their origin in the ionizing radiation circuit is exposed. In terms of the effects of degradation, the Bias Temperature Instability (BTI) effect (VALDUGA, 2012) stands out, which, like the RTS, has its origin linked to the effects of the traps. Standard electrical simulation models do not take into account the effects caused by charged traps such as Bias temperature instability (BTI) and random telegraph noise (RTN). Such device-level variability can cause reduced reliability, for example, the Propagation-Induced Pulse Broadening (PIPB). According to the technological scaling, the speed of the logic gates increases and the SETs can be propagated through a combinational circuit and even may suffer broadening if the transient pulse width exceeds a critical minimum value that depends on the technology (DODD et al., 2004 ), characterizing a PIPB. Based on this, fault injection techniques in complex circuits are not efficiently in predicting, leading to an underestimation of circuit sensitivity to propagation of Single Event Transients (SETs). Using an electrical simulator that aggregates a BTI analysis, we have better estimates of PIPB effects on circuit degradation, which may lead to timing violations in synchronous systems. Then we can put effort in circuit design in order to make it more robust regarding to aging effects and transient faults protection. Based on what has been previously presented, this thesis analyzes the behavior of circuits through electrical simulations of ionizing radiation, allowing susceptibility and reliability evaluations of integrated circuits to the effects of transient faults using electrical simulations. For the accomplishment of these experiments, electrical simulations were performance considering the effects of aging. For a logic chain of 2000 inverters sequentially arranged in the 32nm technology it can be predicted that the transient pulse is subjected to a broadening of seven times its initial width at the time of incidence for transistors with minimum dimensions. From the analysis presented, we can evaluate the possibility of broadening or shrinking of SETs thought the circuit in an efficient way to improve radiation-hardening techniques.

Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.

Avec la tendance continue vers la technologie nanométrique et l'augmentation des fonctions complexes intègres dans les électroniques systèmes embarqués, Assurant la compatibilité électromagnétique (CEM) des systèmes électroniques est un grand défi. CEM est devenu une cause majeure de redesign des Circuits intègres (CI). D’ailleurs, les performances des circuits pourraient être affectés par les mécanismes de dégradation tels que hot carrier injection (HCI), negative bias temperature instability (NBTI), gate oxide breakdown, qui sont accélérés par les conditions d'exploitation extrême (haute / basse température, surcharge électrique, le rayonnement). Ce vieillissement naturel peut donc affecter les performances CEM des circuits intégrés.Les travaux développés dans notre laboratoire vise à clarifier le lien entre les dégradations induites par le vieillissement et les dérives CEM, de développer les modèles de prédiction et de proposer des "insensibles au cours du temps" structures pour CEM protection, afin de fournir des méthodes et des guidelines aux concepteurs d'équipements et CI pour garantir la CEM au cours de durée de vie de leurs applications. Ce sujet de recherche est encore sous-exploré en tant que communautés de recherche sur la «fiabilité IC» et «compatibilité électromagnétique IC» n’a souvent pas de chevauchement.Ce manuscrit de thèse introduit une méthode pour quantifier l'effet du vieillissement sur les CEM des circuits intégrés par la mesure et la simulation. Le premier chapitre donne un aperçu du contexte général et le deuxième chapitre est dédié a l’état de l'art de CEM des circuits intégrés et de problèmes de fiabilité IC. Les résultats expérimentaux de circuits CEM évolution sont présentés dans le troisième chapitre. Ensuite, le quatrième chapitre est consacré à la caractérisation et la modélisation des mécanismes de dégradation du CI. Un EMR modèle qui inclut l'élément le vieillissement pour prédire la dérive du niveau CEM de notre puce de test après stress est proposé / With the continuous trend towards nanoscale technology and increased integration of complex electronic functions in embedded systems, ensuring the electromagnetic compatibility (EMC) of electronic systems is a great challenge. EMC has become a major cause of IC redesign. Meanwhile, ICs performance could be affected by the degradation mechanisms such as hot carrier injection (HCI), negative bias temperature instability(NBTI), gate oxide breakdown, which are accelerated by the harsh operation conditions (high/low temperature, electrical overstress, radiation). This natural aging can thus affect EMC performances of ICs. The work developed in our laboratory aims at clarifying the link between ageing induced IC degradations and related EMC drifts, developing prediction models and proposing “time insensitive” EMC protection structures, in order to provide methods and guidelines to IC and equipment designers to ensure EMC during lifetime of their applications. This research topic is still under-explored as research communities on “IC reliability” and “IC electromagnetic compatibility” has often no overlap. The PhD manuscript introduced a methodology to quantify the effect of ageing on EMC of ICs by measurement and simulation. The first chapter gives an overview of the general context and the second chapter states the EMC of ICs state of the art and IC reliability issues. The experimental results of ICs EMC evolution are presented in the third chapter. Then, the fourth chapter is dedicated to the characterization and modeling IC degradation mechanism. An EMR model which includes the ageing element to predict our test chip’s EMC level drift after stress is proposed

Actuellement, les circuits numériques nécessitent d'être de plus en plus performants. Aussi, les produits doivent être conçus le plus rapidement possible afin de gagner les précieuses parts de marché. Les méthodes rapides de conception et l'utilisation de MPSoC ont permis de satisfaire à ces exigences, mais sans tenir compte précisément de l'impact du vieillissement des circuits sur la conception. Or les MPSoC utilisent les technologies de fabrication les plus récentes et sont de plus en plus soumis aux défaillances matérielles. De nos jours, les principaux mécanismes de défaillance observés dans les transistors des MPSoC sont le HCI et le NBTI. Des marges sont alors ajoutées pour que le circuit soit fonctionnel pendant son utilisation, en considérant le cas le plus défavorable pour chaque mécanisme. Ces marges deviennent de plus en plus importantes et diminuent les performances attendues. C'est pourquoi les futures méthodes de conception nécessitent de tenir compte des dégradations matérielles en fonction de l’utilisation du circuit. Dans cette thèse, nous proposons une méthode originale pour simuler le vieillissement des MPSoC à haut niveau d'abstraction. Cette méthode s'applique lors de la conception du système c.-à-d. entre l'étape de définition des spécifications et la mise en production. Un modèle empirique permet d'estimer les dégradations temporelles en fin de vie d'un circuit. Un exemple d'application est donné pour un processeur embarqué et les résultats pour un ensemble d'applications sont reportés. La solution proposée permet d'explorer différentes configurations d'une architecture MPSoC pour comparer le vieillissement. Aussi, l'application la plus sévère pour le vieillissement peut être identifiée. / Nowadays, more and more performance is expected from digital circuits. What’s more, the market requires fast conception methods, in order to propose the newest technology available. Fast conception methods and the utilization of MPSoC have enabled high performance and short time-to-market while taking little attention to aging. However, MPSoC are more and more prone to hardware failures that occur in transistors. Today, the prevailing failure mechanisms in MPSoC are HCI and NBTI. Margins are usually added on new products to avoid failures during execution, by considering worst case scenario for each mechanism. For the newest technology, margins are becoming more and more important and products performance is getting lower and lower. That’s why the conception needs to take into account hardware failures according to the execution of software. This thesis propose a new methodology to simulate aging at high level of abstraction, which can be applied to MPSoC. The method can be applied during product conception, between the specification phase and the production. An empirical model is used to estimate slack time at circuit's end of life. A use case is conducted on an embedded processor and degradation results are reported for a set of applications. The solution enables architecture exploration and MPSoC aging can thus be compared. The software with most severe impact on aging can also be determined.

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.