Time Sensitive Networking (TSN) defined in the IEEE 802.1 working group, is an important enabler for industrial Internet of things, specifically industry 4.0. 3GPP release 16 specifications includes the 5G system as a logical TSN bridge, thus promoting the integration of 5G technology with TSN. This combination provides wireless deterministic communication thus ensuring low, bounded delay and near-zero packet loss. In this thesis, we implement a 5G system in- tegration with TSN using a discrete event network simulator (NS-3). Further, we propose a simplified per egress port scheduling algorithm based on IEEE 802.1Q (scheduled traffic standard) running in the Centralized Network Con- troller (CNC). Average packet delay, average jitter, average throughput and the packet loss is measured for comparing the performance difference when our TSN scheduler is used versus when it is not. The designed system is tested by measuring it’s network impact in terms of average delay and packet loss. The 5GS logical bridge behavior is simulated by varying the 5G bridge de- lay dynamically. For every frame transmission in the queue, the processing delay of a particular bridge is varied with pre-defined set of values. Two sets of 5GS bridge delay variations are considered, i.e. between 1-10ms and 5- 10ms respectively. On calculating the network impact, we conclude that the overall impact on the network decreases as the variation range for the delay gets smaller. This proves that higher delay variations have a significant impact whereas smaller delay variations have a negligible impact on the network. For the latter case, the system delay is considerably stable and thus can be used for industrial applications in real-life TSN scenarios. / Tidskritiska nätverk (TSN) definierat i IEEE 802.1-arbetsgruppen, är en vik- tig faktor för det industriella Sakernas Internet, särskilt när det gäller Industri4.0. Specifikationer enligt 3GPP release 16 inkluderar 5G-system som en lo- gisk TSN-brygga, som främjar integrationen av 5G-teknik med TSN. 5G med TSN ger trådlös deterministisk kommunikation som säkerställer låg, begrän- sad fördröjning och nästan noll paketförlust. I denna rapport implementerar vi en 5G-systemintegration med TSN med hjälp av en diskret händelse simu- lator (NS-3). Dessutom föreslår vi en förenklad algoritm för schemaläggning av portar per utgång baserat på IEEE 802.1Q (Scheduled Traffic Standard) som körs i en centraliserad nätverks-controller (CNC). Genomsnittlig paket- fördröjning, genomsnittlig fördröjningsvariation, genomsnittlig genomström- ning och paketförlust mäts för att jämföra prestandaskillnaden när vår TSN- schemaläggare används jämfört med när den inte används. Det utformade sy- stemet testas genom att mäta nätverkets påverkan i termer av genomsnittlig fördröjning och paketförlust. 5GS logiska bryggbeteende simuleras genom att dynamiskt variera 5G-bryggfördröjningen. För varje bildöverföring varieras bryggans bearbetningsfördröjning med en fördefinierad uppsättning värden. Två fördefinierade uppsättningar av 5GS-fördröjningsvariationer beaktas som ligger mellan 1-10ms respektive 5-10ms. När vi beräknar nätverkspåverkan drar vi slutsatsen att den totala effekten på nätverket minskar när variationen i fördröjningen blir mindre. Detta visar att högre fördröjningsvariationer har en signifikant effekt medan mindre fördröjningsvariationer har en försumbar effekt. I det senare fallet är systemfördröjningen betydligt stabilare och kan användas för tillämpningar i verkliga TSN-scenarier.

Graphics Processing Units (GPUs) are emerging as the most popular accelerator for many applications, powering the core of Machine Learning applications and many computing-intensive workloads. GPUs have typically been consideredas accelerators, with Central Processing Units (CPUs) in charge of the mainapplication logic, data movement, and network connectivity. In these architectures,input and output data of network-based GPU-accelerated application typically traverse the CPU, and the Operating System network stack multiple times, getting copied across the system main memory. These increase application latency and require expensive CPU cycles, reducing the power efficiency of systems, and increasing the overall response times. These inefficiencies become of higher importance in latency-bounded deployments, or with high throughput, where copy times could easily inflate the response time of modern GPUs. The main contribution of this dissertation is towards a GPU-centric network architecture, allowing GPUs to initiate network transfers without the intervention of CPUs. We focus on commodity hardware, using NVIDIA GPUs and Remote Direct Memory Access over Converged Ethernet (RoCE) to realize this architecture, removing the need of highly homogeneous clusters and ad-hoc designed network architecture, as it is required by many other similar approaches. By porting some rdma-core posting routines to GPU runtime, we can saturate a 100-Gbps link without any CPU cycle, reducing the overall system response time, while increasing the power efficiency and improving the application throughput.The second contribution concerns the analysis of Clockwork, a State-of-The-Art inference serving system, showing the limitations imposed by controller-centric, CPU-mediated architectures. We then propose an alternative architecture to this system based on an RDMA transport, and we study some performance gains that such a system would introduce. An integral component of an inference system is to account and track user flows,and distribute them across multiple worker nodes. Our third contribution aims to understand the challenges of Connection Tracking applications running at 100Gbps, in the context of a Stateful Load Balancer running on commodity hardware. / <p>QC 20240315</p>