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This thesis addresses basic scientific research in the field of transmitter front-end circuits for electro-optical data communication. First, the theoretical fundamentals are presented and analyzed. Based on the theoretical considerations, conceptual circuit designs are studied. Finally, in order to prove the described concepts, the circuits were experimentally characterized and subsequently compared to other works in the literature. The analysis covers key theoretical aspects regarding transmitter front-end circuits. It starts from the basic physical effects inside a transistor and ends with the design of high-swing modulator drivers. Furthermore, it comprises the fundamentals of optical modulators as well as the integration of the electrical driver with the modulator. First, the concept of a basic monolithically integrated transmitter consisting of a Mach-Zehnder modulator (MZM) and an electrical driver is presented. The circuit reaches a bit-error-free data rate of 37 Gb/s, which is a record among other monolithically integrated transmitters reported in the literature. It was shown that by employing a high-swing driver, high extinction ratios (ER) can be achieved (namely 8.4 dB at 25 Gb/s and 7.6 dB at 35 Gb/s) while using short-length phase shifters (2 mm of length). It was therefore proved that one of the main drawbacks of the MZM-based transmitters, namely their large chip area, can be mitigated by using high-swing drivers, however without sacrificing the ER. Next, an improved modulator driver design is investigated, the focus of the study being the linearity. In addition to a high peak-to-peak differential output voltage swing of 7.2 Vpp,d, the driver achieves record-low total harmonic distortion (THD) values of 1% (at 1 GHz, for the output swing of 6.5 Vpp,d) and 1.7% (at 1 GHz, for the output swing of 7 Vpp,d). Moreover, the driver reaches a bandwidth of 61.2 GHz and shows a high power efficiency when relating its DC power consumption to its output voltage swing. The achievement of a high linearity and bandwidth without an increased power consumption is due to the fact that the bias currents of the emitter-follower (EF) stages are provided by means of resistors instead of the conventional current sources. The two approaches were first analyzed mathematically and subsequently compared by means of circuit simulations. It was shown that the proposed approach for the realization of the EFs – i.e. by means of resistors – allows a reduction of the DC power consumption by 19% compared to the current-source approach for an equivalent performance in terms of linearity and bandwidth. Finally, a modulator driver concept suitable for higher-order modulation formats is studied, namely the 8-level pulse amplitude modulation (PAM-8). The circuit was realized as a 3-bit digital-to-analog converter (DAC), thus being able to yield 8-level output signals. Moreover, the circuit is able to function as a PAM-4 driver as well, thanks to the tunable tail currents of the DAC core. It achieves a symbol rate of 50 Gbaud, which corresponds to a bit rate of 150 Gb/s for the PAM-8 modulation and 100 Gb/s for PAM-4. The study showed that a modulator driver can be realized that is able to switch between different modulation formats (namely PAM-8 and PAM-4), without requiring extra power or additional circuit parts. Moreover, the use of on-chip single-to-differential converters (SDCs) targets the relaxation of the requirements on the stages that precede the driver. Finally, relating its DC power consumption (590 mW, including the SDCs) to its output voltage swing (4 Vpp,d), the driver shows one of the highest power efficiencies among PAM modulator drivers in the literature.

In this theses techniques for high-speed digital delta-sigma modulator(DDSM) structures are considered. Four techniques are applied andevaluated: unfolding, increasing the number of delay elements in theinner loop, pipelining/retiming, and optimizations provided by thesynthesis tool. Of interest is to see the speed-area-power trade-offs.For implementation, three different modulators meeting the samerequirements are implemented. Each modulator has a 16-bit input andresults in a 3-bit output. The baseline case is a second-ordermodulator, which has one delay element in its inner loop. Throughoptimization, two new structures are found: to provide two delayelements in the inner loop, a fourth-order modulator is required,while to provide three delay elements, a thirteenth-order modulator isobtained.The results show that in general it is better to unfold the modulatorthan to obtain the speed-up through optimizing the arithmeticoperators with the synthesis tool. Using correct pipelining/retimingis also crucial. Finally, for very high-speed implementation, usingthe structures with more delay elements is required. Also, in manycases these are more area and power efficient compared to usingoptimized arithmetic operators, despite their higher computationalcomplexity.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / A Phase Modulator combining digital techniques with non-traditional analog circuitry can minimize the shortcomings of a traditional (purely analog) Phase Modulator. These shortcomings are: nonlinear response from input modulating signal to output modulated signal; parameters (frequency and modulation index) that are difficult to set; and the need for complex filters. The design approach discussed in this paper uses a combination of Direct Digital Synthesis (DDS) and analog devices operating in their linear range to generate a Phase Modulated RF (140 MHz) signal. A Numerically Controlled Oscillator (NCO) digitally generates the first IF yielding a very accurate, repeatable and linear signal with easily adjustable parameters such as frequency and modulation index. Linear multipliers (instead of saturated diode mixers or step recovery diodes) are used for up-conversion to RF. Using linear multipliers eases the filtering requirements due to the significantly reduced harmonics and IM (Inter-Modulation) terms. The resulting RF signal is easily translated to higher frequency bands such as L, S, C, X or K.

International Telemetering Conference Proceedings / October 26-29, 1987 / Town and Country Hotel, San Diego, California / The three axis stabilized Indian Remote Sensing Satellite will image the earth from a 904 Km polar - sun synchronous orbit. The payload is a set of CCD cameras which collect data in four bands visible and near infra-red region. This payload data from two cameras, each at 10.4 megabits per sec is transmitted in a balanced QPSK in X Band. The payload data before transmission is formatted by adopting Major and Minor frame synchronizing codes. The formatted two streams of data are differentially encoded to take care of 4-phase ambiguity due to QPSK transmission. This paper describes the design and development aspects related to such a Data Handling System. It also highlights the environmental qualification tests that were carried out to meet the requirement of three years operational life of the satellite.

<p>Sigma-delta modulators (SDM) have come up as an attractive candidatefor analog-to-digital conversion in single chip front ends thanks to the continuousimproving performance. The major disadvantage is the limited bandwidthdue to the need of oversampling. Therefore, extending these convertersto broadband applications requires lowering the oversampling ratio (OSR) inorder. The aim of this thesis is the investigation on the topology and structureof sigma-delta modulators suitable for wideband applications, e.g. wireline orwireless communication system applications having a digital baseband aboutone to ten MHz.It has recently become very popular to feedforward the input signal inwideband sigma-delta modulators, so that the integrators only process quantizationerrors. The advantage being that the actual signal is not distorted byopamp and integrator nonlinearities. An improved feedforward 2-2 cascadedstructure is presented based on unity-gain signal transfer function (STF). Theimproved signal-to-noise-ratio (SNR) is obtained by optimizing zero placementof the noise transfer function (NTF) and adopting multi-bit quantizer.The proposed structure has low distortion across the entire input range.In high order single loop continuous-time (CT) sigma-delta modulator, excessloop delay may cause instability. Previous techniques in compensation ofinternal quantizer and feedback DAC delay are studied especially for the feedforwardstructure. Two alternative low power feedforward continuous-timesigma-delta modulators with excess loop delay compensation are proposed.Simulation based CT modulator synthesis from discrete time topologies isadopted to obtain the loop filter coefficients. Design examples are given toillustrate the proposed structure and synthesis methodology.Continuous time quadrature bandpass sigma-delta modulators (QBSDM)efficiently realize asymmetric noise-shaping due to its complex filtering embeddedin the loops. The effect of different feedback waveforms inside themodulator on the NTF of quadrature sigma-delta modulators is presented.An observation is made that a complex NTF can be realized by implementingthe loop as a cascade of complex integrators with a SCR feedback digital-toanalogconverter (DAC), which is desirable for its lower sensitivity to loopmismatch. The QBSDM design for different bandpass center frequencies relativeto the sampling frequency is illustrated.The last part of the thesis is devoted to the design of a wideband reconfigurablesigma-delta pipelined modulator, which consists of a 2-1-1 cascadedmodulator and a pipelined analog-to-digital convertor (ADC) as a multi-bitquantizer in the last stage. It is scalable for different bandwidth/resolutionapplication. The detail design is presented from system to circuit level. Theprototype chip is fabricated in TSMC 0.25um process and measured on thetest bench. The measurement results show that a SNR over 60dB is obtainedwith a sampling frequency of 70 MHz and an OSR of ten.</p>

This dissertation explores methods of reducing the oversampling ratio (OSR) of both delta-sigma modulators and incremental data converters. The first reduced-OSR architecture is the high-order cascaded delta-sigma modulator. These delta-sigma modulators are shown to reduce the in-band noise sufficiently at OSRs as low as 3 while providing power savings. The second low OSR architecture is the high-order cascaded incremental data converter which possesses signal-to-quantization noise ratio (SQNR) advantages over equivalent delta-sigma modulators at low OSRs. The final architecture is the time-interleaved incremental data converter where two designs are identified as potential methods of increasing the throughput of low OSR incremental data converters. A prototype chip is designed in 0.18um CMOS technology which can operate in three modes by simply changing the resetting clock phases. It can operate as an 8-stage pipeline analog-to-digital (A/D) converter, an 8th-order cascaded delta-sigma modulator, and an 8th-order cascaded incremental data converter with an OSR of 3.

The processing of amyloid precursor protein (APP) by - and -secretases produces amyloid (A) peptide, the principal component of the neuritic plaques found in Alzheimers disease (AD) pathology. The enzyme -secretase is a multimeric protein consisting of presenilins-1/2 (PS1/PS2), nicastrin, anterior pharynx defective 1 (APH-1) and presenilin enhancer-2 (PEN-2). Recently it was discovered that p23, a transmembrane protein involved in intracellular protein trafficking, negatively regulates -secretase activity. In the present study, I evaluated the levels/expression of the nicastrin and p23 and their possible colocalization with PS1 in normal adult and developing brains. Additionally, I have studied the alterations of p23 levels in both animal model of neurodegeneration and in postmortem AD brains. Nicastrin and p23 were widely distributed throughout the brain and colocalized in all brain regions with PS1. The levels of nicastrin and p23 were relatively high at the early stages of postnatal development and then declined gradually as age increased. Interestingly, p23 level/expression was found to be altered following kainic acid-induced neurodegeneration in the adult rat brain. Additionally, p23 levels were reduced in the brains of individuals with AD. These results, taken together, suggest that both nicastrin and p23 are expressed in neurons throughout the brain and their levels decline gradually during development to reach an adult profile. Additionally, my results indicate that a decreased level of p23 may contribute to AD pathogenesis by increasing the production of A-related peptides.

The main purpose of this thesis is to research High-Order Sigma-Delta Analog-to-Digital converter for precision measurement, a PI compensator and a third-order Sigma-Delta modulator has been proposed based on a second-order Sigma-Delta modulator. In accordance with the analysis result of frequency domain and time domain of system, we use third-order model because of better response with auxiliary software to simulate and implement the system, then measure modulator output variance for input variation. This converter circuit demonstrates that it can achieve the requirements of precision and linearity which the measure instrument demands.

For the fractional-N frequency synthesizers using delta-sigma modulation (DSM) techniques, higher PLL bandwidth is highly desirable in order to achieve faster settling time. As the PLL bandwidth is increased, more quantization noises pass through the PLL so that the output phase noise performance is degraded. There is a tradeoff between phase-noise performance and PLL bandwidth. To improve the problem, the thesis studies the quantization noise cancellation technique. With this technique, the PLL bandwidth can be increased without the cost of degrading phase-noise performance. With the help of Agilent EEsof¡¦s ADS, the phase-noise performance of the studied fractional-N frequency synthesizers can be predicted. For demonstration, this research implements a 2.6 GHz fractional-N frequency synthesizer hybrid module, and compares the measured phase noises with and without the technique under considering various combinations of MASH DSM orders and PLL bandwidth. Another demonstration of this thesis is to design a PLL IC using TSMC 0.18 £gm CMOS process, and make a discussion on the testing performance of the PLL IC.