The aim of this diploma thesis is a design of a new mental health center. The mental health center is a brand new low-treshold element in the system for people with mental ilness. The building is located in Prague, Hrdlořezy, district of the Capital City of Prague. The building is a detached house, it has three floors, and one partial underground level. On the first floor, there is an entrance hall, administrative facilities, a bed unit, a dining area and last but not least, space for group and individual therapies. On the second and third floor, there are again bed units, administrativ facilities, but also space for leisure activities. The basement of the building consists of the technical backround of the building together with storage space. The proposed building is made up of cubic masses forming a rectangular floor plan with large undercovered atrium penetrating the center of the entire building. The building is designed as a monolithic reinforced concrete skeleton [frame on a base slab]. The skeleton infill masonry is designed from clay blocks. The roofing of this building is designed with a flat green vegetation roof.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第21370号 / 工博第4529号 / 新制||工||1705(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 竹内 繁樹, 教授 雨宮 尚之, 准教授 掛谷 一弘 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Purpose: The purpose of this study was to evaluate the fracture strength of monolithic FDPs of multi-layered zirconia (YML) with different connector dimensions and placement in the disc. Material and method: Forty 3-unit monolithic anterior FDPs were produced, 212223, and divided in four groups (n=10) based on the different connector dimensions and strategies for placement in KATANATM Zirconia Yttria Multi-Layered (YML)-disc. The groups were as follows: EB12, produced with 12 mm  connector dimension and EB7, with 7 mm  connector dimension which were both placed in Enamel layer and Body layer 1 (flexural strength: 750 and 1000 MPa, respectively) in the disc, BB12, with 12 mm  connector dimension and BB7, produced with 7 mm  connector dimension both placed in Body layer 2 and 3 (both with 1100 MPa) in the disc. The specimens were artificially aged by 10 000 cycles in thermocycling. Then, one random specimen was selected from each group (4 in total) and cemented onto the model, subsequently loaded to fracture using a universal testing machine. The result was compiled and reported descriptively. Result: The FDP in group BB12 remained intact and fracturing only occurred in this model at 893 N. The FDP in group BB7 demonstrated the highest fracture strength (972 N), followed by EB12 (842 N) and EB7 which showed the lowest fracture strength (465 N). All these three FDPs broke mesially on the pontics. Conclusion: Within the limitations of this pilot study, the following conclusions can be drawn: the fracture strength of monolithic FDPs of multi-layered zirconia is affected by the connector dimension. Placement of FDPs with a small connector area should be avoided in the layers with lower strength. The choice of model material affects the result. / Syfte: Syftet med föreliggande pilotstudie var att undersöka brotthållfastheten påmonolitiska broar av flerskiktad zirkonia (YML) med olika konnektordimensioneroch placering i disken. Material och metod: Totalt framställdes 40 stycken 3-leds monolitiska anteriorabroar, 212223. Broarna delades in i 4 grupper (n=10) efter olikakonnektordimensionering och placering i KATANATM Zirconia YttriaMulti-Layered (YML)-disken. Grupperna var enligt följande: EB12 med 12 mm²konnektordimension och EB7 med 7 mm² konnektordimension där broarnaplacerades i både Enamel Layer och Body Layer 1 (med 750 respektive 1000 MPai böjhållfasthet) i disken. Broarna i grupperna BB12 med 12 mm²konnektordimension och BB7 med 7 mm² konnektordimension placerades i BodyLayer 2 och Body Layer 3 (med 1100 MPa böjhållfasthet för respektive lager) idisken. Broarna genomgick termocykling, 10 000 cykler. Därefter valdes fyrabroar slumpmässigt ut, en bro från varje grupp, och cementerades på modell.Slutligen genomfördes ett brotthållfasthetstest med en universaltestmaskin tillsfraktur uppstod. Resultatet sammanställdes och redovisades deskriptivt. Resultat: Bron i grupp BB12 förblev intakt och fraktur skedde enbart i modellen(893N). Bron i grupp BB7 visade högst brotthållfasthet: 972N, följt av bron igrupp EB12 som visade brotthållfasthet på 842N och bron i grupp EB7 påvisadeden lägsta brotthållfastheten: 465N. Dessa tre broar frakturerade mesialt på dethängande ledet. Slutsats: Inom ramen för föreliggande pilotstudies begränsningar kan följandeslutsatser dras: brotthållfastheten på monolitiska broar i flerskiktad zirkoniapåverkas av konnektordimensioneringen. Placering av broar med mindrekonnektorarea än rekommendationen ska undvikas i skikten med lägre hållfasthet.Valet av modellmaterial har betydelse och påverkar resultatet.

The purpose of this research is to investigate the use of compliant mechanisms in space applications and design, analyze, and test a compliant space mechanism. Current space mechanisms are already highly refined and it is unclear if significant improvements in performance can be made by continuing to refine current designs. Compliant mechanisms offer a promising opportunity to change the fundamental approach to achieving controlled motion in space systems and have potential for dramatic increases in mechanism performance given the constraints of the space environment. A compliant deployment hinge was selected for development after industry input was gathered. Concepts for large-displacement compliant hinges are investigated. A design process was developed that links the performance requirements of deployment to the design parameters of a deployment hinge. A large-displacement monolithic compliant rotational hinge, the Flex-16, is designed, analyzed, and tested. It was developed for possible application as a spacecraft deployment hinge and designs were developed using three different materials (polypropylene, titanium, and carbon nanotubes) and manufacturing processes (CNC milling, electron beam manufacturing metal rapid prototyping, and a carbon nanotube framework) on two size scales (macro and micro). A parametric finite element model allowed for prediction of prototype behavior before fabrication. The Flex-16 hinge is capable of 90 degrees of deflection without failure or contact and can be designed to meet industry requirements for space.

Robotics and space applications represent areas where compliant mechanisms can continue to make a significant impact by reducing costs and weight while improving performance. Because of the nature of these applications, a common need is for bearing replacement mechanisms, or mechanisms that perform the function of a bearing without the complexity and failure modes associated with bearings. Static balancing is a design strategy that attempts to reduce the actuation effort of a mechanism, and has been applied to compliant mechanisms in some applications. Monolithic construction, especially by means of 3D printing technology, is a strategy whereby the mechanism links and joints are built as a single "chunk" of material. This eliminates assembly and failure modes associated with wear and friction in traditional joints. In this work we examine these design strategies in the context of robotics and space applications. Matlab and Ansys batch files can be found in Appendix A. A fully compliant zero-torque, statically balanced mechanism is described that can undergo greater than 100 of motion. Because compliant mechanisms achieve their motion from the deflection of their constituent members, there is some strain energy associated with actuated positions. By introducing an appropriate pre-load, strain energy can be held constant. This can reduce or nearly eliminate the input force required from the actuating device. This paper describes the statically balanced rotary joint concept, and demonstrates its optimization, testing, and implementation for a haptic pantograph mechanism. The statically balanced properties of the constituent joints result in a mechanism with two balanced degrees of freedom. Matlab and Ansys batch files can be found in Appendix B. The conception, modeling, and development of a fully compliant two-degree-of-freedom pointing mechanism for application in spacecraft thruster, antenna, or solar array systems is described. The design objectives and the advantages of a compliant solution are briefly discussed. A single design concept is selected for final development from a field of generated concepts. Analytical and numerical models are accompanied by prototype testing and measurements in several iterations. A final design is described in detail, a fully compliant prototype is fabricated in titanium, and its performance is measured.

Origami-inspired design is an emerging field capable of producing compact and efficient designs. The object of a surrogate fold is to provide a fold-like motion in a non-paper material without undergoing yielding. Compliant mechanisms provide a means to achieve these objectives as large deflections are achieved. The purpose of this thesis is to present a summary of existing compliant joints suitable for use as surrogate folds. In doing so, motions are characterized which no existing compliant joint provides. A series of compliant joints is proposed which provides many of these motions. The possibility of patterning compliant joints to form an array is discussed. Arrays capable of producing interesting motions are noted.

The project discuss mass and monomateriality through residential case studies of modular masonry.

Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level. Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC's pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products. Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to ± 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR. Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology. ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices' performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range.

Deep neural networks (DNNs) are extensively used for inference in a wide range of emerging mobile and edge application domains, including autonomous vehicles, drones, augmented and virtual reality (AR/VR), etc. Due to the increasing popularity of these applications, there has been an increasing demand for mobile/edge DNN accelerators to achieve low inference latency and high efficiency. Furthermore, these mobile/edge applications also need to execute multi-DNN workloads, where multiple independent DNNs execute subtasks to complete one large task. This thesis aims to optimize the efficiency of systolic arrays for DNN acceleration because they are among the most popular architectures for DNN inference in mobile/edge systems due to their straightforward design and dataflow. Systolic arrays provide several degrees of freedom to co-optimize performance, power, area, and temperature–namely, die/chiplet architecture (number of processing elements, on-chip memory capacity and its architecture), quantity, placement, and dataflow. While recent works have focused on 2D DNN systolic arrays, 2D scaling has been saturating and, thus, improving the performance and power characteristics of computing systems is becoming increasingly challenging. To overcome traditional scaling bottlenecks, 3D integration has emerged as a promising integration technology. 3D technology provides several benefits over 2D systems such as high integration density, high bandwidth, high energy efficiency, and footprint savings. This thesis focuses on two 3D integration technologies: (i) die-stacked 3D (TSV3D), and (ii) monolithic 3D (MONO3D). Both of these 3D technologies provide significant performance and power benefits over 2D systems and thus, are potent technologies for energy efficient design of systolic arrays for DNNs. However, the dense integration in 3D causes high power densities and inter-tier thermal coupling, further escalating thermal issues and resulting in hot spots across tiers. Furthermore, mobile/edge devices have tight area, power, and thermal constraints due to the absence of heat sinks and fans. Thus, temperature is a critical design concern in 3D DNN accelerators for mobile/edge devices. This thesis states that to glean the benefits of 3D technology in mobile/edge devices to improve energy efficiency and satisfy performance and power constraints, it is imperative to design thermally-aware 3D systolic arrays for DNNs. To realize this statement, this thesis makes the following contributions: (i) it designs a thermally-aware optimization flow to select a near-optimal MONO3D DNN systolic array for a given DNN and an optimization goal under a performance constraint. The optimizer is facilitated by circuit and architecture-level cross-layer performance/power models that are developed as part of this thesis. (ii) It introduces thermal awareness in tuning a given TSV3D systolic array chiplet architecture and the chiplet’s placement in a multi-chip module (MCM) executing a multi-DNN workload to balance both cost and power of the MCM, while satisfying latency, area, power, thermal packaging, and workload constraints. (iii) It optimizes a dataflow implementation by utilizing the massive bandwidth available in MONO3D systolic arrays with a dense on-chip resistive RAM to improve energy efficiency while satisfying the thermal and performance constraints. Results demonstrate 81% improvement in inference per second per watt over 2D systolic arrays due to high-density and high-bandwidth resistive RAM interface using monolithic inter-tier vias (MIVs). We also demonstrate up to 44% MCM cost savings and 63% DRAM power savings over temperature-unaware optimization at iso-frequency and iso-MCM area for TSV3D MCMs. In addition, we show that optimization without thermal awareness leads to over-estimation of efficiency gains and thermal violations in both MONO3D and TSV3D systolic arrays. / 2025-01-16T00:00:00Z

В настоящее время Китай еще не достиг наивысшего уровня развития сборно-монолитных зданий, обладающих высоким уровнем сборности. Поэтому исследования сборно-монолитного строительства актуальны. В работе представлен вариант совершенствования оценки сборно-монолитных зданий на примере китайского гражданского строительства. Кратко рассмотрена история развития сборно-монолитных зданий в Китае и других странах. Разработан алгоритм оценки сборно-монолитного здания, представлен пример практического применения методики и алгоритма. / At present, China has not yet reached the highest level of development of prefabricated monolithic buildings with a high level of prefabrication. Therefore, research into prefabricated monolithic construction is relevant. The paper presents an option for improving the assessment of prefabricated monolithic buildings using the example of Chinese civil engineering. The history of the development of prefabricated monolithic buildings in China and other countries is briefly reviewed. An algorithm for assessing a prefabricated monolithic building has been developed, and an example of the practical application of the methodology and algorithm is presented.