La réduction des dimensions des dispositifs MOSFET devient de plus en plus complexe a réalisé, et les nouvelles technologies MOSFET se confrontent à de fortes difficultés. Pour surmonter ce problème, une nouvelle technique, appelée intégration 3D VLSI, est étudiée : remplacer la structure plane conventionnelle par un empilement vertical de transistors.En particulier, l’intégration 3D séquentielle ou CoolCube™ au CEA-Leti permet de profiter pleinement de la troisième dimension en fabriquant séquentiellement les transistors. La réalisation d’une telle intégration apporte une nouvelle contrainte, celle de fabriquer le transistor du dessus avec un budget thermique faible (inférieur à 500°C), afin de préserver les performances du transistor d'en dessous. Puisque ce budget thermique est principalement influencé par l'activation des dopants, plusieurs techniques innovatrices sont actuellement investiguées au CEA-LETI, afin de fabriquer le drain et la source. Dans ce manuscrit, nous utiliserons la recristallisation en phase solide comme mécanisme pour activer les dopants (inférieures à 600 °C). L’objectif de cette thèse est donc de fabriquer et de caractériser des transistors dont l’activation des dopants est réalisée grâce à ce mécanisme, afin d’atteindre des performances similaires à des transistors réalisés avec un budget thermique standard. Ce travail est organisé autour de l’activation des dopants, et en trois chapitres, où chaque chapitre est spécifique à une intégration (« Extension Last »/ « Extension First », « Gate Last »/ « Gate First ») et à une architecture (FDSOI, FINFET) considérées. Ces chapitre permettront, grâce aux caractérisations électriques, morphologiques et aux simulations, de développer un procédé de recristallisation stable à 500°C, à la fois pour les nMOS et les pMOS, et de proposer de nouveaux schémas d’intégrations, afin de réaliser des transistors à faible budget thermique et compatibles avec l’intégration 3D Séquentielle. / The down scaling of MOSFET device is becoming harder and the development of future generation of MOSFET technology is facing some strong difficulties. To overcome this issue, the vertical stacking of MOSFET in replacement of the conventional planar structure is currently investigated. This technique, called 3D VLSI integration, attracts a lot of attention, in research and in the industry. Indeed, this sequential stacking of transistor enables to gain in density and performance without reducing transistors dimensions.More specifically, 3D sequential integration or CoolCube™ at CEA-Leti enables to fully benefit of the third dimension by sequentially manufacturing transistors. Implementing such an integration provides the new constraint of manufacturing top transistor with low thermal budget (below 500°C) in order to preserve bottom-transistor performances. As most of the thermal budget is due to the dopant activation, several innovative techniques are currently investigated at CEA-LETI.In this work, solid phase epitaxy regrowth will be used as the mechanism to activate dopants below 600°C. The aim of this thesis is thus to manufacture and to characterize transistors with low-temperature dopant activation, in order to reach the same performance as devices manufactured with standard thermal budget. The work is organized around the dopant activation, and in three chapters, according to each considered integration scheme (Extension Last/ Extension First, Gate Last/ Gate First) and architecture (FDSOI, FINFET). These chapters, assisted by relevant simulations, electrical and morphological characterizations, will enable to develop a new and stable 500°C recrystallization process for both N and P FETs, and to propose new integration schemes in order to manufacture transistors with low thermal budget and compatible with the 3D sequential integration.

No description available.

Ce mémoire présente des résultats de caractérisation en transport électrique d’une double boîte quantique latérale en silicium de type MOSFET (transistor à effet de champ métal-oxyde-semi- conducteur). La double boîte permet d’isoler des électrons dans les trois dimensions, tout d’abord en formant un gaz bidimensionnel de porteurs de charge près de la surface du substrat sous l’effet d’une grille d’accumulation, puis en déplétant certaines régions du gaz d’électrons avec des grilles de déplétion en polysilicium. Le dispositif a été fabriqué aux Sandia National Laboratories par l’équipe de Malcolm S. Carroll. Les mesures en transport électrique suggèrent l’atteinte du régime à un seul électron à une température relativement élevée de 1.5 K. En effet, des mesures de diamants de Coulomb montrent un diamant associé à la région à zéro électron qui ne se referme pas pour des biais source-drain supérieurs à 30 meV. Il s’agit d’une forte indication que les boîtes quantiques ont bien été vidées, bien que le nombre exact d’électrons n’ait pas pu être confirmé directement par détection de charge. Le diagramme de stabilité obtenu à une température de 8 mK indique la formation d’une double boîte quantique lithographique très stable. Enfin, l’étude des triangles de conduction à fort biais source-drain dans les polarités positive et négative permet d’observer le phénomène du blocage de spin sous l’application d’un champ magnétique parallèle de 450 mT. Une séparation singulet-triplet de ~ 400 μeV en est extraite, indiquant possiblement une levée importante de la dégénérescence de vallée associée au silicium. Les résultats présentés dans ce mémoire constituent l’une des premières observations de l’isolation d’un seul électron dans une double boîte quantique en silicium de type MOSFET. Il s’agit aussi de la première observation du blocage de spin en transport dans ces dispositifs. Ces observations font partie des étapes initiales à réaliser pour obtenir des qubits de spin performants dans le silicium, un matériau pour lequel des longs temps de cohérence sont anticipés.

No description available.

Fabrication and characterization of a new kind of pressure sensor using self-assembly Zinc Oxide (ZnO) nanowires on top of the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Self-assembly ZnO nanowires were fabricated with a diameter of 80 nm and 800 nm height (80:8 aspect ratio) on top of the gate of the MOSFET. The sensor showed a 110% response in the drain current due to pressure, even with the expected piezoresistive response of the silicon device removed from the measurement. The pressure sensor was fabricated through low temperature bottom up ultrahigh aspect ratio ZnO nanowire growth using anodic alumina oxide (AAO) templates. The pressure sensor has two main components: MOSFET and ZnO nanowires. Silicon Dioxide growth, photolithography, dopant diffusion, and aluminum metallization were used to fabricate a basic MOSFET. In the other hand, a combination of aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and wet etching for nanowire release were optimized to fabricate the sensor on a silicon wafer. The ZnO nanowire fabrication sequence presented is at low temperature making it compatible with CMOS technology.

Este trabalho tem como objetivo o estudo, caracterização elétrica e modelagem do novo transistor desenvolvido e fabricado no Laboratório de Sistemas Integráveis (LSI) da Universidade de São Paulo (USP) chamado BE (Back Enhanced) SOI MOSFET. Trata-se de um dispositivo inovador que se destaca principalmente pela sua facilidade de fabricação (exigindo apenas processos bem conhecidos e nenhuma etapa de dopagem do semicondutor) e sua flexibilidade quanto ao modo de operação (pode atuar como um transistor MOS tipo n ou um transistor MOS tipo p, dependendo somente da polarização de substrato). Aplicando-se tensão no substrato (VGB) é possível formar um canal de elétrons (VGB>0) ou lacunas (VGB<0) na segunda interface da camada de silício, por onde a corrente entre fonte e dreno flui. Sua patente foi requerida junto ao INPI (Instituto Nacional da Propriedade Industrial) sob o número BR 10 2015 020974 6. Foram realizadas medidas elétricas e simulações numéricas para melhor compreender seu princípio de funcionamento e as características que tornam possível sua reconfigurabilidade. Duas fabricações distintas deste tipo de dispositivo foram analisadas. Além das espessuras distintas, a principal diferença entre elas é o metal utilizado nos eletrodos de fonte e dreno, sendo alumínio na primeira e níquel na segunda versão. O alumínio utilizado na primeira versão resultou em contatos Ôhmicos após o processamento térmico das lâminas, que favoreceram o funcionamento do dispositivo como transistor tipo p, devido à natureza do material utilizado. A análise em função da temperatura (de 25ºC até 125ºC) mostrou uma variação da tensão de limiar (até 1,52mV/ºC) e uma degradação da mobilidade dos portadores de carga (analisado através da transcondutância), resultando no surgimento de um ponto invariante com a temperatura, o chamado ZTC (Zero Temperature Coefficient). Já a segunda versão possui contatos Schottky, na qual foram obtidos níveis de corrente apreciáveis tanto para transistores tipo n (na ordem de nA para as condições de polarização utilizadas), quanto para transistores tipo p (na ordem de ?A). O comportamento da curva de corrente de dreno deste dispositivo apresentou uma estabilização a partir de determinado valor de tensão de porta. A partir deste ponto o BE SOI MOSFET deixa de atuar como um transistor convencional e passa a ter sua corrente de dreno proporcional a tensão de substrato. Medidas em função da temperatura nesta segunda versão permitiram comparar os resultados com os da primeira versão. Percebeu-se a ausência do ponto de ZTC, uma vez que foi observado o aumento da corrente devido à diminuição da resistência dos contatos de fonte e dreno para temperaturas mais elevadas. Por fim, a operação de um circuito inversor utilizando o BE SOI MOSFET foi implementada, mesmo quando alternando os tipos dos transistores, comprovando a flexibilidade de funcionamento dos transistores ao mudar seu tipo em função da polarização de substrato. / The aim of this work is the study, the electrical characterization and the modeling of the new transistor that was developed and fabricated in the Laboratório de Sistemas Integráveis (LSI) at University of Sao Paulo (USP). It was named BE (Back Enhanced) SOI MOSFET. This innovative device has the advantage of a simple fabrication (only well-known processes are required to build it and there is no need of any doping step) and it has a reconfigurable operation (it can act as a n-type MOS transistor or as a ptype MOS transistor depending only on substrate bias). The substrate voltage (VGB) is responsible for the formation of an electron (VGB>0) or a hole (VGB<0) channel at the back interface of the silicon, where the drain current flows. The patent for it was required at the National Industrial Property Institute under the number BR 10 2015 020974 6. Electrical measurements and numerical simulations were performed to better understand its functioning principle and the characteristics that enable its reconfigurability. Two different fabrication splits were analyzed. Beside their thicknesses, the main difference between them is the drain and source metal electrode (aluminum in the first split and nickel in the second one). The one with aluminum electrodes resulted in Ohmic contacts after thermal processing, that favored the formation on the p-type transistor because of the nature of the used element. It was observed a variation of the threshold voltage (up to 1.52mV/ºC) and a mobility degradation (seen through the transconductance behavior) as a function of the temperature (from 25ºC to 125ºC), resulting in a zero-temperature coefficient (ZTC) bias point in this device. In this bias condition point, the drain current is almost constant as a function of the temperature, which is a good characteristic especially for analog circuits. The second split has Schottky drain and source contacts, in which appreciable current levels were obtained for both n-type transistors (order of magnitude of nA in the measured bias conditions) and p-type transistors (order of magnitude of ?A). The drain current of this device showed a particular behavior where the drain current stabilizes from a certain gate voltage. In this condition, the BE SOI MOSFET does not act as a conventional transistor anymore and its current is proportional to the substrate bias. Measurements as a function of the temperature were performed in the device too. It was observed an increase of the drain current, differently from the first split, due to the reduction of the source and drain contacts resistances as a function of the temperature. This resulted in the absence of the ZTC point. Finally, the operation of an inverter circuit using BE SOI MOSFET transistors was implemented, even if the type of the transistors were switched. This result shows the flexibility of operation of the transistor, in other words, it is possible to change its type as a function of the substrate bias.

Este trabalho tem como objetivo o estudo, caracterização elétrica e modelagem do novo transistor desenvolvido e fabricado no Laboratório de Sistemas Integráveis (LSI) da Universidade de São Paulo (USP) chamado BE (Back Enhanced) SOI MOSFET. Trata-se de um dispositivo inovador que se destaca principalmente pela sua facilidade de fabricação (exigindo apenas processos bem conhecidos e nenhuma etapa de dopagem do semicondutor) e sua flexibilidade quanto ao modo de operação (pode atuar como um transistor MOS tipo n ou um transistor MOS tipo p, dependendo somente da polarização de substrato). Aplicando-se tensão no substrato (VGB) é possível formar um canal de elétrons (VGB>0) ou lacunas (VGB<0) na segunda interface da camada de silício, por onde a corrente entre fonte e dreno flui. Sua patente foi requerida junto ao INPI (Instituto Nacional da Propriedade Industrial) sob o número BR 10 2015 020974 6. Foram realizadas medidas elétricas e simulações numéricas para melhor compreender seu princípio de funcionamento e as características que tornam possível sua reconfigurabilidade. Duas fabricações distintas deste tipo de dispositivo foram analisadas. Além das espessuras distintas, a principal diferença entre elas é o metal utilizado nos eletrodos de fonte e dreno, sendo alumínio na primeira e níquel na segunda versão. O alumínio utilizado na primeira versão resultou em contatos Ôhmicos após o processamento térmico das lâminas, que favoreceram o funcionamento do dispositivo como transistor tipo p, devido à natureza do material utilizado. A análise em função da temperatura (de 25ºC até 125ºC) mostrou uma variação da tensão de limiar (até 1,52mV/ºC) e uma degradação da mobilidade dos portadores de carga (analisado através da transcondutância), resultando no surgimento de um ponto invariante com a temperatura, o chamado ZTC (Zero Temperature Coefficient). Já a segunda versão possui contatos Schottky, na qual foram obtidos níveis de corrente apreciáveis tanto para transistores tipo n (na ordem de nA para as condições de polarização utilizadas), quanto para transistores tipo p (na ordem de ?A). O comportamento da curva de corrente de dreno deste dispositivo apresentou uma estabilização a partir de determinado valor de tensão de porta. A partir deste ponto o BE SOI MOSFET deixa de atuar como um transistor convencional e passa a ter sua corrente de dreno proporcional a tensão de substrato. Medidas em função da temperatura nesta segunda versão permitiram comparar os resultados com os da primeira versão. Percebeu-se a ausência do ponto de ZTC, uma vez que foi observado o aumento da corrente devido à diminuição da resistência dos contatos de fonte e dreno para temperaturas mais elevadas. Por fim, a operação de um circuito inversor utilizando o BE SOI MOSFET foi implementada, mesmo quando alternando os tipos dos transistores, comprovando a flexibilidade de funcionamento dos transistores ao mudar seu tipo em função da polarização de substrato. / The aim of this work is the study, the electrical characterization and the modeling of the new transistor that was developed and fabricated in the Laboratório de Sistemas Integráveis (LSI) at University of Sao Paulo (USP). It was named BE (Back Enhanced) SOI MOSFET. This innovative device has the advantage of a simple fabrication (only well-known processes are required to build it and there is no need of any doping step) and it has a reconfigurable operation (it can act as a n-type MOS transistor or as a ptype MOS transistor depending only on substrate bias). The substrate voltage (VGB) is responsible for the formation of an electron (VGB>0) or a hole (VGB<0) channel at the back interface of the silicon, where the drain current flows. The patent for it was required at the National Industrial Property Institute under the number BR 10 2015 020974 6. Electrical measurements and numerical simulations were performed to better understand its functioning principle and the characteristics that enable its reconfigurability. Two different fabrication splits were analyzed. Beside their thicknesses, the main difference between them is the drain and source metal electrode (aluminum in the first split and nickel in the second one). The one with aluminum electrodes resulted in Ohmic contacts after thermal processing, that favored the formation on the p-type transistor because of the nature of the used element. It was observed a variation of the threshold voltage (up to 1.52mV/ºC) and a mobility degradation (seen through the transconductance behavior) as a function of the temperature (from 25ºC to 125ºC), resulting in a zero-temperature coefficient (ZTC) bias point in this device. In this bias condition point, the drain current is almost constant as a function of the temperature, which is a good characteristic especially for analog circuits. The second split has Schottky drain and source contacts, in which appreciable current levels were obtained for both n-type transistors (order of magnitude of nA in the measured bias conditions) and p-type transistors (order of magnitude of ?A). The drain current of this device showed a particular behavior where the drain current stabilizes from a certain gate voltage. In this condition, the BE SOI MOSFET does not act as a conventional transistor anymore and its current is proportional to the substrate bias. Measurements as a function of the temperature were performed in the device too. It was observed an increase of the drain current, differently from the first split, due to the reduction of the source and drain contacts resistances as a function of the temperature. This resulted in the absence of the ZTC point. Finally, the operation of an inverter circuit using BE SOI MOSFET transistors was implemented, even if the type of the transistors were switched. This result shows the flexibility of operation of the transistor, in other words, it is possible to change its type as a function of the substrate bias.

This thesis describes experimental work performed (1998-2001) during the author's involvement with the Brachytherapy group at the Peter MacCallum Cancer Centre (PMCC), where he was employed by its Department of Physical Sciences and subsequent modeling and analytical studies. When PMCC added HDR brachytherapy to its radiation therapy practice, an existing operating suite was considered the ideal location for such procedures to be carried out. The integration of brachytherapy into the theatre environment was considered logical due to the relatively invasive nature of brachytherapy techniques and the availability of medical equipment. This thesis contains the detailed study of three key Research Questions involved in clinical aspects relating to quality assurance of an HDR brachytherapy practice. An investigative chapter is dedicated to the pursuit of each of the Research Questions. The first question asked… Is the novel approach to using modular shielding combined with time and distance constraints adequately optimized during HDR brachytherapy? In order to establish optimal clinical practices, this project evaluates the effectiveness of additional shielding added to the modular shielding system without modification of the previously determined time and distance constraints for PMCC staff, other patients, and member of the public. The DOSXYZnrc user code for the EGSnrc Monte Carlo radiation transport code has been used to model exposure pathways to strategic locations used for measurement in and around the operating theatre suite. Modeling allowed exposure pathways to various areas with the facility to be tested without the need to use real sources. The second Research Question asked… How well is dose anisotropy characterized in the near field range of the clinic's HDR 192Ir source? This study experimentally investigated the anisotropy of dose around a 192Ir HDR source in a water phantom using MOSFETs as relative dosimeters. In addition, modeling using the DOSRZnrc user code for the EGSnrc Monte Carlo radiation transport code was performed to provide a complete dose distribution consistent with the MOSFET measurements. Measurements performed for radial distances from 5 to 30 mm extend the range of measurements to 5 mm which has not been previously reported for this source construction. The third Research Question is aimed at the patient level. Is the dose delivered to in vivo dosimeters, located within critical anatomical structures near the prostate, within acceptable clinical tolerance for a large group of HDR prostate patients? An in vivo dosimetry technique employing TLDs to experimentally measure doses delivered to the urethra and rectum during HDR prostate brachytherapy was investigated. Urethral and rectal in vivo measurements for 56 patients have been performed in the initial fraction of four-fraction brachytherapy boost. In the absence of comparable in vivo data, the following local corrective action level was initially proposed: more than 50% of the prostatic urethra receiving a dose 10% beyond the urethral tolerance. The level for investigative action is considered from the analyses of dose differences between measured data and TPS calculation.

L'électronique de puissance prend une place croissante dans le domaine automobile, avec notamment l'apparition de systèmes de motorisation mixte thermique-électrique (véhicules hybrides). Dans cette optique, les outils de conception des convertisseurs basse tension doivent être suffisamment précis pour réduire les phases de prototypage, mais également pour analyser la robustesse d'un convertisseur face aux inévitables dispersions d'une fabrication en grande série.<br>Dans la première partie, nous proposons un modèle de MOSFET valide dans les différentes phases de fonctionnement rencontrées dans un onduleur (commutation du transistor, de sa diode interne, et fonctionnement en avalanche notamment). La nécessité de modélisation du câblage est ensuite démontrée, puis nous présentons la méthode de modélisation, reposant sur l'utilisation du logiciel InCa. <br>La seconde partie de cette thèse, qui repose principalement sur une démarche expérimentale, permet d'identifier les paramètres du modèle de MOSFET puis de valider la modélisation complète du convertisseur vis-à-vis de mesures. Pour cela, nous avons choisi un critère de comparaison très sensible aux erreurs de modélisation : le niveau de pertes du convertisseur. La mesure de ces pertes est effectuée par calorimétrie. <br>Nous en concluons que la modélisation proposée atteint une précision satisfaisante pour pouvoir être exploitée dans une démarche de conception, ce qui fait l'objet de la dernière partie de cette thèse. La simulation est alors utilisée pour étudier l'influence du câblage et de la commande sur les pertes d'un bras d'onduleur, puis pour étudier la répartition du courant entre transistors d'un assemblage en parallèle en tenant compte de leurs dispersions de caractéristiques. Une telle étude ne pourrait que très difficilement être effectuée de façon expérimentale (elle nécessiterait la modification du circuit pour insérer les instruments de mesure), ce qui montre l'intérêt de la conception assistée par ordinateur en tant qu'outil d'analyse.

La méthode de dépôt séquentiel par voie humide est une méthode adéquate pour obtenir des films denses et de bonne qualité aussi bien pour des applications aux diélectriques que pour des composés hybrides. En utilisant un automate programmable dans une atmosphère contrôlée d'azote, un échantillon de silicium est alternativement trempé dans des solutions diluées d'alkoxydes, d'acide phosphorique et d'eau (hydrolyse). Chaque séquence est suivie d'un rinçage à l'éthanol afin de greffer seulement une monocouche et dans de l'eau afin d'activer le substrat pour le cycle suivant. Un meilleur control de la densité des films par rapport au dépôt sol-gel classique est obtenue en travaillant avec des solutions très diluées (< 10-3 mol / L) et des vitesses de retrait lentes ! (< 2 cm/min). Des films de phosphate de titane (ou zirconium) bidimensionnels, des dépôts alternés de couches d'oxydes (ZrO2)n et des couches de phosphate de lanthane dopées par de l'europium (Eu3+) ont été élaborés sur du silicium grâce à cette méthode.