Este trabalho apresenta um estudo da influência do crescimento epitaxial seletivo (SEG) em dispositivos tensionados mecanicamente (strain) em transistores SOI MuGFET de porta tripla. Com a evolução da tecnologia de integração de transistores, alguns efeitos parasitários são eliminados ou diminuídos, porém outros novos surgem. A tecnologia SOI MuGFETs disponibiliza dispositivos de múltiplas portas, tridimensionais. Nesses dispositivos, há um aumento da resistência de contato dos terminais devido ao estreitamento da região de canal, tornando esta resistência significativa em relação à resistência total. A utilização do Crescimento Epitaxial Seletivo (SEG) é uma das opções para diminuir a resistência total, elevando a região de fonte e dreno, causando o aumento da área de contato, diminuindo essa resistência parasitária. Em contrapartida, a utilização dos canais tensionados Uniaxiais, por filme de Si3N4, pela técnica de CESL, que é uma opção de melhora da transcondutância, mas em conjunto com o SEG afasta essa a camada de nitreto, tornando em determinada altura prejudicial ao invés de benéfico. Este trabalho foi realizado baseado em resultados experimentais e em simulações numéricas, mecânicas e elétricas de dispositivos, variando as tecnologias de tensionamento mecânico nos dispositivos com e sem SEG. Variou-se a altura do SEG em simulações, possibilitando extrapolar e obter resultados que de forma experimental não foram possíveis, permitindo um entendimento físico do fenômeno estudado. O resultados obtidos das diferentes tecnologias com e sem o uso de SEG mostraram que, em transistores SOI MuGFETs de porta tripla, o crescimento seletivo epitaxial nos dispositivos com tensão uniaxial piora a transcondutância máxima para dispositivos abaixo de 200nm de comprimento de canal, mas em contra partida torna mais prolongado o efeito pelos dispositivos acima dessa dimensão, como pode ser comprovado nos resultados obtidos. / This paper presents the study of the influence of selective epitaxial growth (SEG) devices mechanically strained (strain) in SOI transistors MuGFET triple gate. With the evolution of integration technology of transistors, some parasitic effects are eliminated or reduced, but new ones arise. MuGFETs SOI technology, devices are multiple ports, three-dimensional, these devices there is an increase in contact resistance of terminals due to the narrowing of the channel region, making considered in relation to total resistance. Use of Selective Epitaxial Growth (SEG) is one of the options to reduce the total resistance, raising the source and drain region, causing increased contact area by reducing the parasitic resistance. In contrast, the use of uniaxial strained channel by a film of Si3N4 by CESL technique is an option for improvement in transconductance, but in conjunction with the SEG away this layer of nitride, making it at some point or detrimental rather than beneficial. This study was based on experimental results and numerical simulations, mechanical and electrical devices of varying technologies in mechanical tensioning devices with and without FES, the height was varied in simulations of the FES, allowing extrapolate and obtain results that way trial was not possible, allowing a physical understanding of the phenomenon. The results of the different technologies with and without the use of FES showed that in SOI transistors MuGFETs triple gate, the selective epitaxial growth in uniaxial strained devices tends to worsen the maximum transconductance for devices below 200nm channel length, but against departure becomes more unrelenting effect on the devices above this size. As can be evidenced in the results obtained.

Neste trabalho é desenvolvido de forma inédita no Brasil um processo simples de fabricação de transistores FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) com porta de silício policristalino, para servir como base para futuros desenvolvimentos e, também, com finalidade de educação em microeletrônica. É proposta uma sequência de etapas de fabricação necessárias para a obtenção do dispositivo FD SOI nMOSFET, usando apenas 3 etapas de fotogravação e usando o óxido enterrado, intrínseco à tecnologia SOI, como região de campo, objetivando a obtenção do processo mais simples possível e eficiente. São apresentados os procedimentos detalhados de todas as etapas de fabricação executadas. Para obtenção da tensão de limiar de 1V foram fabricadas amostras com 2 doses diferentes de implantação iônica, 1,0x1013cm-2 e 1,2x1013cm-2. Estas doses resultaram em tensões de limiar (VTH) de 0,72V e 1,08V; respectivamente. Como esperado, a mobilidade independente de campo (0) é maior na amostra com dose menor, sendo de 620cm²/Vs e, para a dose maior, 460cm²/Vs. A inclinação de sublimiar é calculada através da obtenção experimental do fator de acoplamento capacitivo () 0,22; para as duas doses, e resulta em 73mV/déc. O ganho intrínseco de tensão (AV) mostrou-se maior na amostra com maior dose em função da menor condutância de saída, sendo 28dB contra 26dB para a dose menor, no transistor com L=40m e W=12m. Desta forma foi possível implementar uma sequência simples de fabricação de transistores SOI, com resultados elétricos relevantes e com apenas 3 etapas de fotogravação, fato importante para viabilizar seu uso em formação de recursos humanos para microeletrônica. / In this work is developed in an unprecedented way in Brazil a simple process of manufacturing transistors FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) with gate polysilicon, to serve as the basis for future developments and also with the purpose of education in microelectronics. A sequence of manufacturing steps necessary for obtaining FD SOI nMOSFET device is proposed, using only three photolithographic steps and using the buried oxide, intrinsic to SOI technology such as field region, aiming to get the simplest possible and efficient process. All the detailed manufacturing steps performed procedures are presented. To obtain the threshold voltage of 1V samples with 2 different doses of ion implantation (1.0x1013cm-2 and 1.2 x1013cm-2) were fabricated. These doses resulted in threshold voltages (VTH) of 0.72 V and 1.08 V, respectively. As expected, mobility independent of field (0) is higher in the sample with the lowest dose, 620cm²/Vs, and for the higher dose, 460cm²/Vs. The subthreshold slope is calculated by obtaining experimental capacitive coupling factor () 0.22, for both doses and results in 73mV/déc. The intrinsic voltage gain (AV) was higher in the sample with a higher dose due to lower output conductance, 28dB against 26dB to the lowest dose, to the transistor with L = W = 40m and 12m. This made it possible to implement a simple sequence of manufacturing SOI transistors with relevant electrical results and with only 3 steps photolithographic important fact to enable their use in training human resources for microelectronics.

Este trabalho apresenta o estudo do efeito de Auto-Aquecimento (Self-Heating SH) em transistores Silicon-On-Insulator (SOI) com estrutura de canal gradual (GC SOI MOSFET). São apresentadas as características da tecnologia SOI e em especial as características do transistor GC-SOI MOSFET. Foi realizada uma análise do SH usando uma comparação de dispositivos SOI convencionais com GC SOI nMOSFET. Esta análise compara dispositivos com o mesmo comprimento de máscara do canal e dispositivos com o mesmo comprimento efetivo de canal. Simulações numéricas bidimensionais foram efetuadas nas duas análises considerando o aquecimento da rede cristalina. Os modelos e a constante térmica usados nestas simulações também foram apresentados. É demonstrado que os dispositivos GC com o mesmo comprimento de máscara do canal apresentam uma ocorrência similar de SH independentemente do comprimento da região menos dopada apesar de uma maior corrente de dreno. Por outro lado, para mesmo comprimento efetivo de canal o SH é menos pronunciado em transistores GC uma vez que o comprimento de máscara do canal é aumentado para compensar a diferença de corrente. Esta análise é realizada também variando-se a temperatura de 200K a 400K e resultados análogos foram observados apesar do efeito ser mais intenso em baixas temperaturas. / This work presents the study of Self-Heating (SH) effect in Graded-Channel Silicon-On-Insulator (GC SOI) nMOSFETs. The SOI technology characteristics are described with special attention to the GC SOI nMOSFET characteristics. A Self-Heating (SH) analysis was performed using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis was performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations were performed considering the lattice heating in both cases. The models and the thermal conductive constant used in these simulations are also presented. It has been demonstrated that conventional and GC devices with the same mask channel length present similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel lengths, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. This analysis is also carried through varying it temperature of 200K to 400K and analogous results had been observed despite the effect being more intense in low temperatures.

Este trabalho apresenta o estudo do efeito de Auto-Aquecimento (Self-Heating SH) em transistores Silicon-On-Insulator (SOI) com estrutura de canal gradual (GC SOI MOSFET). São apresentadas as características da tecnologia SOI e em especial as características do transistor GC-SOI MOSFET. Foi realizada uma análise do SH usando uma comparação de dispositivos SOI convencionais com GC SOI nMOSFET. Esta análise compara dispositivos com o mesmo comprimento de máscara do canal e dispositivos com o mesmo comprimento efetivo de canal. Simulações numéricas bidimensionais foram efetuadas nas duas análises considerando o aquecimento da rede cristalina. Os modelos e a constante térmica usados nestas simulações também foram apresentados. É demonstrado que os dispositivos GC com o mesmo comprimento de máscara do canal apresentam uma ocorrência similar de SH independentemente do comprimento da região menos dopada apesar de uma maior corrente de dreno. Por outro lado, para mesmo comprimento efetivo de canal o SH é menos pronunciado em transistores GC uma vez que o comprimento de máscara do canal é aumentado para compensar a diferença de corrente. Esta análise é realizada também variando-se a temperatura de 200K a 400K e resultados análogos foram observados apesar do efeito ser mais intenso em baixas temperaturas. / This work presents the study of Self-Heating (SH) effect in Graded-Channel Silicon-On-Insulator (GC SOI) nMOSFETs. The SOI technology characteristics are described with special attention to the GC SOI nMOSFET characteristics. A Self-Heating (SH) analysis was performed using conventional Silicon-On-Insulator (SOI) in comparison to Graded-Channel (GC) SOI nMOSFETs devices. The analysis was performed comparing devices with the same mask channel length and with the same effective channel length. Two-dimensional numerical simulations were performed considering the lattice heating in both cases. The models and the thermal conductive constant used in these simulations are also presented. It has been demonstrated that conventional and GC devices with the same mask channel length present similar occurrence of SH independently of the length of lightly doped region despite the larger drain current. On the other hand, for similar effective channel lengths, the SH is less pronounced in GC transistors as the mask channel length has to be increased in order to compensate the current difference. This analysis is also carried through varying it temperature of 200K to 400K and analogous results had been observed despite the effect being more intense in low temperatures.

Em decorrência da necessidade de se obter circuitos integrados (CIs) cada vez mais velozes e consequentemente dando sequência à lei de Moore, a redução das dimensões dos dispositivos se torna necessária, aumentando assim a capacidade de integração de transistores dentro de um CI, porém, ao passo que ocorre a miniaturização, aparecem efeitos parasitários que afetam o comportamento dos transistores. Sendo assim, torna-se necessária a utilização de novos dispositivos e o uso de diferentes materiais, para dar continuidade à evolução tecnológica. Com o avanço da tecnologia, as indústrias seguiram em dois caminhos diferentes, a tecnologia planar (exemplo: UTBB) e a tridimensional (exemplo: FinFET). Neste trabalho são abordadas estas duas diferentes geometrias. Foram analisados dispositivos UTBOX e UTBB (planares) e os nanofios de porta ômega (?-Gate NW), que tem estrutura tridimensional. O uso de dispositivos com baixa-potência e baixa-tensão tornaram-se ainda mais importante nos dias de hoje, com aplicações em áreas médicas, como aparelhos auditivos e marca passos, em relógios inteligentes, microsensores e etc. Quanto menor for a potência consumida, menor será o calor gerado, resultando em uma redução de custos com sistemas de refrigeração. Os circuitos que operam na região de sublimiar são utilizados em aplicações onde o consumo de energia é mais importante do que a performance, porém, ao trabalhar nessa região os transistores apresentam um alto ganho para pouca variação de tensão. Nos transistores UTBOX e UTBB SOI nMOSFETs foram analisados os parâmetros partindo-se da tensão de limiar em direção à região do transistor no estado desligado, analisando a influência da espessura da região ativa do silício, do comprimento do canal e da implantação do plano de terra nos seguintes parâmetros: tensão de limiar, inclinação de sublimiar, abaixamento da barreira induzido pelo dreno (DIBL), a fuga no dreno induzida pela porta (GIDL) e razão das correntes no estado ligado e desligado (ION/IOFF). A redução do comprimento de canal afeta todos os parâmetros, devido ao efeito de canal curto, que além de reduzir a tensão de limiar, quando o dispositivo opera com baixo VDS (tensão entre dreno (VD) e fonte (VS)), reduz ainda mais quando aplicado alto VDS (em saturação), aumentando o DIBL. Esse efeito foi observado para os dispositivos nanofios com porta ômega, nos três valores de largura de canal analisados. Com o VDS alto também ocorre mais fuga de corrente pela segunda interface para comprimentos de canal curto, o que reduz a razão ION/IOFF. Quanto mais fina é a espessura do canal, melhor é o acoplamento entre as interfaces, resultando em uma melhor inclinação de sublimiar (SS) tornando os valores próximos ao limite teórico de 60mV/dec à temperatura ambiente. Nos resultados experimentais foi possível observar, para os dispositivos UTBOX e UTBB, uma redução de SS de aproximadamente 20 mV/dec, com a redução de tsi. A espessura da região ativa do silício também influencia na distribuição do campo elétrico, sendo diretamente proporcional, ou seja, quanto mais espessa a camada de silício, maior será o campo elétrico. A implantação do plano de terra (GP) tem como um de seus objetivos reduzir as cargas de depleção que são formadas abaixo do óxido enterrado e assim melhorar o controle das cargas no canal pela tensão aplicada no substrato. Essas cargas de depleção aumentam a espessura efetiva do óxido enterrado e também influenciam as cargas dentro do canal, resultando em um maior potencial na segunda interface (canal/óxido enterrado), facilitando a condução no canal, ou seja, reduzindo o valor de VT. Com a presença do GP, o potencial na segunda interface é mais próximo de zero, o que reduz a condução por essa região. Com isso será necessária uma maior tensão para inverter o canal. Porém, o controle das cargas pela tensão aplicada na porta é maior. Os valores extraídos de VT sem GP foram de aproximadamente 0,25V e com GP aproximadamente 0,45V. O estudo feito nos transistores de estrutura de nanofio e porta ômega NMOS e PMOS foi baseado em três parâmetros: tensão de limiar, inclinação de sublimiar e DIBL, com diferentes comprimentos e larguras de canal, sendo possível observar a presença do efeito de canal curto ao analisar os três parâmetros para L a partir de 100nm. Os transistores com Wfin=220nm apresentaram um menor VT em relação aos demais, para explorar esse fato, foram feitas simulações numéricas dos transistores do tipo N com Wfin=220nm e L=100nm. Com as simulações iniciais, os transistores com Wfin=220nm apresentaram um valor da tensão de limiar bem próximo dos demais Wfin. Para explorar o porquê de os dispositivos experimentais apresentarem um deslocamento no VT, foi analisada a condução pela segunda interface, onde, com as simulações com cargas fixas na segunda interface, a curva IDSXVGS simulada ficou próxima da experimental, explicando a redução de VT para Wfin=220nm. Com as simulações com cargas fixas na primeira e segunda interfaces, foi possível notar uma imunidade na inclinação de sublimiar ao adicionar essas cargas, que ocorre devido à pequena altura da região ativa de silício (hfin=10nm) que promove um forte acoplamento entre as interfaces. A largura de canal afetou significativamente os valores de DIBL para Ls menores que 100nm, pois, como o campo elétrico é proporcional à área, os transistores com L pequeno e W grande sofrem forte influência desse campo, resultando em um aumento de VT quando em saturação. / Due to the need to obtain integrated circuits (IC) faster and to follow Moore\'s law, it is necessary to reduce the dimensions of the devices increasing the capacity of integration of transistors inside an IC, however, with the miniaturization appears parasitic effects that affect the behavior of the transistors. Therefore, it is necessary to use new devices and the use of different materials to continue the technological evolution. With the advancement of technology, the industries have followed in two different ways, the planar technology (example: UTBB) and the three-dimensional technology (example: FinFET). In this work, these two different geometries are discussed. UTBOX and UTBB (planar) devices and the ?-Gate NW, which has a three-dimensional structure, were analyzed. The use of low-power low-voltage devices has become even more important nowadays, with applications in medical areas such as hearing aids and pacemakers, in smart watches, microsensors, and so on. The lower the power consumed, the lower the heat generated, resulting in a reduction of costs with cooling systems. The circuits that operate in the subthreshold region are used in applications where power consumption is more important than performance, but when working in this region the transistors have a high gain for little voltage variation. In the UTBOX and UTBB SOI nMOSFETs transistors the parameters starting from the threshold voltage towards the region of the transistor in the off state were studied, analyzing the influence of the silicon active region thickness, the channel length and the ground plane implantation in the following parameters: threshold voltage, subthreshold swing, drain-induced barrier lowering (DIBL), gate-induced drain leakage (GIDL) and current ratio on over off (ION/IOFF). The channel length reduction affects all parameters due to the short channel effect, which in addition to reducing the threshold voltage when the device operates with low VDS (VD) and source (VS)), reduces even further when applied high VDS (in saturation), increasing the DIBL. This effect was observed for the nanowire devices with omega gate, in the three channel width analyzed. With high VDS, there is also more current leakage through the back interface for short channel lengths, which reduces the ION/IOFF ratio. The thinner the channel thickness, the better the coupling between the interfaces, resulting in a better SS, making the values close to the theoretical limit of 60mV/dec at room temperature. In the experimental results, it was possible to observe for the UTBOX and UTBB devices a SS reduction of approximately 20mV/dec, with tsi reduction. The thickness of the active region of the silicon also influences the distribution of the electric field, being directly proportional, that is, the thicker the silicon layer, the greater the electric field. The implementation of the ground plane (GP) has as one of its objectives to reduce the depletion charges that are formed below the buried oxide and thus improve the control of the charges in the channel by the voltage applied at the substrate. These depletion charges increase the effective thickness of the buried oxide and also influence the charges at the channel, resulting in a higher potential at the second interface (buried channel/oxide), facilitating the conduction in the channel, i.e., reducing the value of VT. And with the presence of GP, the potential in the second interface is closer to zero, which reduces the conduction by this region, and then, this will require a higher voltage to invert the channel. However, the charge control by the voltage applied at the gate is higher. Values extracted of VT without GP were approximately 0.25V and with GP approximately 0.45V. The study on the omega-gate nanowire transistors of N and P type was based on three parameters: threshold voltage, subthreshold swing and DIBL, with different channel lengths and widths, being possible to observe the presence of the short channel effect for the three analyzed parameters and L=100 and 40nm. The transistors with Wfin=220nm had a higher VT in relation to the others, suggesting the presence of the narrow channel effect, to explore this fact, numerical simulations of N type transistors with Wfin=220nm and L=100nm were done. With the initial simulations, the transistors with Wfin=220nm did not show a narrow channel effect, where the threshold voltage value is very close to the others Wfin. Another alternative that was explored was the conduction by the back interface, where, with the simulations with fixed charges in the back interface, the simulated IDSXVGS curve was close to the experimental one, explaining the reduction of VT for Wfin=220nm. With the simulations with fixed charges in the front and back interfaces it was possible to notice an immunity in the subthreshold swing when adding these charges, which occurs due to the small height of the silicon active region (hfin=10nm) that promotes a strong coupling between the interfaces. The channel width significantly affected the DIBL values for Ls smaller than 100nm since, the electric field is proportional to the area, and the transistors with small L and large W have strong influence of this field, resulting in an increase of VT when in saturation.

Este trabalho apresenta um estudo da influência do crescimento epitaxial seletivo (SEG) em dispositivos tensionados mecanicamente (strain) em transistores SOI MuGFET de porta tripla. Com a evolução da tecnologia de integração de transistores, alguns efeitos parasitários são eliminados ou diminuídos, porém outros novos surgem. A tecnologia SOI MuGFETs disponibiliza dispositivos de múltiplas portas, tridimensionais. Nesses dispositivos, há um aumento da resistência de contato dos terminais devido ao estreitamento da região de canal, tornando esta resistência significativa em relação à resistência total. A utilização do Crescimento Epitaxial Seletivo (SEG) é uma das opções para diminuir a resistência total, elevando a região de fonte e dreno, causando o aumento da área de contato, diminuindo essa resistência parasitária. Em contrapartida, a utilização dos canais tensionados Uniaxiais, por filme de Si3N4, pela técnica de CESL, que é uma opção de melhora da transcondutância, mas em conjunto com o SEG afasta essa a camada de nitreto, tornando em determinada altura prejudicial ao invés de benéfico. Este trabalho foi realizado baseado em resultados experimentais e em simulações numéricas, mecânicas e elétricas de dispositivos, variando as tecnologias de tensionamento mecânico nos dispositivos com e sem SEG. Variou-se a altura do SEG em simulações, possibilitando extrapolar e obter resultados que de forma experimental não foram possíveis, permitindo um entendimento físico do fenômeno estudado. O resultados obtidos das diferentes tecnologias com e sem o uso de SEG mostraram que, em transistores SOI MuGFETs de porta tripla, o crescimento seletivo epitaxial nos dispositivos com tensão uniaxial piora a transcondutância máxima para dispositivos abaixo de 200nm de comprimento de canal, mas em contra partida torna mais prolongado o efeito pelos dispositivos acima dessa dimensão, como pode ser comprovado nos resultados obtidos. / This paper presents the study of the influence of selective epitaxial growth (SEG) devices mechanically strained (strain) in SOI transistors MuGFET triple gate. With the evolution of integration technology of transistors, some parasitic effects are eliminated or reduced, but new ones arise. MuGFETs SOI technology, devices are multiple ports, three-dimensional, these devices there is an increase in contact resistance of terminals due to the narrowing of the channel region, making considered in relation to total resistance. Use of Selective Epitaxial Growth (SEG) is one of the options to reduce the total resistance, raising the source and drain region, causing increased contact area by reducing the parasitic resistance. In contrast, the use of uniaxial strained channel by a film of Si3N4 by CESL technique is an option for improvement in transconductance, but in conjunction with the SEG away this layer of nitride, making it at some point or detrimental rather than beneficial. This study was based on experimental results and numerical simulations, mechanical and electrical devices of varying technologies in mechanical tensioning devices with and without FES, the height was varied in simulations of the FES, allowing extrapolate and obtain results that way trial was not possible, allowing a physical understanding of the phenomenon. The results of the different technologies with and without the use of FES showed that in SOI transistors MuGFETs triple gate, the selective epitaxial growth in uniaxial strained devices tends to worsen the maximum transconductance for devices below 200nm channel length, but against departure becomes more unrelenting effect on the devices above this size. As can be evidenced in the results obtained.

Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe. / High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.

Les systèmes et applications microélectroniques sont présentes partout dans notre civilisation humaine d’aujourd’hui, depuis le plus simple appareil de notre vie quotidienne jusqu’à des vaisseaux/robots spatiaux qui nous permettent d’observer des images des mondes lointains du Système Solaire et au-delà. L’industrie du semi-conducteur est devenue, depuis sa naissance dans les années 1960, l’une des plus grandes d’aujourd’hui et qui connait une croissance continue avec environ 350 milliards de dollars de chiffre d’affaires annuel. Le composant de base de la microélectronique est le transistor, qui depuis sa conception il y a environ 50 ans a subit une évolution impressionnante en termes de performances, coût et densité d’intégration, cette évolution a été soutenue par des investissements économiques et humains pour suivre ladite « Loi de Moore », qui prédit une augmentation du double de composants intégrés dans une puce tous les deux ans. Le Transistor à Effet de Champ Métal/Oxyde/Semi-conducteur (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET en anglais) est devenu le composant préféré pour les applications numériques dans l’industrie. Avec la miniaturisation du transistor, l’un des grands défis est de limiter l’impact de la variabilité du transistor, qui devient de plus en plus important lorsqu’on diminue les dimensions du composant. Deux transistors dessinés et fabriqués de manière identique peuvent présenter des caractéristiques très différentes; lorsque cette variabilité est de nature systématique, on peut trouver souvent un moyen technologique pour l’éliminer ou on peut modéliser les effets de manière très précise, ce qui n’est pas le cas lorsque la variabilité est de nature statistique, ce type de variabilité est de nature aléatoire et résulte de la nature granulaire de la matière et la difficulté de contrôler le positionnement des atomes, un-par-un, à un niveau industriel. Il est donc nécessaire de caractériser et modéliser la variabilité local statistique pour permettre de mieux prédire les effets indésirables dans des circuits complexes dus à ce type de variabilité et donc de mieux concevoir les produits pour qu’ils soit le plus robustes. Le but de ce projet est d’aller plus loin dans la manière d’appréhender la variabilité et de revisiter les moyens de caractérisation de la variabilité du MOSFET, développer des méthodes d’analyse de données pour extraire le maximum d’information pertinente sur les sources de variabilité et leur impact dans les performances des composants, le tout basé sur des données expérimentales obtenues sur des structures de test améliorées. L’un des points clés de notre méthode de caractérisation de la variabilité développée dans ce projet, est de permettre une modélisation statistique précise des variations du procédé de fabrication et leur impact dans l’environnement design; pour réussir notre objectif, les méthodes développées doivent fournir des paramètres statistiques avec un intervalle de confiance bien établi, et qui peuvent être implémentés dans des modèles statistiques dans la chaine design. Pour amener à bien les objectifs, ce projet bénéficie du support de STMicroelectronics et du Laboratoire IMEP-LACH, qui permettent l’accès à du silicium en technologie 28 nm avec des structures de test dédiées « fait maison » et à des équipements dernière génération de caractérisation. Le projet est principalement focalisé sur la variabilité locale (à l’échelle du micromètre et en dessous), que ce soit de nature systématique ou aléatoire. Cependant, quelques aspects de la variabilité à plus grande échelle (inter-puce) sont étudiés pour pouvoir discriminer les différentes sources de la variabilité locale. / Microelectronic systems and their applications are everywhere in the current human civilization, from the simplest gadget in our everyday life to fiction-like space probes which let us see wonderful pictures of other worlds within the Solar System and beyond. The semiconductor industry has become, since its inception in the 1960s, one of the largest and growing industries with approximately a 350 billion dollars market.The central device of microelectronics is the transistor, which has experienced enormous improvements in the last half century, boosted by the economic and human investments to follow the so-called “Moore’s law”, which states that the number of transistors in a chip doubles every two years. Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) has become the preferred transistor in the industry for digital applications. With the miniaturization of the transistor, a major challenge is to deal with transistor Variability, as its impact becomes more and more important with decreasing size. Two identically fabricated transistors may present highly different characteristics; when this Variability is systematic in nature, we can often find a way to eliminate it using fabrication means or model it very accurately; nevertheless, Statistical Variability is the other major component of Local Variability which is more complicated to deal with; in fact, Statistical Variability is random in nature, as it results from de granular nature of matter and also from the difficulty of control atom per atom placement in an industrial level. Then, it becomes necessary to precisely characterize and model Local Statistical Variability for Variability-aware design to better predict circuit fails from simple standard circuits to final products.The purpose of this project is to go further in the characterization means of MOSFET Local Variability by revisiting existing test structures, and to develop methods of analysis to extract the maximum of relevant information about transistor Variability sources and impact from experiments conducted on improved test structures. One important merit for the Variability characterization methods developed in this project is to enable an accurate statistical modeling of Local Variations and their impact throughout the design space; to meet the goal, the methods developed must provide statistical parameters with well-established confidence, and be suited for implementation on statistical models within the circuit design flow.To achieve this objective, this work is a common project of STMicroelectronics and IMEP-LAHC laboratory, which benefit from access to 28 nm silicon technology home design test structures and state-of-the-art characterization facilities.The project is primarily focused on local variability (in micrometer scale and below), whether of systematic or statistical nature. Nevertheless, some aspects of Intrawafer and Systematic Variations are studied when it is necessary to discriminate Local Variability from other effects.

La motivation de cette thèse est deux des principaux problèmes soulevés par la mise à l'échelle des appareils de la nouvelle ère dans la conception MOSFET contemporaine: le développement d'un modèle de courant de drain analytique et compact, valable dans toutes les régions d'opération, décrivant précisément les caractéristiques Id-Vg et Id-Vd des dispositifs FDSOI à canaux courts et l'étude des problèmes de fiabilité et de variabilité de ces transistors évolués à l'échelle nanométrique. Le chapitre II fournit une base théorique et technique pour une meilleure compréhension de cette thèse, en mettant l'accent sur les paramètres électriques MOSFET critiques et les techniques d'extraction. Il démontre les méthodologies de Y-Function et de Split-CV pour la caractérisation électrique dans divers types de semiconducteurs. L'influence du niveau de l'oscillateur du signal AC sur la mesure de la mobilité efficace par la technique Split-CV dans MOSFET est également analysée. Une nouvelle méthodologie basée sur la fonction Lambert W qui permet d'extraire les paramètres MOSFET sur la gamme de tension de grille complète, permettant de décrire la transition entre les regions en dessous et au dessus du seuil, malgré la réduction de la tension d'alimentation. Enfin, certains éléments de base concernant le bruit à basse fréquence (LFN) sur la caractérisation MOSFET sont décrits. Le chapitre III présente la modélisation analytique et compacte du courant de drain dans les MOSFET FDSOI à l'échelle nanométrique. Des modèles analytiques simples pour les tensions de seuil de la grille avant et arrière et les facteurs d'idéalité ont été développés en termes de paramètres de géométrie du dispositif et de tensions de polarisation appliquées avec contrôle de la grille arrière. Un modèle analytique et compact de courant de drain a été développé pour les MOSFET FDSOI UTBB légèrement dopés avec contrôle de la grille arrière, prenant en compte la géométrie réduite et d'autres effets importants dans ces technologies et implémenté en Verilog-A pour la simulation des circuits dans Cadence Spectre. Le chapitre IV traite des problèmes de fiabilité dans les transistors FDSOI. La dégradation par des porteurs chauds des nMOSFET UTBB FDSOI decananométrique a été étudiée dans différentes conditions de stress de drain et de grille. Les mécanismes de dégradation ont été identifiés grâce à des mesures LFN à température ambiante dans les domaines de la fréquence et du temps. Un modèle de vieillissement HC est proposé permettant de prédire la dégradation du dispositif stressé dans différentes conditions de polarisation, en utilisant de paramètres uniques déterminés pour chaque technologie extraits par des mesures. Enfin, les caractéristiques de stress NBTI et le comportement de relaxation après stress sous la polarisation positive des pMOSFET UTBB FDSOI de grille HfSiON ont été étudiés. Un modèle pour le NBTI a été développé en considérant les mécanismes de piégeage/dépiégeage des trous, en fonction de la température et de la tension de polarisation. Le chapitre V présente des études sur les problèmes de variabilité dans les dispositifs décananométriques. Les principales sources de courant de drain et de grille de la variabilité locale ont été étudiées. Dans cet aspect, un modèle de courant de drain de la variabilité locale, valable pour toute condition de polarisation de grille et de drain, a été développé. Les principaux paramètres MOSFET de variabilité locale et globale ont été extraits par ce modèle pour différentes technologies CMOS (Bulk 28nm, FDSOI 14nm, Si bulk FinFET 14nm, nanofils Si/SiGe sous 15nm). L’impact de la variabilité du courant de drain sur les circuits de Cadence Spectre est présenté. Un résumé de cette thèse est présenté au chapitre VI, qui souligne les principales contributions à la recherche et les orientations de recherche futures sont suggérées. / Τhe motivation for this dissertation is two of the main issues brought up by the scaling of new-era devices in contemporary MOSFET design: the development of an analytical and compact drain current model, valid in all regions of operation describing accurately the transfer and output characteristics of short-channel FDSOI devices and the investigation of reliability and variability issues of such advanced nanoscale transistors. Chapter II provides a theoretical and technical background for the better understanding of this dissertation, focusing on the critical MOSFET electrical parameters and the techniques for their extraction. It demonstrates the so-called Y-Function and Split-CV methodologies for electrical characterization in diverse types of semiconductors. The influence of AC signal oscillator level on effective mobility measurement by split C-V technique in MOSFETs is also analyzed. A new methodology based on the Lambert W function which allows the extraction of MOSFET parameters over the full gate voltage range, enabling to fully capture the transition between subthreshold and above threshold region, despite the reduction of supply voltage Vdd is presented. Finally, some basic elements concerning the low frequency noise (LFN) on MOSFETs characterization are described. Chapter III presents the analytical drain current compact modeling in nanoscale FDSOI MOSFETs. Simple analytical models for the front and back gate threshold voltages and ideality factors have been derived in terms of the device geometry parameters and the applied bias voltages with back gate control. An analytical compact drain current model has been developed for lightly doped UTBB FDSOI MOSFETs with back gate control, accounting for small geometry and other significant in such technologies effects and implemented via Verilog-A code for simulation of circuits in Cadence Spectre. Chapter IV is dealing with reliability issues in FDSOI transistors. The hot-carrier degradation of nanoscale UTBB FDSOI nMOSFETs has been investigated under different drain and gate bias stress conditions. The degradation mechanisms have been identified by combined LFN measurements at room temperature in the frequency and time domains. Based on our analytical compact model of Chapter III, an HC aging model is proposed enabling to predict the device degradation stressed under different bias conditions, using a unique set of few model parameters determined for each technology through measurements. Finally, the NBTI stress characteristics and the recovery behavior under positive bias temperature stress of HfSiON gate dielectric UTBB FDSOI pMOSFETs have been investigated. A model for the NBTI has been developed by considering hole-trapping/detrapping mechanisms, capturing the temperature and bias voltage dependence. In Chapter V studies of variability issues in advanced nano-scale devices are presented. The main sources of drain and gate current local variability have been thoroughly studied. In this aspect, a fully functional drain current mismatch model, valid for any gate and drain bias condition has been developed. The main local and global variability MOSFET parameters have been extracted owing to this generalized analytical mismatch model. Furthermore, the impact of the source-drain series resistance mismatch on the drain current variability has been investigated for 28nm Bulk MOSFETs. A detailed statistical characterization of the drain current local and global variability in sub 15nm Si/SiGe Trigate nanowire pMOSFETs and 14nm Si bulk FinFETs has been conducted. Finally, a complete investigation of the gate and drain current mismatch in advanced FDSOI devices has been performed. Finally, the impact of drain current variability on circuits in Cadence Spectre is presented. An overall summary of this dissertation is presented in Chapter VI, which highlights the key research contributions and future research directions are suggested.

Les MOSFET III-V sont considérés comme des candidats potentiels pour les futures générations d'applications à base de logique CMOS, grâce à leurs remarquables propriétés de transport.D'un autre côté, ils souffrent de désavantages physiques (tels que les courants tunnels ou leur faible densité d'états), et de difficultés technologiques (en particulier les états d'interface), qui peuvent détériorer leur performance.Dans cette thèse, un modèle physique et compact du MOSFET III-V est établi. Il inclut une description des effets canaux courts, de la charge d'inversion (considérant aussi les effets de structure de bandes dans les canaux fins), les caractéristiques de transport, les courants tunnels, et les composants externes tels que les résistances d'accès et les capacités parasites.En utilisant ce modèle, la performance des MOSFET III-V est évaluée par rapport à celle du Si, et une feuille de route incluant ces dispositifs est présentée.Il est démontré que les canaux à matériaux III-V pourraient présenter une meilleure performance que le Si, pourvu que le problème des pièges d'interface soit résolu. Si tel est le cas, ils pourraient être introduits au noeud "7nm".La densité de pièges, à partir de laquelle la performance des MOSFET III-V devient pire que celle du Si, dépend de l'architecture considérée.Enfin, les canaux très fins nécessaires pour atteindre une bonne performance avec les matériaux III-V risquent de poser des problèmes de variabilité, qui pourraient avec des répercussions négatives au niveau de la conception du circuit. / III-V MOSFETs are considered as a potential candidate for next generation CMOS logic applications thanks to their remarkable transport properties.On the other hand, they suffer from several physical drawbacks (such as tunneling currents or low density-of-states) and technological difficulties (in particular interface traps), which may deteriorate their performance.In this thesis, a physical compact model of the III-V MOSFET is established. It includes a description of short-channel effects, inversion charge (also considering bandstructure effects in thin channels), transport characteristics, tunneling currents, and external components such as access resistances and fringe capacitances. Using this model, the performance of III-V MOSFETs is benchmarked against Si, and a possible roadmap including these devices is presented. It has been found that the III-V channels may feature a significant performance advantage over Si, provided that the interface traps issue be solved. In that case, they may be introduced at the "7nm" node. The critical trap density, above which the performance of III-V MOSFETs degrades below Si, depends on the architecture considered. Finally, the very thin channels required to achieve a good performance with III-V materials may raise variability issues that could reverberate negatively at the circuit design level.