International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Boeing Commercial Airplanes has used many methods in the past to measure the structural loads on the wings of its airplanes. The most recent approach is to use arrays of MEMS pressure sensors on the top and bottom surfaces of the wings. By knowing the difference in pressure between the top and bottom of the wings the structural loads on the wings can be calculated. It was decided that in order to build an array of 1100 sensors it would be necessary to condition the sensors and convert the analog output to a digital form at the site of the pressure measurement. This process was taken one step further by converting the output of the A/D converter into engineering units within the sensor module as well. The array is built using a flex circuit card in one foot sections that can be interconnected to form an array of up to 125 sensors. There is a sensor location every two inches on the flex circuit but not all locations are populated. This paper will describe not only the pressure belt but the lessons learned during the development and the implications that these lessons have for smart transducers in general.

Silver sintering technology has received considerable attention in recent years because it has the potential to be a suitable interconnection material for high-temperature power electronic packaging, such as high melting temperature, high electrical/thermal conductivity, and excellent mechanical reliability. It should be noted, however, that pressure (usually between three to five MPa) was added during the sintering stage for attaching power chips with area larger than 100 mm2. This extra pressure increased the complexity of the sintering process. The maximum chip size processed by pressure-free sintering, in the published resources, was 6 x 6 mm2. One objective of this work was to achieve chip-attachment with area of 13.5 x 13.5 mm2 (a chip size of one kind of commercial IGBT) by pressure-free sintering of nano-silver paste. Another objective was to fabricate high-power (1200 V and 150 A) multi-chip module by pressure-free sintering. In each module (half-bridge), two IGBT dies (13.5 x 13.5 mm2) and two diode dies (10 x 10 mm2) were attached to a DBC substrate. Modules with solder joints (SN100C) and pressure-sintered silver joints were also fabricated as the control group. The peak temperature in the process of of pressure-free sintering of silver was around 260oC, whereas 270oC for vacuum reflowing of solder, and 280oC under three MPa for pressure-sintering of silver. The process for wire bonding, lead-frame attachment, and thermocouple attachment are also recorded. Modules with the above three kinds of joints were first characterized by electrical methods. All of them could block 1200 V DC voltage after packaging, which is the voltage rating of bare dies. Modules were also tested up to the rated current (150 A) and half of the rated voltage (600 V), which were the test conditions in the datasheet for commercial modules with the same voltage and current ratings. I-V characteristics of packaged devices were similar (on-resistance less than 0.5 mohm). All switching waveforms at transient stage (both turn-on and turn-off) were clean. Six switching parameters (turn-on delay, rise time, turn-off delay, fall time, turn-on loss, and turn-off loss) were measured, which were also similar (<9%) among different kinds of modules. The results from electrical characterizations showed that both static characterizations and double-pulse test cannot be used for evaluating the differences among chip-attach layers. All modules were also characterized by their thermal performances. Transient thermal impedances were measured by gate-emitter signals. Two setups for thermal impedance measurement were used. In one setup, the bottoms of modules were left in the air, and in the other setup, bottoms of modules were attached to a chiller (liquid cooling and temperature controlled at 25oC) with thermal grease. Thermal impedances of three kinds of modules still increased after 40 seconds for the testing without chiller, since the thermal resistance of heat convection from bottom copper to the air was included , which was much larger than the sum of the previous layers (from IGBT junction, through the chip-attach layer, to the bottom of DBC substrate). In contrast, thermal impedances became almost stable (less than 3%) after 15 seconds for all modules when the chiller was used. Among these three kinds of modules, the module with pressure sintered joints had the lowest thermal impedance and the thermal resistance (tested with the chiller) around 0.609oK/W, In contrast, the thermal resistance was around 964oK /W for the soldered module, and 2.30oK /W for pressure-free sintered module. In summary, pressure-free large-area sintered joints were achieved and passed the fabrication process for IGBT half-bridge module with wiring bonding. Packaged devices with these kinds of joints were verified with good electrical performance. However, thermal performances of pressure-free joints were worse than solder joints and pressure-sintered joints. / Master of Science

Ce travail s'intègre dans les domaines de l'analyse et de la prédiction de la fiabilité des assemblages Multi-Chip Module. Il présente l'étude de fiabilité de microcâblages filaires (wire bonding) en très haute température à partir d'essais de vieillissement et d'analyses expérimentales. Les résultats permettent d'identifier les mécanismes de dégradation et d'évaluer les températures limites d'utilisation de ces interconnexions. Il développe une étude du comportement thermomécanique des joints collés à partir d'essais de caractérisation mécanique, d'essais de vieillissement accéléré et de simulations numériques par éléments finis. Ces méthodes permettent d'évaluer la criticité des assemblages dès la phase de conception. / This work is performed in analysis and prediction areas of Multi-Chip Module package reliability. It presents a reliability study on wire bonding in high temperature environment from aging tests and experimental analyzes. Results permit to identify degradation mechanisms and evaluate temperature limits of these interconnections. It develops a study of the thermomechanical behavior of adhesive joints from mechanical characterization tests, accelerated aging tests and finite element simulations. These methods are used to assess the criticality of packages from the design phase.

This paper describes the design, fabrication, and testing of a 1.2 kV, 6.5 mΩ, half-bridge, SiC MOSFET power module to evaluate the impact of parametric device tolerances on electrical and thermal performance. Paralleling power devices increases current handling capability for the same bus voltage. However, inherent parametric differences among dies leads to unbalanced current sharing causing overstress and overheating. In this design, a symmetrical DBC layout is utilized to balance parasitic inductances in the current pathways of paralleled dies to isolate the impact of parametric tolerances. In addition, the paper investigates the benefits of flexible PCB in place of wire bonds for the gate loop interconnection to reduce and minimize the gate loop inductance. The balanced modules have dies with similar threshold voltages while the unbalanced modules have dies with unbalanced threshold voltages to force unbalanced current sharing. The modules were placed into a clamped inductive DPT and a continuous, boost converter. Rogowski coils looped under the wire bonds of the bottom switch dies to observe current behavior. Four modules performed continuously for least 10 minutes at 200 V, 37.6 A input, at 30 kHz with 50% duty cycle. The modules could not perform for multiple minutes at 250 V with 47.7 A (23 A/die). The energy loss differential for a ~17% difference in threshold voltage ranged from 4.52% (~10 µJ) to -30.9% (~30 µJ). The energy loss differential for a ~0.5% difference in V_th ranged from -2.26% (~8 µJ) to 5.66% (~10 µJ). The loss differential was dependent on whether current unbalance due to on-state resistance compensated current unbalance due to threshold voltage. While device parametric tolerances are inherent, if the higher threshold voltage devices can be paired with devices that have higher on-state resistance, the overall loss differential may perform similarly to well-matched dies. Lastly, the most consistently performing unbalanced module with 17.7% difference in V_th had 119.9 µJ more energy loss and was 22.2°C hotter during continuous testing than the most consistently performing balanced module with 0.6% difference inV_th. / Master of Science / This paper describes the design, construction, and testing of advanced power devices for use in electric vehicles. Power devices are necessary to supply electricity to different parts of the vehicle; for example, energy is stored in a battery as direct current (DC) power, but the motor requires alternating current (AC) power. Therefore, power electronics can alter the energy to be delivered as DC or AC. In order to carry more power, multiple devices can be used together just as 10 people can carry more weight than 1 person. However, because the devices are not perfect, there can be slight differences in the performance of one device to another. One device may have to carry more current than another device which could cause failure earlier than intended. In this research project, multiple power devices were placed into a package, or "module." In a control module, the devices were selected with similar properties to one another. In an experimental module, the devices were selected with properties very different from one another. It was determined that the when the devices were 17.7% difference, there was 119.9 µJ more energy loss and it was 22.2°C hotter than when the difference was only 0.6%. However, the severity of the difference was dependent on how multiple device characteristics interacted with one another. It may be possible to compensate some of the impact of device differences in one characteristic with opposing differences in another device characteristic.