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Carbon nanotubes are promising candidates for enhancing electronic devices in the future at the nanoscale level. Their integration into today’s electronics has however been challenging due to the difficulties in controlling their orientation, location, chirality and diameter during formation. This thesis investigates and develops new techniques for the controlled growth and assembly of carbon nanotubes as a way to address some of these challenges. Colloidal lithography using nanospheres of 450 nm in diameter, acting as a shadow mask during metal evaporation, has been used to pattern thin films of single-walled carbon nanotube multilayer catalysts on Si and Si/SiO2 substrates. Large areas of periodic hexagonal catalyst islands were formed and chemical vapor deposition resulted in aligned single-walled carbon nanotubes on Si substrates within the hexagonal array of catalyst islands. On silicon dioxide, single-walled carbon nanotubes connecting the hexagonal catalyst islands were observed. To help explain these observations, a growth model based on experimental data has been used. Electrostatic interaction, van der Waals interaction and gas flow appear to be the main forces contributing to single-walled carbon nanotube alignment on Si/SiO2. Although the alignment of single-walled carbon nanotubes on Si substrates is still not fully understood, it may be due to a combination of the above factors, in addition to silicide-nanotube interaction. Atomic force microscopy and Raman spectroscopy of the post-growth samples show single-walled carbon nanotubes of 1-2 nm in diameter. Based on the atomic force microscopy data and Raman spectra, a mixture of individual and bundles of metallic and semiconducting nanotubes were inferred to be present. A novel technique based on direct nanowriting of carbon nanotube catalysts in liquid form has also been developed. The reliability of this method to produce nanoscale catalyst geometries in a highly controlled manner, as required for carbon nanotube growth and applications, was demonstrated. Chemical vapor deposition growth of the patterned regions shows individual and bundles of single-walled carbon nanotubes. This was confirmed by Raman spectroscopy of the samples, giving single-walled carbon nanotubes ~1-2 nm in diameter. The capabilities of the nanowriting process were also explored for direct-writing of carbon based nanomaterials such as single-walled carbon nanotubes and C60 molecules. Finally, a brief survey on carbon nanotube field-effect transistor modeling tools has been presented, followed by two-terminal current-voltage measurements on colloidal lithography and nanowriting samples. Results show primarily ohmic behavior with conductances of ~0.86-16.5 μS for the hexagonal catalyst array patterned samples for various geometries and ~0.27-1 μS for the nanowriting samples. In addition, compact models have been used to gain insights into the device performance and the unique advantages of the hexagonal array approach over devices fabricated using parallel or randomly distributed SWCNTs. Device performance appears to be determined primarily by the contact resistance which includes both Schottky barrier resistances and an interface resistance. In summary, colloidal lithography and direct-writing of single-walled carbon nanotube catalyst have been used to achieve the controlled growth and assembly of carbon nanotubes. Electronic transport of carbon nanotube devices fabricated using these two methods showed near ohmic behavior with device performance modeled primarily by the contact resistance. The approaches developed in this thesis allow nanoscale control over catalyst deposition and nanotube growth which makes them promising for the fabrication of future carbon nanotube electronic devices.

Fabrication of nanoscale Josephson junctions and Superconducting Quantum Interference Devices (SQUID) is very promising but challenging topic in the superconducting electronics and device technology. In order to achieve best sensitivity of SQUIDs and to reproduce them easily with a straightforward method, new fabrication techniques for realization of nanoSQUIDs needs to be investigated. This study concentrates on investigation of new fabrication methodology for manufacturing nanoSQUIDs with High Temperature Bi-Crystal Grain Boundary Josephson Junctions fabricated onto SrTiO3 bi-crystal substrates using YBa2Cu3O7-δ (YBCO) thin-films. In this process nanoscale patterning of YBCO was realized by using electron beam patterning and physical dry etching of YBCO thin films on STO substrates. YBCO thin films were deposited using RF magnetron sputtering technique in the mixture of Ar and O2 gases and followed by annealing at high temperatures in O2 atmosphere. Structural characterization of YBCO thin films was done by Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDX). Superconducting properties of thin films was characterized by AC magnetic susceptibility measurements. Nanoscale structures on YBCO thin films were fabricated by one E-Beam Lithography (EBL) step followed by Reactive Ion Etching (RIE) and physical dry etching. First SiO2 thin film were deposited on YBCO by RF magnetron sputtering and it was patterned by EBL using Polystyrene (PS) as resist material and RIE. Then SiO2 was used as an etch mask for physical dry etching of YBCO and nanoscale structures on YBCO were formed.

As CMOS manufacturing technology approaches fundamental limits, researchers are looking for revolutionary technologies beyond the end of the CMOS roadmap. Recent progress on devices, nano-manufacturing, and assembling of nanoscale structures is driving researchers to explore possible new fabrics, circuits and architectures based on nanoscale devices. Several fabric architectures based on various nanoscale devices have been proposed for nanoscale computation. These show great advantages over conventional CMOS technology but focus on FPGA-style applications. There has been no work shown for nanoscale architectures tuned for a processor application. This dissertation proposes a novel nanowire-based 2-D fabric referred to as Nanoscale Application-Specific IC (NASIC). Compared with other nanoscale fabric architectures, NASIC designs can be optimized for higher density and performance in an application-specific way (similar to ASIC in this aspect) and used as a fabric for processors. We present the design of a wire-streaming processor (WISP-0), which exercises many NASIC circuit styles and optimizations. A major goal of NASIC, and for other nanoscale architectures, is to preserve the density advantage of underlying nanodevices. Topological, doping and interconnect constraints can severely impact the effective density that can be achieved at the system level. To handle these constraints, we propose a comprehensive set of optimizations at both circuit and logic levels. Evaluations show that with combined optimizations, WISP-0 is still 39X denser than the equivalent design in 18nm CMOS technology (expected in 2018 by ITRS). Another key challenge for nanoscale computing systems is dealing with the unreliable nanodevices. The defect rate of nanodevices is expected to be orders of magnitude higher than what we are accustomed to with conventional CMOS processing based on lithography. In this dissertation, we first investigate various sources of defects/faults in NASIC circuits and analyze their impacts. Then, a hierarchical, multi-layer solution is proposed to tolerate defects/faults. Simulation shows that the yield of WISP-0 is as high as 50% even if as many as 15% transistors are defective. Estimations of the speed, power consumption of NASIC designs are also presented.

La miniaturisation croissante des transistors MOS a rendu les mémoires RAM de plus en plus sensibles aux particules alpha émises par les éléments radioactifs naturellement présents dans les matériaux utilisés dans la fabrication de ces mémoires. En effet, au niveau du sol, le taux d'erreurs logiques déclenchées par ces particules est comparable à celui déclenché par les neutrons issus du rayonnement cosmique. L'objectif principal de ce travail de thèse est la mise au point de méthodes d'évaluation de ce taux et permettre par la suite de proposer des solutions technologiques. Ainsi, dans le cadre d'une approche théorique, nous avons développé des modèles permettant d'évaluer le taux des erreurs logiques déclenchées par les chaines de l'uranium et du thorium dans un état d'équilibre séculaire mais aussi de déséquilibre. Ceci passe par une identification des radioéléments critiques, c'est-à-dire ceux qui sont capables d'augmenter l'émissivité (et ainsi le taux d'erreurs d'aléas logiques) à des niveaux inacceptables pendant la durée de vie du composant. La prise en compte de l'état de déséquilibre des chaines de désintégration radioactive dans ce volet théorique permet une approche réaliste de la contamination. Nous avons également proposé une méthode expérimentale pour analyser l'évolution de l'état radioactif dans les matériaux utilisés dans la fabrication des mémoires. Dans cette approche expérimentale, nous avons combiné trois techniques de mesure complémentaires: la spectroscopie alpha, la spectroscopie gamma et l'ICPMS. / The increasing miniaturisation of MOS transistors has made RAM memories more and more sensitive to alpha particles emitted by radioactive elements naturally present in the materials used for memory fabrication. Indeed, at ground level, the soft error rate triggered by these particles is comparable to that triggered by neutrons from cosmic rays. The main purpose of this work aims to develop methods to evaluate this rate allowing thereafter suggesting technologies mitigations. Thus, in the context of a theoretical approach, we have developed models to estimate soft errors rate triggered by uranium and thorium chains in secular equilibrium but also disequilibrium state. This requires identification of critical radionuclides those are able to increase the emissivity (and thus the soft error rate) to unacceptable levels during device lifetime. Taking into account disequilibrium state of decay chains in theoretical study provides a realistic approach to the contamination. We have also proposed an experimental method to analyze the radioactive state evolution in materials used for memory fabrication. In this experimental approach, we have combined three complementary measurement techniques: alpha spectroscopy, gamma spectroscopy and ICPMS.

Les progrès technologiques de ces dernières années ont permis une très forte intégration des composants de la microélectronique à l'échelle nanométrique. Face aux limites de la miniaturisation classique, les technologies d'intégration en trois dimensions (3D) ouvrent la voie vers des dispositifs miniaturisés hétérogènes avec de nouvelles générations de puces. En parallèle, de nouveaux concepts tels que les nanofils sans jonction et les nanofils en silicium polycristallins permettent à terme d'imaginer des procédés froids et des dispositifs à faible coût permettant une intégration 3D hyperdense sur un CMOS stabilisé. La fabrication de NEMS à base de nanofils polycristallins pour la détection de masse sur CMOS est donc une nouvelle opportunité « More-Than-Moore ». Les capteurs pourraient être disposés en réseau dense en s'inspirant des architectures mémoires et imageurs. L'adressage individuel de chaque NEMS, la possibilité de les fonctionnaliser à la détection de molécules particulières, et la multiplication des capteurs sur une grande surface (« Very Large Integration » (VLSI)) permettraient la mise en œuvre d'un nouveau genre de capteur multi-physique, compact et ultrasensible. Le but de ces travaux de thèse a donc été la fabrication et l'évaluation des performances de NEMS à base de nanofils en poly-silicium. L'enjeu fut de trouver des procédés avec un budget thermique compatible à une intégration sur back-end. Une étude rigoureuse sur les propriétés physico-chimiques de la couche a été corrélée aux performances électriques, mécaniques, ainsi qu'au rendement des NEMS poly-Silicium, ce qui nous a permis de faire une sélection des meilleurs procédés de fabrication. Les NEMS fabriqués à basse température avec une couche active déposée à température ambiante et recristallisée par laser ont montré des performances, que ce soit au niveau de la transduction (piézorésistivité), ou de la stabilité du résonateur compétitives par rapports aux références monocristallines. / Recently, technological advances lead to a very large scale integration (VLSI) of microelectronics components at the nanoscale. Faced with the traditional miniaturization limits, the three dimensions (3D) integration open the door to heterogeneous miniaturized devices, with new chip generations. At the same time, new concepts such as junctionless nanowires and polycrystalline silicon nanowires allow to imagine low temperature processes and low-cost devices for a 3D integration on a stabilized CMOS. Poly-silicon nanowire based NEMS on CMOS for mass detection is a new "More-Than-Moore" opportunity. The NEMS could be arranged in a dense network like memory and image sensor architectures. The individual addressing of each NEMS, the functionalization for the detection of specific molecules within a large area (VLSI), allow the implementation of a new type of Multi-physics sensors, compact and highly sensitive. The purpose of this thesis has been the manufacturing and the performance evaluation of poly-silicon nanowire based NEMS. The challenge was to find the best processes with a back-end compatible thermal budget. A rigorous study of the layer physicochemical properties has been correlated with the electrical, mechanical performances and the yield of poly-silicon NEMS. This allowed us to make a selection of the best fabrication processes. NEMS manufactured at very low temperature with an active layer deposited at room temperature and recrystallized by a laser annealing exhibited high performances in terms of transduction (piezoresistivity) and frequency stability comparable to monocrystalline references. Polycrystalline silicon.

Cette thèse s'inscrit dans le cadre du développement des technologies CMOS 32/28nm chez STMicroelectronics. Elle porte sur l'étude d'empilements de grille métal/diélectrique high-k élaborés selon une stratégie d'intégration Gate First, où le couple TiN/HfSiON est introduit avec une couche interfaciale SiON et une encapsulation de la grille TiN par du polysilicium. Cette étude s'est principalement focalisée sur l'analyse des interactions entre les différentes couches constituant les empilements, en particulier des additifs lanthane et aluminium, employés pour moduler la tension de seuil Vth des transistors NMOS et PMOS respectivement. Les analyses physico-chimiques réalisées au cours de ces travaux ont permis de mettre en évidence la diffusion en profondeur des éléments La et Al à travers le diélectrique de grille HfSiON sous l'effet du recuit d'activation des dopants à 1065°C. Les résultats obtenus ont montré que ce processus de diffusion entraine une réaction du lanthane et de l'aluminium avec la couche interfaciale de SiON pour former un silicate stable La(ou Al)SiO au profit de la couche de SiON. L'analyse des propriétés électrique des structures MOS a permis de révéler que la présence d'atomes La ou Al proximité de l'interface HfSiON/SiON conduit à la présence d'un dipôle généré à cette interface, qui a pour effet de décaler le travail de sortie effectif de la grille métallique. / This thesis is part of the development of CMOS technologies 32/28nm STMicroelectronics. It focuses on the study of stacks of metal / high-k dielectric prepared by an integration strategy Gate First , where the couple TiN / HfSiON gate is introduced with an interfacial layer SiON and encapsulation of TiN gate polysilicon by . The study was mainly focused on the analysis of interactions between the various layers forming the stacks , in particular lanthanum and aluminum additives , used for modulating the threshold voltage Vth of the PMOS and NMOS transistors respectively . The physico-chemical analyzes in this work helped to highlight the depth distribution of the elements La and Al through the HfSiON gate dielectric under the influence of dopant activation annealing at 1065 ° C. The results obtained showed that this diffusion process causes a reaction of lanthanum and aluminum with the interfacial layer of SiON to form a stable silicate La ( or Al ) SiO benefit of the SiON layer . The analysis of electrical properties of MOS structures revealed that the presence of the atoms near the Al or HfSiON / SiON interface leads to the presence of a dipole generated at this interface , which has the effect of shifting actual output work of the metal gate.

L’intégration à large échelles de bits quantiques (qubits) nécessite le développement de systèmes quantiques à deux niveaux à l’état solide comme par exemple des spins électroniques confinés dans des boîtes quantiques ou des fermions de Majorana dans des nanofils semiconducteurs.Les trous confinés à une ou deux dimensions dans des hétérostructures à base de germanium sont de bons candidats pour de tels qubits parce qu’ils offrent i) une forte interaction spin-orbite (SOI) conduisant à des facteurs de Landé relativement grands, ii) un couplage hyperfin réduit laissant entrevoir un long de temps de cohérence de spin et iii) des masses efficaces relativement faibles favorisant le confinement quantique. Au cours de cette thèse, j’ai étudié le transport de trous dans des systèmes unidimensionnels et bidimensionnels faits à partir d’hétérostructures Ge/Si_0.2Ge_0.8 à contrainte compressive. Une partie importante de mon travail de recherche a été consacrée au développement de techniques de fabrication pour ces dispositifs semi-conducteurs. J’ai débuté par la fabrication de dispositifs de type "barre de Hall" à partir d’hétérostructures Ge/SiGe non dopées.J’ai étudié deux types d’ hétérostructures contenants un puits quantique de Ge contraint: l’une où le puits de Ge est à la surface de la structure donc facilement accessible aux contacts métalliques, et l’autre où le puitsest enterré à 70nm sous la surface permettant d’avoir une mobilité élevée.Les propriétés électroniques du gaz de trou bidimensionnel confiné dans lepuits de Ge ont été étudiées à travers des mesures de magnéto-transportjusqu’à 0,3 K. Pour le puits enterré, mes mesures ont révélé un caractère dominant de trou lourd, ce qui est attendu dans le cas d’une contrainte compressive en combinaison avec un confinement bidimensionnel. Les dispositifs avec un puits de Ge superficiel ont montré un transport diffusif et un effet d’anti-localisation faible, ce qui est dû à l’interférence quantique de differents chemins de diffusion en présence du SOI. Le fait que le puits de Ge soit situé à la surface permet des champs électriques perpendiculaires relativement grands et, par conséquent, un plus fort SOI de type Rashba. J’ai été en mesure d’estimer l’énergie caractéristique du SOI en obtenant une valeur d’environ 1 meV. Pour la réalisation de nano-dispositifs quantiques,j’ai utilisé l’ hétérostructure avec un puits de Ge enterré où la mobilité des trous se rapproche de 2 × 105 cm2/Vs. En utilisant la lithographie par faisceau d’électrons, des grilles métalliques à l’échelle nanométrique ont été définies sur la surface de l’échantillon afin de créer des constrictions unidimensionnelles dans le gaz de trous bidimensionnel. J’ai ainsi réussi à observer la quantification de la conductance dans des fils quantiques d’une longueur allant jusqu’à ~ 600 nm. Dans ces fils, j’ai étudié l’effet Zeeman sur les sous-bandes unidimensionnelles. J’ai trouvé des grands facteurs g pour le champ magnétique perpendiculaire, et des petits facteurs g dans le plan. Cette forte anisotropie indique un caractère de trou lourd prédominant,ce qui est attendu dans le cas d’un confinement dominant dans la direction perpendiculaire. Les grands facteurs g et le caractère unidimensionnel balistique sont des propriétés favorables à la réalisation de fermions de Majorana. Enfin, j’ai commencé à explorer le potentiel des hétérostructures à base de Ge pour la réalisation de dispositifs à points quantiques, en visant des applications en calcul quantique à base de spin. Au cours des derniers mois, j’ai pu observer des signes évidents de transport à un seul trou, posant ainsi les bases pour des études plus approfondies sur les points quantiques des trous. / Aiming towards largely integrated quantum bits (qubits) requires thedevelopment of solid-state, two-level quantum systems, such as spins inquantum dots or Majorana fermions in one-dimensional wires. Holes confinedin low-dimensional, germanium-based heterostructures are good candidatesfor such qubits because they offer i) large spin-orbit interaction(SOI), leading to conveniently large g factors, ii) reduced hyperfine coupling,which is important for long spin coherence, and iii) relatively loweffective masses, favoring quantum confinement. In this thesis, I have investigatedhole transport in one- and two-dimensional systems made fromcompressively strained Ge/Si_0.2Ge_0.8 heterostructures. An important partof my research work has been devoted to developing the recipes for devicefabrication. I have started from the fabrication of gated Hall bardevices from nominally undoped Ge/SiGe heterostructures. I have studiedtwo types of the heterostructures embedding a strained Ge quantumwell: one where the Ge well is at the surface, hence easily accessible tometal contacts, and one where it is buried 70 nm below the surface, aconfiguration resulting in higher hole mobility. The electronic propertiesof the two-dimensional hole gas confined to the Ge well were studied bymeans of magneto-transport measurements down to 0.3 K. My measurementsrevealed a dominant heavy-hole character, which is expected fromthe presence of a compressive strain in combination with two-dimensionalconfinement. The surface-Ge devices showed diffusive transport and a weakanti-localization effect, which is due to SOI in combination with quantuminterference. The fact that the Ge quantum well is located at the surfaceallows for relatively large perpendicular electric fields and hence enhancedRashba-type SOI. I was able to estimate a spin splitting of around 1 meV.For the realization of quantum nano-devices, I used the heterostructure witha buried Ge well where the hole mobility approaches 2×105 cm2/Vs. Usinge-beam lithography, sub-micron metal gates were defined on sample surfacein order to create one-dimensional constrictions in the two-dimensional holegas. I succeeded in observing conductance quantization in hole quantum wires with a length up to ~ 600 nm. In these wires I investigated the Zeemansplitting of the one-dimensional subbands, finding large perpendicularg-factors as opposed to small in-plane g-factors. This strong anisotropyindicates a prevailing heavy-hole character, which is expected in the caseof a dominant confinement in the perpendicular direction. The large g factorsand the ballistic one-dimensional character are favorable properties forthe realization of Majorana fermions. Finally, I have begun to explore thepotential of Ge-based heterostructures for the realization of quantum-dotdevices, having in mind applications in spin-based quantum computing.During the last months, I was able to observe clear evidence of single-holetransport, laying the ground for more in-depth studies of hole quantumdots.

The tri-gate FET has been hailed as the biggest breakthrough in transistor technology in the last 20 years. The increase in device performance (faster switching, less delay, improved short channel effects, etc.) coupled with the reduction in device size, would allow for huge gains in the electronics industry. This thesis aims to not only investigate the validity of these claims, but also how random dopant fluctuation (RDF) affects the tri-gates performance and how to curb these issues. In order to achieve this, an atomistic 3-D device simulation program was utilized in order to capture the many quantum mechanical effects that devices of this size experience and compare the results against a similar planar device. We see the tri-gate FET does indeed perform extremely well compared to its planar counterpart, but both devices experience a great deal of fluctuations due to the random dopants in the device. In order to limit the RDF effects a variety of methods were implemented including increasing doping concentrations in the channel, source, and drain regions, varying the source/drain junction depths, and varying the source/drain contact workfunction. The results showed that increasing doping concentrations in order to reduce the amount of space the dopants had to diffuse did not reduce the randomness experienced by the devices, but rather the randomness increased. The dopant fluctuation was insensitive to the varying of the workfunction, but was found to decrease with an increase in junction depth in the source/drain regions. With randomness in the tri-gate reduced, the overall performance should increase when used in ICs, where consistency in device characteristics is essential.

Esta dissertação discute o desenvolvimento de modelos analíticos e numéricos para as características elétricas de transistores de fios quânticos. Sendo assim, realizou-se um estudo implementando uma sequência de formalismos e ferramentas computacionais para solução auto-consistente das equações de Schrödinger e Poisson para poços e fios quânticos. Com a utilização deste método numérico pode-se determinar os auto-estados os níveis de energias e as densidades eletrônicas de portadores livres, dentre outros parâmetros relevantes para dispositivos de fio quântico. Adicionalmente, realizou-se um estudo analítico das heteroestruturas semicondutoras de interesse para a área de dispositivos de dimensionalidade reduzida. Este estudo levou a obtenção de resultados referentes ao desenvolvimento de modelos teóricos para as características elétricas de dispositivos baseados no mecanismo de tunelamento ressonante. Os resultados obtidos para a característica corrente-tensão (I-V) nas heteroestruturas investigadas foram contrastados satisfatoriamente com os encontrados na literatura. Este ferramental analítico foi então aplicado para computar o coeficiente de transmissão eletrônico de um diodo de fio quântico com tunelamento ressonante. / This dissertation discusses the development of analytical and numerical models for the electrical characteristics of quantum wire transistors. A study is carried out, implementing a sequence of formalisms and computational tools for the self-consistent solution of the equations of Schrödinger and Poisson in quantum wells and quantum wires. By using this numerical formulation it is possible to determine the eigenstates, energy levels and free-carrier electronic density, among other relevant parameters for quantum wire devices. In addition, we also conducted an analytical study concerning semiconductor heetrostrucures of interest for reduced dimensionality devices applications. This study led to results regarding the development of theoretical models for the electrical characteristics of devices based on the resonant tunneling mechanism. The results obtained for the current-voltage (I-V) characteristics in the investigated heterostructures were satisfactorily compared to those available at the published literature and this analytical tool was then used to compute the electronic transmission coefficient in a resonant tunneling quantum wire diode.