Avec l’augmentation du nombre de cœurs, les problèmes de congestion sont commencé avec les interconnexions conventionnelles. Afin de remédier à ces défis, WiNoCoD projet (Wired RF Network-on-Chip Reconfigurable-on-Demand) a été initié par le financement de l’Agence Nationale de Recherche (ANR). Ce travail de thèse contribue à WiNoCoD projet. Une structure de contrôleur de RF est proposé pour l’interconnexion OFDMA de WiNoCoD et plusieurs algorithmes d’allocation de bande passante efficaces (distribués et centralisés) sont développés, concernant les demandes et contraintes très spécifiques de l’environnement sur-puce. Un protocole innovante pour l’arbitrage des sous-porteuses pour des longueurs bimodales de paquets sur-puce, qui ne nécessite aucun signalisation supplémentaire est introduit. Utilisation des ordres de modulation élevés avec plus grande consommation d’énergie est évaluée. / With rapidly increasing number of cores on a single chip, scalability problems have arised due to congestion and latency with conventional interconnects. In order to address these issues, WiNoCoD project (Wired RF Network-on-Chip Reconfigurable-on-Demand) has been initiated by the support of French National Research Agency (ANR). This thesis work contributes to WiNoCoD project. A special RF controller structure has been proposed for the OFDMA based wired RF interconnect of WiNoCoD. Based on this architecture, effective bandwidth allocation algorithms have been presented, concerning very specific requirements and constraints of on-chip environment. An innovative subcarrier allocation protocol for bimodal packet lengths of cache coherency traffic has been presented, which is proven to decrease average latency significantly. In addition to these, effective modulation order selection policies for this interconnect have been introduced, which seeks the optimal delay-power trade-off.

Os atuais sistemas eletrônicos desenvolvidos na forma de SoCs (Sistemas-sobre-Silício) são caracterizados pelo incremento de informação crítica que é capturada, armazenada e processada. Com a introdução dos SoCs nos sistemas distribuídos que promovem o compartilhamento dos recursos, a segurança vem se transformando num requisito de projeto extremamente importante. Os atuais SoCs são alvo de ataques. O desafio consiste em projetar um SoC seguro que satisfaça os requisitos de segurança e desempenho, próprios para cada aplicação. A estrutura de comunicação está se tornando o coração do SoC. Esta possui um impacto significativo no desempenho do sistema. A inclusão de serviços de segurança na estrutura de comunicação é vantajosa devido à sua capacidade de: 1) monitorar a informação transmitida; 2) detectar violações; 3) bloquear ataques; e 4) fornecer informações para diagnóstico e ativação de mecanismos de recuperação e defesa. O presente trabalho propõe a implementação do conceito de QoSS (Qualidade do Serviço de Segurança) no projeto da estrutura de comunicação baseada em redes intrachip (NoCs, Network-on-Chip). QoSS permite a inclusão da segurança como uma dimensão de QoS (Quality-of-Sevice), admitindo a existência de diferentes níveis de proteção. A adoção do QoSS no projeto das NoCs permite a exploração do espaço de projeto das NoCs levando em consideração o compromisso entre a segurança do sistema e o desempenho do sistema. A inclusão do QoSS na NoC é realizada através de uma metodologia que inclui 5 etapas: definição, descrição, implementação, avaliação e otimização. Como resultado é obtido um conjunto de NoCsQoSS que satisfazem os requisitos de segurança e desempenho do sistema. Criamos neste trabalho o ambiente de simulação APOLLO que fornece suporte na rápida exploração do espaço de soluções a partir de modelos SystemC-TLM do SoC. Neste trabalho, apresentamos três estudos de caso que utilizam a nossa metodologia de projeto de NoCs com QoSS na implementação de políticas de segurança estática e dinâmica. Os serviços de segurança de controle de acesso e autenticação foram implementados de duas formas: na interface da rede e no roteador. Realizamos a avaliação da eficácia e eficiência das NoCs resultantes sob diferentes condições de ataques e de tráfego, resultado da variação topológica do tráfego, natureza e tipo de tráfego. Mostramos que a implementação da segurança no roteador é mais eficiente que a implementação na interface da rede em termos de latência e potência sob todas as diferentes condições de tráfego. Porém, a utilização na interface permite a inclusão das características da segurança na NoC de uma maneira mais simples. Desta forma para sistemas complexos a implementação na interface é vantajosa. / As embedded electronic systems are pervading our lives, security is emerging as an extremely important design requirement. Due to the increasing complexity, intrinsic embedded constraints and strict requirements, security and performance are considered challenging tasks. Most of the current electronic systems embedded in a SoC (System-on-Chip) are used to capture, store, manipulate and access sensitive data and perform several critical functions without security guarantee. The challenge is to provide SoC security that allows a trustworthy system that meets the security and performance requirements. As security requirements vary dramatically for different applications, differentiated security services are necessary. The SoC communication structure is becoming the heart of the SoC. It has a significant impact on the overall system performance. The security services integration at the communication structure take advantage of its wide system visibility and critical role in enabling the system operation. It is able to: 1) monitor data transfer; 2) detect attacks; 3) block attacks; and 4) supply information for trigger suitable recovery mechanisms. This work proposes the implementation of the QoSS (Quality-of-Security-Service) concept at the NoC-based communication structure design. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. In contrast with previous works, the different security levels deployment allow a best trade-of the system security and performance requirements. The QoSS integration is carried out trough a 5 step methodology: definition, description, implementation, evaluation and optimization. As a result a set of NoCs-QoSS that satisfies the security and performance requirements are obtained. We use the framework APOLLO that integrates a set of tools, allowing the fast exploration of the huge NoC design space. In this work we present 2 study cases that uses our methodology in order to design a NoC-QoSS that supports static and a dynamic security policies and also satisfies the security and performance requirements. Two security services: Access Control and authentication are implemented at the NoC interface and at the NoC router. The final configurations are evaluated under different traffic and attack conditions. We show that the security implementation at the router is latency and power consumption efficient that the implementation at the network interface under all the traffic conditions. However, the security implementation at the network interface allows the integration of the security characteristics in a simpler way.

Os atuais sistemas eletrônicos desenvolvidos na forma de SoCs (Sistemas-sobre-Silício) são caracterizados pelo incremento de informação crítica que é capturada, armazenada e processada. Com a introdução dos SoCs nos sistemas distribuídos que promovem o compartilhamento dos recursos, a segurança vem se transformando num requisito de projeto extremamente importante. Os atuais SoCs são alvo de ataques. O desafio consiste em projetar um SoC seguro que satisfaça os requisitos de segurança e desempenho, próprios para cada aplicação. A estrutura de comunicação está se tornando o coração do SoC. Esta possui um impacto significativo no desempenho do sistema. A inclusão de serviços de segurança na estrutura de comunicação é vantajosa devido à sua capacidade de: 1) monitorar a informação transmitida; 2) detectar violações; 3) bloquear ataques; e 4) fornecer informações para diagnóstico e ativação de mecanismos de recuperação e defesa. O presente trabalho propõe a implementação do conceito de QoSS (Qualidade do Serviço de Segurança) no projeto da estrutura de comunicação baseada em redes intrachip (NoCs, Network-on-Chip). QoSS permite a inclusão da segurança como uma dimensão de QoS (Quality-of-Sevice), admitindo a existência de diferentes níveis de proteção. A adoção do QoSS no projeto das NoCs permite a exploração do espaço de projeto das NoCs levando em consideração o compromisso entre a segurança do sistema e o desempenho do sistema. A inclusão do QoSS na NoC é realizada através de uma metodologia que inclui 5 etapas: definição, descrição, implementação, avaliação e otimização. Como resultado é obtido um conjunto de NoCsQoSS que satisfazem os requisitos de segurança e desempenho do sistema. Criamos neste trabalho o ambiente de simulação APOLLO que fornece suporte na rápida exploração do espaço de soluções a partir de modelos SystemC-TLM do SoC. Neste trabalho, apresentamos três estudos de caso que utilizam a nossa metodologia de projeto de NoCs com QoSS na implementação de políticas de segurança estática e dinâmica. Os serviços de segurança de controle de acesso e autenticação foram implementados de duas formas: na interface da rede e no roteador. Realizamos a avaliação da eficácia e eficiência das NoCs resultantes sob diferentes condições de ataques e de tráfego, resultado da variação topológica do tráfego, natureza e tipo de tráfego. Mostramos que a implementação da segurança no roteador é mais eficiente que a implementação na interface da rede em termos de latência e potência sob todas as diferentes condições de tráfego. Porém, a utilização na interface permite a inclusão das características da segurança na NoC de uma maneira mais simples. Desta forma para sistemas complexos a implementação na interface é vantajosa. / As embedded electronic systems are pervading our lives, security is emerging as an extremely important design requirement. Due to the increasing complexity, intrinsic embedded constraints and strict requirements, security and performance are considered challenging tasks. Most of the current electronic systems embedded in a SoC (System-on-Chip) are used to capture, store, manipulate and access sensitive data and perform several critical functions without security guarantee. The challenge is to provide SoC security that allows a trustworthy system that meets the security and performance requirements. As security requirements vary dramatically for different applications, differentiated security services are necessary. The SoC communication structure is becoming the heart of the SoC. It has a significant impact on the overall system performance. The security services integration at the communication structure take advantage of its wide system visibility and critical role in enabling the system operation. It is able to: 1) monitor data transfer; 2) detect attacks; 3) block attacks; and 4) supply information for trigger suitable recovery mechanisms. This work proposes the implementation of the QoSS (Quality-of-Security-Service) concept at the NoC-based communication structure design. QoSS is a novel concept for data protection that introduces security as a dimension of QoS. In contrast with previous works, the different security levels deployment allow a best trade-of the system security and performance requirements. The QoSS integration is carried out trough a 5 step methodology: definition, description, implementation, evaluation and optimization. As a result a set of NoCs-QoSS that satisfies the security and performance requirements are obtained. We use the framework APOLLO that integrates a set of tools, allowing the fast exploration of the huge NoC design space. In this work we present 2 study cases that uses our methodology in order to design a NoC-QoSS that supports static and a dynamic security policies and also satisfies the security and performance requirements. Two security services: Access Control and authentication are implemented at the NoC interface and at the NoC router. The final configurations are evaluated under different traffic and attack conditions. We show that the security implementation at the router is latency and power consumption efficient that the implementation at the network interface under all the traffic conditions. However, the security implementation at the network interface allows the integration of the security characteristics in a simpler way.

O paradigma das redes em chip (NoCs) surgiu a fim de permitir alto grau de integração entre vários núcleos de sistemas em chip (SoCs), cuja comunicação é tradicionalmente baseada em barramentos. As NoCs são definidas como uma estrutura de switches e canais ponto a ponto que interconectam núcleos de propriedades intelectuais (IPs) de um SoC, provendo uma plataforma de comunicação entre os mesmos. As redes em chip sem fio (WiNoCs) são uma abordagem evolucionária do conceito de rede em chip (NoC), a qual possibilita a adoção dos mecanismos de roteamento das NoCs com o uso de tecnologias sem fio, propondo a otimização dos fluxos de tráfego, a redução de conectores e a atuação em conjunto com as NoCs tradicionais, reduzindo a carga nos barramentos. O uso do roteamento dinâmico dentro das redes em chip sem fio permite o desligamento seletivo de partes do hardware, o que reduz a energia consumida. Contudo, a escolha de onde empregar um link sem fio em uma NoC é uma tarefa complexa, dado que os nós são pontes de tráfego os quais não podem ser desligados sem potencialmente quebrar uma rota preestabelecida. Além de fornecer uma visão sobre as arquiteturas de NoCs e do estado da arte do paradigma emergente de WiNoC, este trabalho também propõe um método de avaliação baseado no já consolidado simulador ns-2, cujo objetivo é testar cenários híbridos de NoC e WiNoC. A partir desta abordagem é possível avaliar diferentes parâmetros das WiNoCs associados a aspectos de roteamento, aplicação e número de nós envolvidos em redes hierárquicas. Por meio da análise de tais simulações também é possível investigar qual estratégia de roteamento é mais recomendada para um determinado cenário de utilização, o que é relevante ao se escolher a disposição espacial dos nós em uma NoC. Os experimentos realizados são o estudo da dinâmica de funcionamento dos protocolos ad hoc de roteamento sem fio em uma topologia hierárquica de WiNoC, seguido da análise de tamanho da rede e dos padrões de tráfego na WiNoC. / The network on chip (NoC) paradigm was conceived in order to allow a high-level integration among several system-on-chip (SoC) cores whose communication is traditionally based on buses. NoCs are defined as a switch structure with communication channels, which interconnect SoC Intellectual Property cores allowing data transfer among them. Wireless networks on chip (Wi-NoC) are an evolutionary approach from the network on chip (NoC) concept, proposing the traffic flow optimization among different modules by providing wireless shortcuts over a traditional NoC, reducing the bus load. Using dynamic routing within the WiNoC enables selective hardware power management, reducing power consumption. However, choosing where to deploy a wireless link over a NoC is a complex task given that those nodes are gateways that cannot be turned off without potentially breaking an established route. Besides providing an overview of NoC architectures and about the emerging WiNoC paradigm, this work proposes a method to use well known ns-2 network simulator to test mixed NoC-WiNoC scenarios. With this approach it is possible to evaluate different WiNoC parameters associated to routing, application and total number of nodes in hierarchical topologies. Simulation study can also point-out which routing strategy is more suitable for a given scenario, what is considered important when choosing wireless node placement over a NoC.We performed experiments to understand the dynamics of wireless ad hoc routing protocol functioning in a WiNoC hierarchical topology, followed by an analysis of network size and traffic patterns over WiNoC.

Ces dernières années, les fournisseurs de cloud et les centres de données ont intégrés les FPGA dans leur environnement à des fins d'accélération. Cela est dû au fait que les accélérateurs à base de FPGA sont connus pour leur faible puissance et leurs bonnes performances par watt. En outre, l'introduction de la capacité de reconfiguration partielle dynamique (DPR) de certains FPGA incite les chercheurs de l'industrie et des universitaires à proposer des services de cloud FPGA virtualisés baser sur DPR. Dans la plupart des travaux existants, l'interconnexion entre les vFPGA repose soit sur les réseaux BUS ou OpenFlow. Cependant le bus et OpenFlow ne sont pas des solutions optimales pour la virtualisation.Dans cette thèse, nous avons proposé un NoC évolutif à l'exécution pour les accélérateurs basés sur FPGA virtualisés dans un cloud computing. Les composants NoC s'adapteront dynamiquement aux nombres d'accélérateurs virtualisés actifs en ajoutant et en supprimant des sous-noC. Pour minimiser la complexité de la conception de l'architecture NoC à un niveau inférieur (implémentation HDL), nous avons proposé un langage de modélisation unifié de haut niveau (UML) basé sur une ingénierie dirigée par les modèles. Une approche basée sur UML / MARTE et IP-XACT est utilisée pour définir les composants de la topologie NoC de haut niveau et générer les fichiers HDL requis. Les résultats des expériences montrent que le NoC évolutif à l'exécution peut réduire la consommation d'énergie de 17%. La caractérisation NoC sur la modélisation de haut niveau basée sur MDE réduit également le temps de conception de 25%. / In the last few years, cloud providers and data centers have been integrating FPGAs in their environment for acceleration purpose. This is due to the fact that FPGA based accelerator are known for their lower power and good performance per watt. Moreover, the introduction of the ability for dynamic partial reconfiguration (DPR) of some FPGAs trigger researchers in both industry and academics to propose DPR based virtualized FPGA (vFPGA) cloud services. In most of the existing works, the interconnection between the vFPGAs relies either on BUS or OpenFlow networks. However, both the bus and OpenFlow are not virtualization-aware and optimal solutions. In this thesis, we have proposed a virtualization-aware dynamically scalable NoC for virtualized FPGA accelerators in cloud computing. The NoC components will adapt to the number of active virtualized accelerator dynamically by adding and removing sub-NoCs. To minimize the complexity of NoC architecture design at a low level (HDL implementation), we have proposed a Model-Driven Engineering (MDE) based high-level unified modeling language (UML). A UML/MARTE and IP-XACT based approach are used to define the NoC Topology components at a high-level and generate the required HDL files. Experiment results show that the dynamically scalable NoC can reduce the power consumption by 17%. The MDE based high-level modeling based NoC characterization also reduce the design time by 25%.

Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.

Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared medium wired interconnects offering many practical applications in industry. Dynamic Voltage Frequency Scaling (DVFS) is a technique whereby a chip?s voltage-frequency levels are varied at run time, often used to conserve dynamic power. Various DVFSbased NoC optimization techniques have been proposed. However, due to the resources required to validate architectural decisions through prototyping, few are implemented. As a result, designers are faced with a lack of insight into potential power savings or performance gains at early architecture stages. This thesis proposes a DVFS aware NoC simulator with support for per node power-frequency modeling to allow fine-tuning of such optimization techniques early on in the design cycle. The proposed simulator also provides a framework for benchmarking various candidate strategies to allow selective prototyping and optimization. As part of the research, DVFS extensions were built for an existing NoC performance simulator and released for public use. This thesis presents some of the preliminary results from our simulator that show the average power consumed per node for all the benchmarks in SPLASH 2 benchmark suite [74] to be quite similar to each other. This thesis also serves as a technical manual for the simulator extensions. Important links for downloading and using the simulator are provided at the end of this document in Appendix C.

<p>Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.</p>

<p>During the past years has the Nostrum Network on Chip <i>(NoC)</i> been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties <i>(IP) </i>on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.</p><p>Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.</p><p>Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce</p><p>the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called<i> Data Motorways</i> achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in</p><p>hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.</p><p>This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways</p><p>can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.</p>

Made available in DSpace on 2014-12-17T15:48:02Z (GMT). No. of bitstreams: 1 TadeuFO_DISSERT.pdf: 1305505 bytes, checksum: 419b87148f7490aba343231bb89f4d72 (MD5) Previous issue date: 2010-08-09 / The increasingly request for processing power during last years has pushed integrated circuit industry to look for ways of providing even more processing power with less heat dissipation, power consumption, and chip area. This goal has been achieved increasing the circuit clock, but since there are physical limits of this approach a new solution emerged as the multiprocessor system on chip (MPSoC). This approach demands new tools and basic software infrastructure to take advantage of the inherent parallelism of these architectures. The oil exploration industry has one of its firsts activities the project decision on exploring oil fields, those decisions are aided by reservoir simulations demanding high processing power, the MPSoC may offer greater performance if its parallelism can be well used. This work presents a proposal of a micro-kernel operating system and auxiliary libraries aimed to the STORM MPSoC platform analyzing its influence on the problem of reservoir simulation / O aumento da demanda por poder de processamento nos ?ltimos anos for?ou a ind?stria de circuitos integrados a buscar formas de prover maior poder de processamento com menor dissipa??o de calor, menor consumo de pot?ncia e ?rea em chip. Isso vinha sendo feito com o aumento do clock dos circuitos. Por?m, com a proximidade dos limites f?sicos dessa abordagem, surgem como solu??o alternativa as arquiteturas com m?ltiplos processadores em um ?nico chip: os MPSoC (Multi-Processor System on a Chip). Essa abordagem exige que novas ferramentas e novos softwares sejam desenvolvidos buscando aproveitar ao m?ximo o aspecto paralelo destas arquiteturas. A ind?stria de explora??o de petr?leo tem como uma de suas atividades iniciais a decis?o de projetos de explora??o de campos de petr?leo. Essas decis?es s?o tomadas baseando-se em simula??es computacionalmente intensivas, situa??o em que os MPSoCs podem oferecer aumento de performance atrav?s de paralelismo. Este trabalho apresenta a proposta de implementa??o de um micro-kernel de sistema operacional e bibliotecas auxiliares para a plataforma MPSoC STORM analisando a influ?ncia na simula??o de reservat?rios