O projeto de sistemas eletrônicos atuais segue o paradigma do reuso de componentes de hardware. Este paradigma reduz a complexidade do projeto de um chip, mas cria novos desafios para o projetista do sistema em relação ao teste do produto final. O acesso aos núcleos profundamente embutidos no sistema, a integração dos diversos métodos de teste e a otimização dos diversos fatores de custo do sistema são alguns dos problemas que precisam ser resolvidos durante o planejamento do teste de produção do novo circuito. Neste contexto, esta tese propõe duas abordagens para o planejamento de teste de sistemas integrados. As abordagens propostas têm como principal objetivo a redução dos custos de teste através do reuso dos recursos de hardware disponíveis no sistema e da integração do planejamento de teste no fluxo de projeto do circuito. A primeira abordagem considera os sistemas cujos componentes se comunicam através de conexões dedicadas ou barramentos funcionais. O método proposto consiste na definição de um mecanismo de acesso aos componentes do circuito e de um algoritmo para exploração do espaço de projeto. O mecanismo de acesso prevê o reuso das conexões funcionais, o uso de barramentos de teste locais, núcleos transparentes e outros modos de passagem do sinal de teste. O algoritmo de escalonamento de teste é definido juntamente com o mecanismo de acesso, de forma que diferentes combinações de custos sejam exploradas. Além disso, restrições de consumo de potência do sistema podem ser consideradas durante o escalonamento dos testes. Os resultados experimentais apresentados para este método mostram claramente a variedade de soluções que podem ser exploradas e a efi- ciência desta abordagem na otimização do teste de um sistema complexo. A segunda abordagem de planejamento de teste propõe o reuso de redes em-chip como mecanismo de acesso aos componentes dos sistemas construídos sobre esta plataforma de comunicação. Um algoritmo de escalonamento de teste que considera as restrições de potência da aplicação é apresentado e a estratégia de teste é avaliada para diferentes configurações do sistema. Os resultados experimentais mostram que a capacidade de paralelização da rede em-chip pode ser explorada para reduzir o tempo de teste do sistema, enquanto os custos de área e pinos de teste são drasticamente minimizados. Neste manuscrito, os principais problemas relacionados ao teste dos sistemas integrados baseados em componentes virtuais são identificados e as soluções já apresentadas na literatura são discutidas. Em seguida, os problemas tratados por este traballho são listados e as abordagens propostas são detalhadas. Ambas as técnicas são validadas através dos sistemas disponíveis no ITC’02 SoC Test Benchmarks. As técnicas propostas são ainda comparadas com outras abordagens de teste apresentadas recentemente. Esta comparação confirma a eficácia dos métodos desenvolvidos nesta tese. / Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

Un équipement portable moderne intègre plusieurs capteurs d'image qui peuvent être de différents types. On peut citer en guise d'exemple un capteur couleur, un capteur infrarouge ou un capteur basse lumière. Cet équipement doit alors supporter différentes sources qui peuvent être hétérogènes en terme de résolution, de granularité de pixels et de fréquence d'émission des images. Cette tendance à multiplier les capteurs, est motivée par des besoins applicatifs dans un but de complémentarité en sensibilité (fusion des images), en position (panoramique) ou en champ de vision. Le système doit par conséquent être capable de supporter des applications de plus en plus complexes et variées, nécessitant d'utiliser une seule ou plusieurs sources d'image. Du fait de cette variété de fonctionnalités embarquées, le système électronique doit pouvoir s'adapter constamment pour garantir des performances en terme de latence et de temps de traitement en fonction des applications, tout en respectant des contraintes d'encombrement.% Même si depuis de nombreuses années, un grand nombre de solutions architecturales ont été proposées pour améliorer l'adaptabilité des unités de calcul, un problème majeur persiste au niveau du réseau d'interconnexion qui n'est pas suffisamment adaptable, en particulier pour le transfert des flux de pixels et l'accès aux données. Nous proposons dans cette thèse un nouveau réseau de communication sur puce (NoC) pour un SoC dédié à la vision. Ce réseau permet de gérer dynamiquement différents types de flux en parallèle en auto-adaptant le chemin de donnée entre les unités de calcul, afin d'exécuter de manière efficace différentes applications. La proposition d'une nouvelle structure de paquets de données, facilite les mécanismes d'adaptation du système grâce à la combinaison d'instructions et de données à traiter dans un même paquet. Nous proposons également un système de mémorisation de trames à adressage indirecte, capable de gérer dynamiquement plusieurs trames image de différentes sources d'image. Cet adressage indirect est réalisé par l'intermédiaire d'une couche d'abstraction matérielle qui se charge de traduire des requêtes de lecture et d'écriture, réalisées suivant des indicateurs de la trame requise (source de l'image, indice temporel et dernière opération effectuée). Afin de valider notre proposition, nous définissons une nouvelle architecture, appelée Multi Data Flow Ring (MDFR) basée sur notre réseau avec une topologie en anneau. Les performances de cette architecture, en temps et en surface, ont été évaluées dans le cadre d'une implémentation sur une cible FPGA / Modern portable vision systems include several types of image sensors such as colour, low-light or infrared sensor. Such system has to support heterogeneous image sources with different spatial resolutions, pixel granularities and working frequencies. This trend to multiply sensors is motivated by needs to complete sensor sensibilities with image fusion processing techniques, or sensor positions in the system. Moreover, portable vision systems implement image applications which require several images sources with a growing computing complexity. To face those challenges in integrating such a variety of functionalities, the embedded electronic computing system has to adapt permanently to preserve application timing performance in latency and processing, and to respect area and low-power constraints. In this thesis, we propose a new Network-On-Chip (NoC) adapted for a System-On-Chip (SoC) dedicated to image applications. This NoC can manage several pixel streams in parallel by adapting dynamically the datapatah between processing elements and memories. The new header packet structure enables adaptation mechanisms in routers by combining instructions and data in a same packet. To manage efficiently the frames storage required for an application, we propose a frame buffer system with an indirect frame addressing, which is able to manage several frames from different sensors. It features a hardware abstraction layer which is in charge to collect reading and writing requests, according to specific frame indicators such as the image source ID. The NoC has been validated in a complete processing architecture called Multi Data Flow Ring (MDFR) with a ring topology. The MDFR performances in time and area has been demonstrated for an FPGA target

Due to increased complexity of today’s computer systems, which are manufactured in recent semiconductor technologies, and the fact that recent semiconductor technologies are more liable to soft errors (non-permanent errors) it is inherently difficult to ensure that the systems are and will remain error-free. Depending on the application, a soft error can have serious consequences for the system. It is therefore important to detect the presence of soft errors as early as possible and recover from the erroneous state and maintain correct operation. There is an entire research area devoted on proposing, implementing and analyzing techniques that can detect and recover from these errors, known as fault tolerance. The drawback of using faulttolerance is that it usually introduces some overhead. This overhead may be for instance redundant hardware, which increases the cost of the system, or it may be a time overhead that negatively impacts on system performance. Thus a main concern when applying fault tolerance is to minimize the imposed overhead while the system is still able to deliver the correct error-free operation. In this thesis we have analyzed one well known fault tolerant technique, Rollback-Recovery with Checkpointing (RRC). This technique is able to detect and recover from errors by taking and storing checkpoints during the execution of a job.Therefore we can think as if a job is divided into a number of execution segments and a checkpoint is taken after executing each execution segment. This technique requires the job to be concurrently executed on two processors. At each checkpoint, both processors exchange data, which contains enough information for the job’s state. The exchanged data are then compared. If the data differ, it means that an error is detected in the previous execution segment and it is therefore re-executed. If the exchanged data are the same, it means that no errors are detected and the data are stored as a safe point from which the job can be restarted later. A time overhead due to exchanging data between processors is therefore introduced, and it increases the average execution time of a job, i.e. the average time required for a given job to complete. The overhead depends on the number of links that has to be traversed (due to data exchange) after each execution segment and the number of execution segments that are needed for the given job. The number of links that has to be traversed after each execution segment is twice the distance between the processors that are executing the same job concurrently. However, this is only true if all the links are fully functional. A link failure can result in a longer route for communication between the processors. Even though all links arefully functional, the number of execution segments still depends on error-free probabilities of the processors, and these error-free probabilities can vary between processors. This implies that the choice of processors affects the total number of links the communication has to traverse. Choosing two processors with higher error-free probability further away from eachother increases the distance, but decreases the number of execution segments, which can result in a lower overhead. By carefully determining the mapping for a given job, one can decrease the overhead, hence decreasing the average execution time. Since it is very common to have a larger number of jobs than available resources, it is not only important to find a good mapping to decrease the average execution time for a whole system, but also a good order of execution for a given set jobs (scheduling of the jobs). We propose in this thesis several mapping and scheduling algorithms that aim to reduce the average execution time in a fault-tolerant multiprocessor System-on-Chip, which uses Network-on-Chip as an underlying interconnect architecture, so that the fault-tolerant technique (RRC) can perform efficiently.

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O paradigma das redes em chip (NoCs) surgiu a fim de permitir alto grau de integração entre vários núcleos de sistemas em chip (SoCs), cuja comunicação é tradicionalmente baseada em barramentos. As NoCs são definidas como uma estrutura de switches e canais ponto a ponto que interconectam núcleos de propriedades intelectuais (IPs) de um SoC, provendo uma plataforma de comunicação entre os mesmos. As redes em chip sem fio (WiNoCs) são uma abordagem evolucionária do conceito de rede em chip (NoC), a qual possibilita a adoção dos mecanismos de roteamento das NoCs com o uso de tecnologias sem fio, propondo a otimização dos fluxos de tráfego, a redução de conectores e a atuação em conjunto com as NoCs tradicionais, reduzindo a carga nos barramentos. O uso do roteamento dinâmico dentro das redes em chip sem fio permite o desligamento seletivo de partes do hardware, o que reduz a energia consumida. Contudo, a escolha de onde empregar um link sem fio em uma NoC é uma tarefa complexa, dado que os nós são pontes de tráfego os quais não podem ser desligados sem potencialmente quebrar uma rota preestabelecida. Além de fornecer uma visão sobre as arquiteturas de NoCs e do estado da arte do paradigma emergente de WiNoC, este trabalho também propõe um método de avaliação baseado no já consolidado simulador ns-2, cujo objetivo é testar cenários híbridos de NoC e WiNoC. A partir desta abordagem é possível avaliar diferentes parâmetros das WiNoCs associados a aspectos de roteamento, aplicação e número de nós envolvidos em redes hierárquicas. Por meio da análise de tais simulações também é possível investigar qual estratégia de roteamento é mais recomendada para um determinado cenário de utilização, o que é relevante ao se escolher a disposição espacial dos nós em uma NoC. Os experimentos realizados são o estudo da dinâmica de funcionamento dos protocolos ad hoc de roteamento sem fio em uma topologia hierárquica de WiNoC, seguido da análise de tamanho da rede e dos padrões de tráfego na WiNoC. / The network on chip (NoC) paradigm was conceived in order to allow a high-level integration among several system-on-chip (SoC) cores whose communication is traditionally based on buses. NoCs are defined as a switch structure with communication channels, which interconnect SoC Intellectual Property cores allowing data transfer among them. Wireless networks on chip (Wi-NoC) are an evolutionary approach from the network on chip (NoC) concept, proposing the traffic flow optimization among different modules by providing wireless shortcuts over a traditional NoC, reducing the bus load. Using dynamic routing within the WiNoC enables selective hardware power management, reducing power consumption. However, choosing where to deploy a wireless link over a NoC is a complex task given that those nodes are gateways that cannot be turned off without potentially breaking an established route. Besides providing an overview of NoC architectures and about the emerging WiNoC paradigm, this work proposes a method to use well known ns-2 network simulator to test mixed NoC-WiNoC scenarios. With this approach it is possible to evaluate different WiNoC parameters associated to routing, application and total number of nodes in hierarchical topologies. Simulation study can also point-out which routing strategy is more suitable for a given scenario, what is considered important when choosing wireless node placement over a NoC.We performed experiments to understand the dynamics of wireless ad hoc routing protocol functioning in a WiNoC hierarchical topology, followed by an analysis of network size and traffic patterns over WiNoC.