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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
121

ON THE RATE-COST TRADEOFF OF GAUSSIAN LINEAR CONTROL SYSTEMS WITH RANDOM COMMUNICATION DELAY

Jia Zhang (13176651) 01 August 2022 (has links)
<p>    </p> <p>This thesis studies networked Gaussian linear control systems with random delays. Networked control systems is a popular topic these years because of their versatile applications in daily life, such as smart grid and unmanned vehicles. With the development of these systems, researchers have explored this area in two directions. The first one is to derive the inherent rate-cost relationship in the systems, that is the minimal transmission rate needed to achieve an arbitrarily given stability requirement. The other one is to design achievability schemes, which aim at using as less as transmission rate to achieve an arbitrarily given stability requirement. In this thesis, we explore both directions. We assume the sensor-to-controller channels experience independently and identically distributed random delays of bounded support. Our work separates into two parts. In the first part, we consider networked systems with only one sensor. We focus on deriving a lower bound, R_{LB}(D), of the rate-cost tradeoff with the cost function to be E{| <strong>x^</strong>T<strong>x </strong>|} ≤ D, where <strong>x </strong>refers to the state to be controlled. We also propose an achievability scheme as an upper bound, R_{UB}(D), of the optimal rate-cost tradeoff. The scheme uses lattice quantization, entropy encoder, and certainty-equivalence controller. It achieves a good performance that roughly requires 2 bits per time slot more than R_{LB}(D) to achieve the same stability level. We also generalize the cost function to be of both the state and the control actions. For the joint state-and-control cost, we propose the minimal cost a system can achieve. The second part focuses on to the covariance-based fusion scheme design for systems with multiple > 1 sensors. We notice that in the multi-sensor scenario, the outdated arrivals at the controller, which many existing fusion schemes often discard, carry additional information. Therefore, we design an implementable fusion scheme (CQE) which is the MMSE estimator using both the freshest and outdated information at the controller. Our experiment demonstrates that CQE out-performances the MMSE estimator using the freshest information (LQE) exclusively by achieving a 15% smaller average L2 norm using the same transmission rate. As a benchmark, we also derive the minimal achievable L2 norm, Dmin, for the multi-sensor systems. The simulation shows that CQE approaches Dmin significantly better than LQE. </p>
122

Digital control strategies for DC/DC SEPIC converters towards integration / Stratégies de commande numérique pour un convertisseur DC/DC SEPIC en vue de l’intégration

Li, Nan 29 May 2012 (has links)
L’utilisation des alimentations à découpage (SMPSs : switched mode power supplies) est à présent largement répandue dans des systèmes embarqués en raison de leur rendement. Les exigences technologiques de ces systèmes nécessitent simultanément une très bonne régulation de tension et une forte compacité des composants. SEPIC (Single-Ended Primary Inductor Converter) est un convertisseur à découpage DC/DC qui possède plusieurs avantages par rapport à d’autres convertisseurs de structure classique. Du fait de son ordre élevé et de sa forte non linéarité, il reste encore peu exploité. L’objectif de ce travail est d’une part le développement des stratégies de commande performantes pour un convertisseur SEPIC et d’autre part l’implémentation efficace des algorithmes de commande développés pour des applications embarquées (FPGA, ASIC) où les contraintes de surface silicium et le facteur de réduction des pertes sont importantes. Pour ce faire, deux commandes non linéaires et deux observateurs augmentés (observateurs d’état et de charge) sont exploités : une commande et un observateur fondés sur le principe de mode de glissement, une commande prédictive et un observateur de Kalman étendu. L’implémentation des deux lois de commande et l’observateur de Kalman étendu sont implémentés sur FPGA. Une modulation de largeur d’impulsion (MLI) numérique à 11-bit de résolution a été développée en associant une technique de modulation Δ-Σ de 4-bit, un DCM (Digital Clock Management) segmenté et déphasé de 4-bit, et un compteur-comparateur de 3-bit. L’ensemble des approches proposées sont validées expérimentalement et constitue une bonne base pour l’intégration des convertisseurs à découpage dans les alimentations embarquées. / The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

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