The temperature sensor design discussed in this thesis, is meant mainly to monitor temperature at power outlets. Current variations in power cords have a direct impact on the surrounding temperature. Sensing these variations ,enables us to take necessary measures to prevent any hazards due to temperature rise. Thus, for this application we require a sensor with a moderate temperature error (_10C) over a sensing range of -200C to 1500C. Low power consumption and simple digitizing scheme alleviate measurement errors due to self heating effects of the sensor. A current starved inverter based ring oscillator was chosen for the sensor design in 130nm technology. The inverter delay variation with temperature is used for sensing. Linearity and process invariancy of these characteristics are fundamental to the sensor design. We observed through simulations, and confirmed by mathematical analysis, that the sensing characteristics are governed by bias current dependence on temperature. Control voltage for the bias circuitry of the oscillator determines current through the inverter stages. Hence, for linear sensing characteristics, a control voltage(Vc) just above the maximum threshold voltage of bias transistor is used. This enables generation of PTAT saturation current for current starved inverters, due to dominance of threshold voltage decrease with temperature over mobility decrease. I.Another limitation, process dependency of the sensing characteristics, was overcome through the proposed calibration based compensation technique. A changing Vc proportional to threshold voltage variation with process, process independent bias current and current temperature characteristics were obtained. This compensated for the process variation effects on frequency. Thus, a variable Vc was generated using a reference with low temperature sensitivity of 17.6_V=0C, and resistive divider combinations for various processes. Incorporating this compensation technique we achieved good linearity in sensor characteristics and a maximum temperature error of± 1.60C over the sensing range. The sensor consumes a low power of 0.29mW and also occupies minimal area.

The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

This thesis introduces, for the first time, a novel 4-bit, metal-oxide-metal (MOM) digital capacitor switching array (MOMDCSA) which has been implemented into a wideband CMOS voltage controlled oscillator (VCO) for 5 GHz WiMAX/WLAN applications. The proposed MOMDCSA is added both in series and parallel to nMOS varactors. For further gain linearity, a wider tuning range and minor phase noise variations, this varactor bank is connected in parallel to four nMOS varactor pairs, each of which is biased at a different voltage. Thus, VCO tuning gain reduces and optimal phase noise variation is obtained across a wide range of frequencies. Based on this premise, a wideband VCO is achieved with low phase noise variation of less than 4.7 dBc/Hz. The proposed VCO has been designed using UMC 130 nm CMOS technology. It operates from 3.45 GHz to 6.23 GHz, with a phase noise of -133.80 dBc/Hz at a 1 MHz offset, a figure of merit (FoM) of -203.5 dBc/Hz. A novel microstrip low-phase noise oscillator is based on a left-handed (LH) metamaterial bandpass filter which is embedded in the feedback loop of the oscillator. The oscillator is designed at a complex quality factor Qsc peak frequency, to achieve excellent phase noise performance. At a centre frequency of 2.05 GHz, the reported oscillator demonstrates, experimentally, a phase noise of -126.7 dBc/Hz at a 100 kHz frequency offset and a FoM of -207.2 dBc/Hz at a 1 MHz frequency offset. The increasing demands have been placed on the electromagnetic compatibility performance of VCO devices is crucial. Therefore, this thesis extends the potential of highly flexible and conductive graphene laminate to the application of electromagnetic interference (EMI) shielding. Graphene nanoflake-based conductive ink is printed on paper, and then it is compressed to form graphene laminate with a conductivity of 0.43×105 S/m. Shielding effectiveness is experimentally measured at above 32 dB as being between 12GHz and 18GHz, even though the thickness of the graphene laminate is only 7.7µm. This result demonstrates that graphene has great potential for offering lightweight, low-cost, flexible and environmentally friendly shielding materials which can be extended to offering required shielding from electromagnetic interference (EMI), not only for VCO phase noise optimisation, but also for sensitive electronic devices.

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No description available.

K-Band (18 to 26 GHz) dielectric resonator oscillators are typically used as a local oscillator in most K-Band digital transmitter/receiver topologies. Traditionally, the oscillator itself is made up of an active device, a dielectric resonator termination network, and a passive load matching network. The termination network embodies a cylindrical high permittivity dielectric resonator that is coupled on the same plane as a current carrying transmission line. This configuration provides an adequate resonance needed for oscillation but has some limitations. In order to provide a high Q resonance the entire oscillator is placed in a metal box to prevent radiation losses. This increases the overall size of the device and makes it difficult to integrate in smaller transceiver topologies. Secondly, a tuning screw is required to help excite the dominant mode of the resonator to achieve the high Q response. This can cause problems in precision due to the mechanical jitter of the screw inherent in mobile devices. By embedding this resonator inside the substrate it is possible to realize a very high Q resonance at a desired frequency and remove the need for a metal cavity and tuning screw. An additional advantage can be seen in terms of overall size reduction of the oscillator circuit. To demonstrate the feasibility of utilizing a dielectric resonator embedded within a substrate, a K-Band oscillator proof of concept has been designed, fabricated, and tested. The oscillator is comprised of a low noise active transistor device, an embedded k-band dielectric resonator and a passive transmission line load network. All elements within the oscillator are optimized to produce a steady oscillation near 20 GHz. Preliminary investigations of a microstrip resonator S-band (2-3 GHz) oscillator are first discussed. Secondly, various challenges in design and fabrication are discussed. Thereafter, simulated and measured results of the embedded DRO structure are presented. Emphasis is placed on output oscillation power and low phase noise. With further development, the entire oscillator can be embedded within the substrate leaving only the active device on the surface. This allows for a considerable reduction in material cost and simple integration with miniaturized digital transmitter/receiver devices.

No description available.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / M/A-COM, Inc. has developed a miniature Tactical Telemetry Module (TTM) for medium power (500 mW and 1 W) telemetry applications. The TTM demonstrates system integration of a multi-channel PCM encoder, lower S-band transmitter, and power regulation onto a single printed wiring board (PWB). The module is smaller than a standard business card and utilizes both COTS and M/A-COM proprietary technologies. The PCM encoder is designed for eight (8) analog inputs, eight (8) discrete inputs, and one (1) synchronous RS-422 serial interface. Data rates of 300 kbps to 6 Mbps are supported. The module incorporates a frequency programmable, phase-locked FM S-band transmitter. The transmitter utilizes M/A-COM’s new dual port VCO and high efficiency 500 mW and 1 W power amplifier MMIC’s. Additionally, switching power regulation circuits were implemented within the module to provide maximum operating efficiency. This paper reviews the design and manufacturing of the Tactical Telemetry Module (TTM) and its major components, and presents system performance data.