Peptidoglycan, the major component of the bacterial cell wall, is essential for cell viability. Several important antibiotics disrupt peptidoglycan metabolism, including the β-lactams and vancomycin. There are several bacterial enzymes involved in peptidoglycan metabolism that are not yet the target of antibiotics, such as the lytic transglycosylases (LTs). Relatively little experimental characterization has been done on LTs, due largely to the difficulties of working with insoluble, heterogeneous, and highly variable peptidoglycan. This research develops a method for the generation of a soluble, homogeneous oligosaccharide substrate that can be used to study LTs. The approach taken was based on the enzymatic degradation of peptidoglycan into fragments of a specific nature, and their separation by HPLC. This work identifies the challenges associated with this approach, and discusses the potential flaws in the 'top-down' generation of a soluble substrate. / This thesis was typeset with LaTeX using Minion Pro and Myriad Pro typefaces.

Wire bonding is the process of creating interconnects between the circuitry on a microchip and PCB boards or substrates so that the microchip can interact with the outside world. The materials and techniques used in this bonding process can cause a wide variation in bond quality, so wire bond reliability testing is very important in determining the quality and longevity of wire bonds. Due to the fact that microchips are encased in protective resins after bonding and their substrates attached to the larger device as a whole, once any single wire bond fails then it could jeapordize the entire device as the wire bonds cannot be individually replaced or fixed. Current methods of reliability testing are lengthy and often destroy the entire sample in the process of evaluation, so the availability of novel non-destructive, real-time monitoring methods as well as accelerated aging could reduce costs and provide realistically timed tests of novel wire bond materials which do not form Intermetallic compounds (IMCs) as rapidly as Au wire on Al substrates. In this thesis, five new chip designs for use in wire bond reliability testing are reported, focusing on the first joint made in a wire bond, called the ball bond. These chips are scaled either to test up to 55 test bonds simultaneously or just one at a time, introducing different requirements for microchip infrastructure capabilities, such as on-chip sensing/data bus, multiplexer, and switches able to operate under High Temperature Storage (HTS) which ranges from temperatures of 150-220 ??C. There are different heating requirements for each of these microchips, needing to be heated externally or containing on-chip microheaters to heat only the ball bond under test, and not the rest of the microchip or surrounding I/O pads. Of the five chip designs, sample chips were produced by an external company. Experimental studies were then carried out with two of these chip designs. They were specifically made to test novel methods of determining ball bond reliability using in-situ, non-destructive sensing, in real-time, while the ball bond undergoes thermal aging. Pad resistance as an analysis tool for ball bond reliability is proposed in this thesis as a new way of evaluating ball bond quality and allows for the testing of electrical connection without the need for specialized measurement probes or difficult bonding processes that contact resistance measurements require. Results are reported for pad resistance measurements of a ball bond under very high temperature storage (VHTS) at 250 ??C, a temperature exceeding typical HTS ranges to accelerate aging. Pad resistance measurements are taken using the four-wire measurement method from each corner of the bond pad, while reversing current direction every measurement to remove thermo-electric effects, and then calculating the average square resistance of the pad from this value. The test ball bond is aged using a novel on-chip microheater which is a N+ doped Si resistive heater located directly underneath the bond pad, and can achieve temperatures up to 300 ??C while not aging any of the I/O pads surrounding it, which are located ~180 ??m away. A 50 ??? resistor is placed 60 ??m away from the heater to monitor the temperature. The use of a microheater allows the aging of novel wire types at temperatures much higher than those permitted for microchip operation while thermally isolating the test bond from the sensing and power bonds, which do not need to be aged. Higher temperatures allow the aging process to be sped up considerably. The microheater is programmatically cycled between 250 ??C (for 45 min) and 25 ??C (for 15 min) for up to 200 h or until the pad resistance measurements fail due breakdown of the bonding pad. Intermetallic compounds forming between the ball bond and the pad first become visible after a few hours, and then the pad becomes almost completely consumed after a day. The pad resistance is measured every few seconds while the sample is at room temperature, and the increase in pad resistance agrees with the fact that Au/Al IMC products are known to have much higher resistance than both pure Au or Al. Also discussed are some aging results of Au wires and Pd coated Cu (PCC) wires bonded to Al bonding pads and aged at a temperature of 200 ??C in an oven for 670 h. The oven aged Au ball bonds also saw IMC formation on the surface of the bonding pad, much like the microheater tests. The PCC ball bonds became heavily oxidized due to lack of Pd on the surface of the ball, the wire portions did not oxidize much. In conclusion, the new structures have been demonstrated to age ball bonds faster than with conventional methods while obtaining non-destructive data. Specifically, the new microheater ages a test bond at an accelerated rate without having an observable effect on the I/O connections used to monitor the test bond. Pad resistance measurements correlate to the aging of the test bond and ensure the electrical integrity of the joint is checked.

Scratch-pad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embedded systems. Compared to hardware-managed cache, SPM can be more efficient in performance, power and area cost, and has the added advantage of better time predictability. In this thesis, SPMs should be seen in a general context. For example, in stream processors, a software-managed stream register file is usually used to stage data to and from off-chip memory. In IBM's Cell architecture, each co-processor has a software-managed local store for keeping data and instructions. SPM management is critical for SPM-based embedded systems. In this thesis, we propose two novel methodologies, the memory colouring methodology and the perfect colouring methodology, to place the static data aggregates such as arrays and structs of a program in SPM. Our methodologies are dynamic in the sense that some data aggregates can be swapped into and out of SPM during program execution. To this end, a live range splitting heuristic is introduced in order to create potential data transfer statements between SPM and off-chip memory. The memory colouring methodology is a general-purpose compiler approach. The novelty of this approach lies in partitioning an SPM into a pseudo register file then generalising existing graph colouring algorithms for register allocation to colour data aggregates. In this thesis, a scheme for partitioning an SPM into a pseudo register file is introduced. This methodology is inter-procedural and therefore operates on the interference graph for the data aggregates in the whole program. Different graph colouring algorithms may give rise to different results due to live range splitting and spilling heuristics used. As a result, two representative graph colouring algorithms, George and Appel's iterative-coalescing and Park and Moon's optimistic-coalescing, are generalised and evaluated for SPM allocation. Like memory colouring, perfect colouring is also inter-procedural. The novelty of this second methodology lies in formulating the SPM allocation problem as an interval colouring problem. The interval colouring problem is an NP problem and no widely-accepted approximation algorithms exist. The key observation is that the interference graphs for data aggregates in many embedded applications form a special class of superperfect graphs. This has led to the development of two additional SPM allocation algorithms. While differing in whether live range splits and spills are done sequentially or together, both algorithms place data aggregates in SPM based on the cliques in an interference graph. In both cases, we guarantee optimally that all data aggregates in an interference graph can be placed in SPM if the given SPM size is no smaller than the chromatic number of the graph. We have developed two memory colouring algorithms and two perfect colouring algorithms for SPM allocation. We have evaluated them using a set of embedded applications. Our results show that both methodologies are efficient and effective in handling large-scale embedded applications. While neither methodology outperforms the other consistently, perfect colouring has yielded better overall results in the set of benchmarks used in our experiments. All these algorithms are expected to be valuable. For example, they can be made available as part of the same compiler framework to assist the embedded designer with exploring a large number of optimisation opportunities for a particular embedded application.

Scratch-pad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embedded systems. Compared to hardware-managed cache, SPM can be more efficient in performance, power and area cost, and has the added advantage of better time predictability. In this thesis, SPMs should be seen in a general context. For example, in stream processors, a software-managed stream register file is usually used to stage data to and from off-chip memory. In IBM's Cell architecture, each co-processor has a software-managed local store for keeping data and instructions. SPM management is critical for SPM-based embedded systems. In this thesis, we propose two novel methodologies, the memory colouring methodology and the perfect colouring methodology, to place the static data aggregates such as arrays and structs of a program in SPM. Our methodologies are dynamic in the sense that some data aggregates can be swapped into and out of SPM during program execution. To this end, a live range splitting heuristic is introduced in order to create potential data transfer statements between SPM and off-chip memory. The memory colouring methodology is a general-purpose compiler approach. The novelty of this approach lies in partitioning an SPM into a pseudo register file then generalising existing graph colouring algorithms for register allocation to colour data aggregates. In this thesis, a scheme for partitioning an SPM into a pseudo register file is introduced. This methodology is inter-procedural and therefore operates on the interference graph for the data aggregates in the whole program. Different graph colouring algorithms may give rise to different results due to live range splitting and spilling heuristics used. As a result, two representative graph colouring algorithms, George and Appel's iterative-coalescing and Park and Moon's optimistic-coalescing, are generalised and evaluated for SPM allocation. Like memory colouring, perfect colouring is also inter-procedural. The novelty of this second methodology lies in formulating the SPM allocation problem as an interval colouring problem. The interval colouring problem is an NP problem and no widely-accepted approximation algorithms exist. The key observation is that the interference graphs for data aggregates in many embedded applications form a special class of superperfect graphs. This has led to the development of two additional SPM allocation algorithms. While differing in whether live range splits and spills are done sequentially or together, both algorithms place data aggregates in SPM based on the cliques in an interference graph. In both cases, we guarantee optimally that all data aggregates in an interference graph can be placed in SPM if the given SPM size is no smaller than the chromatic number of the graph. We have developed two memory colouring algorithms and two perfect colouring algorithms for SPM allocation. We have evaluated them using a set of embedded applications. Our results show that both methodologies are efficient and effective in handling large-scale embedded applications. While neither methodology outperforms the other consistently, perfect colouring has yielded better overall results in the set of benchmarks used in our experiments. All these algorithms are expected to be valuable. For example, they can be made available as part of the same compiler framework to assist the embedded designer with exploring a large number of optimisation opportunities for a particular embedded application.

Scratch-pad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embedded systems. Compared to hardware-managed cache, SPM can be more efficient in performance, power and area cost, and has the added advantage of better time predictability. In this thesis, SPMs should be seen in a general context. For example, in stream processors, a software-managed stream register file is usually used to stage data to and from off-chip memory. In IBM's Cell architecture, each co-processor has a software-managed local store for keeping data and instructions. SPM management is critical for SPM-based embedded systems. In this thesis, we propose two novel methodologies, the memory colouring methodology and the perfect colouring methodology, to place the static data aggregates such as arrays and structs of a program in SPM. Our methodologies are dynamic in the sense that some data aggregates can be swapped into and out of SPM during program execution. To this end, a live range splitting heuristic is introduced in order to create potential data transfer statements between SPM and off-chip memory. The memory colouring methodology is a general-purpose compiler approach. The novelty of this approach lies in partitioning an SPM into a pseudo register file then generalising existing graph colouring algorithms for register allocation to colour data aggregates. In this thesis, a scheme for partitioning an SPM into a pseudo register file is introduced. This methodology is inter-procedural and therefore operates on the interference graph for the data aggregates in the whole program. Different graph colouring algorithms may give rise to different results due to live range splitting and spilling heuristics used. As a result, two representative graph colouring algorithms, George and Appel's iterative-coalescing and Park and Moon's optimistic-coalescing, are generalised and evaluated for SPM allocation. Like memory colouring, perfect colouring is also inter-procedural. The novelty of this second methodology lies in formulating the SPM allocation problem as an interval colouring problem. The interval colouring problem is an NP problem and no widely-accepted approximation algorithms exist. The key observation is that the interference graphs for data aggregates in many embedded applications form a special class of superperfect graphs. This has led to the development of two additional SPM allocation algorithms. While differing in whether live range splits and spills are done sequentially or together, both algorithms place data aggregates in SPM based on the cliques in an interference graph. In both cases, we guarantee optimally that all data aggregates in an interference graph can be placed in SPM if the given SPM size is no smaller than the chromatic number of the graph. We have developed two memory colouring algorithms and two perfect colouring algorithms for SPM allocation. We have evaluated them using a set of embedded applications. Our results show that both methodologies are efficient and effective in handling large-scale embedded applications. While neither methodology outperforms the other consistently, perfect colouring has yielded better overall results in the set of benchmarks used in our experiments. All these algorithms are expected to be valuable. For example, they can be made available as part of the same compiler framework to assist the embedded designer with exploring a large number of optimisation opportunities for a particular embedded application.

Scratch-pad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embedded systems. Compared to hardware-managed cache, SPM can be more efficient in performance, power and area cost, and has the added advantage of better time predictability. In this thesis, SPMs should be seen in a general context. For example, in stream processors, a software-managed stream register file is usually used to stage data to and from off-chip memory. In IBM's Cell architecture, each co-processor has a software-managed local store for keeping data and instructions. SPM management is critical for SPM-based embedded systems. In this thesis, we propose two novel methodologies, the memory colouring methodology and the perfect colouring methodology, to place the static data aggregates such as arrays and structs of a program in SPM. Our methodologies are dynamic in the sense that some data aggregates can be swapped into and out of SPM during program execution. To this end, a live range splitting heuristic is introduced in order to create potential data transfer statements between SPM and off-chip memory. The memory colouring methodology is a general-purpose compiler approach. The novelty of this approach lies in partitioning an SPM into a pseudo register file then generalising existing graph colouring algorithms for register allocation to colour data aggregates. In this thesis, a scheme for partitioning an SPM into a pseudo register file is introduced. This methodology is inter-procedural and therefore operates on the interference graph for the data aggregates in the whole program. Different graph colouring algorithms may give rise to different results due to live range splitting and spilling heuristics used. As a result, two representative graph colouring algorithms, George and Appel's iterative-coalescing and Park and Moon's optimistic-coalescing, are generalised and evaluated for SPM allocation. Like memory colouring, perfect colouring is also inter-procedural. The novelty of this second methodology lies in formulating the SPM allocation problem as an interval colouring problem. The interval colouring problem is an NP problem and no widely-accepted approximation algorithms exist. The key observation is that the interference graphs for data aggregates in many embedded applications form a special class of superperfect graphs. This has led to the development of two additional SPM allocation algorithms. While differing in whether live range splits and spills are done sequentially or together, both algorithms place data aggregates in SPM based on the cliques in an interference graph. In both cases, we guarantee optimally that all data aggregates in an interference graph can be placed in SPM if the given SPM size is no smaller than the chromatic number of the graph. We have developed two memory colouring algorithms and two perfect colouring algorithms for SPM allocation. We have evaluated them using a set of embedded applications. Our results show that both methodologies are efficient and effective in handling large-scale embedded applications. While neither methodology outperforms the other consistently, perfect colouring has yielded better overall results in the set of benchmarks used in our experiments. All these algorithms are expected to be valuable. For example, they can be made available as part of the same compiler framework to assist the embedded designer with exploring a large number of optimisation opportunities for a particular embedded application.

Scratch-pad memory (SPM), a fast on-chip SRAM managed by software, is widely used in embedded systems. Compared to hardware-managed cache, SPM can be more efficient in performance, power and area cost, and has the added advantage of better time predictability. In this thesis, SPMs should be seen in a general context. For example, in stream processors, a software-managed stream register file is usually used to stage data to and from off-chip memory. In IBM's Cell architecture, each co-processor has a software-managed local store for keeping data and instructions. SPM management is critical for SPM-based embedded systems. In this thesis, we propose two novel methodologies, the memory colouring methodology and the perfect colouring methodology, to place the static data aggregates such as arrays and structs of a program in SPM. Our methodologies are dynamic in the sense that some data aggregates can be swapped into and out of SPM during program execution. To this end, a live range splitting heuristic is introduced in order to create potential data transfer statements between SPM and off-chip memory. The memory colouring methodology is a general-purpose compiler approach. The novelty of this approach lies in partitioning an SPM into a pseudo register file then generalising existing graph colouring algorithms for register allocation to colour data aggregates. In this thesis, a scheme for partitioning an SPM into a pseudo register file is introduced. This methodology is inter-procedural and therefore operates on the interference graph for the data aggregates in the whole program. Different graph colouring algorithms may give rise to different results due to live range splitting and spilling heuristics used. As a result, two representative graph colouring algorithms, George and Appel's iterative-coalescing and Park and Moon's optimistic-coalescing, are generalised and evaluated for SPM allocation. Like memory colouring, perfect colouring is also inter-procedural. The novelty of this second methodology lies in formulating the SPM allocation problem as an interval colouring problem. The interval colouring problem is an NP problem and no widely-accepted approximation algorithms exist. The key observation is that the interference graphs for data aggregates in many embedded applications form a special class of superperfect graphs. This has led to the development of two additional SPM allocation algorithms. While differing in whether live range splits and spills are done sequentially or together, both algorithms place data aggregates in SPM based on the cliques in an interference graph. In both cases, we guarantee optimally that all data aggregates in an interference graph can be placed in SPM if the given SPM size is no smaller than the chromatic number of the graph. We have developed two memory colouring algorithms and two perfect colouring algorithms for SPM allocation. We have evaluated them using a set of embedded applications. Our results show that both methodologies are efficient and effective in handling large-scale embedded applications. While neither methodology outperforms the other consistently, perfect colouring has yielded better overall results in the set of benchmarks used in our experiments. All these algorithms are expected to be valuable. For example, they can be made available as part of the same compiler framework to assist the embedded designer with exploring a large number of optimisation opportunities for a particular embedded application.

A successful immune response depends on prompt and sufficient recruitment of leukocytes from the circulation to infected or injured sites. Mobilization of leukocytes to hypoxic tissues is vital for angiogenesis, i.e. the formation of new blood vessels from preexisting vasculature, and thus crucial for tissue growth and regeneration. Deviations from normal leukocyte recruitment drive a variety of pathologies, including chronic inflammation, autoimmune diseases and cancer, for which therapeutic options are limited or unspecific. Understanding the mechanisms by which the body controls leukocyte recruitment is therefore critical for the development of novel therapeutic strategies. The present investigations focused on delineating the mechanisms behind leukocyte mobilization from the bloodstream to afflicted sites, by means of in vivo imaging techniques and in vitro assays. We demonstrate that, in response to inflammation, increased vascular permeability enhances transendothelial transport of tissue-released chemokines. Within the vasculature, chemokines form a chemotactic gradient sequestered on heparan sulfate, which directs crawling neutrophils and expedites their extravasation to the inflamed tissue. Consequently, gradient formation grants efficient bacterial clearance. Citrullination of chemokines by leukocyte-derived PAD enzymes in the inflamed tissue prevents chemokine transport into blood vessels, which dampens further neutrophil recruitment and thereby controls the amplitude of the inflammatory response. Moreover, the mechanisms of neutrophil recruitment in response to proangiogenic factors released during hypoxia are revealed to differ from those observed during classical inflammation. Particularly, VLA-4 integrin and VEGFR1 expressed on a defined subset of neutrophils, along with endothelial VEGFR2, are required for efficient neutrophil recruitment to hypoxia. Rather than stimulus-induced phenotypic changes on neutrophils, specific neutrophil subtypes with innate proinflammatory or proangiogenic functions (respectively, CD49d-VEGFR1lowCXCR4low and CD49d+VEGFR1highCXCR4high) coexist in the circulation of humans and mice. In summary, this dissertation provides relevant information on specific steps of neutrophil recruitment to inflamed or hypoxic tissues, which may represent future means to down-regulate aberrant immune responses during chronic inflammation and autoimmune diseases; to increase angiogenesis during ischemia; or to limit pathological angiogenesis, a characteristic of tumor growth and of several chronic inflammatory disorders.

L’occurrence en service commercial de fissures macroscopiques dans certains disques de frein TGV a pu être reliée au type de garniture utilisé. L’objectif de cette thèse est de comprendre cette relation, d’identifier les paramètres d’influence et de proposer des voies d’amélioration pour la conception de garnitures à risque de fissuration réduit. Le comportement thermique de quatre couples disque-garnitures est d’abord analysé par le biais d’une campagne expérimentale de freinage originale. Elle met en évidence différents types de localisations thermiques et permet d’identifier des signatures thermiques caractéristiques des garnitures. Le lien entre localisations thermiques et risques de fissuration est ensuite établi à l’aide d’une modélisation thermomécanique. Des indicateurs tenant compte des caractéristiques spatiales et temporelles des localisations thermiques ainsi que des niveaux de température atteints sont proposés. Ils permettent de classer les garnitures testées dans un graphe de « criticité ». Enfin, une étude d’influence des caractéristiques mécaniques et thermiques des garnitures sur les localisations engendrées permet de dégager des préconisations et des voies d’amélioration pour la conception de nouvelles garnitures. La caractérisation expérimentale du comportement de deux nouvelles garnitures, l’une s’approchant le plus des préconisations faites, l’autre s’en éloignant fortement, montre la pertinence de l’approche développée et la validité des préconisations / The occurrence of macroscopic cracks in some TGV brake discs in commercial service has been linked to the pad type used. The objective of this thesis is to understand this relationship, to identify sensitive parameters and to propose guidelines to the design of pads reducing the risk of cracking.The thermal behavior of four disc-pad couples is first analyzed through an original experimental campaign of braking. It highlights various types of thermal localisations and enables to identify thermal signatures characteristic of the various pads. The relationship between thermal localisation and risk of cracking is then determined using thermomechanical modeling. Some indicators taking into account spatial and temporal characteristics of thermal localisations and temperature levels achieved are proposed. They enable to classify the tested pads in a graph of "criticity". Finally, a study of the influence of mechanical and thermal properties of pads on the thermal localisations occurrence enables to propose guidelines and improving ways for the design of new pads. An experimental characterization of the behavior of two new pads, one very close to the given recommendations, the other strongly away from them, shows the relevance of the approach and the validity of the present recommendations

A política agrária brasileira, motivada pelos anseios de reforma e justiça social, vem sendo pautada nos projetos de assentamento familiar, cujo modelo restou também consolidado em território amazônico e repercutindo graves incidentes ambientais. O estudo de caso do Projeto de Assentamento Dirigido Anauá, fincado no sul do Estado de Roraima, traz à tona toda essa complexa problemática, agravada sobremaneira pelo diagnóstico de desflorestamento não autorizado, procedimento de licenciamento ambiental sequer iniciado e responsabilidade a ser apurada dentro dos organismos oficiais de controle. / The Brazilian agrarian policy, motivated by the desire for reform and social justice, has been based on projects of family settlement, the model also remained consolidated in Amazonian territory and resulting serious environmental incidents. The case study of the Draft Settlement Managed Anauá, established in southern state of Roraima, brings to light all those complex problems, particularly exacerbated by the diagnosis of unauthorized deforestation, environmental permitting procedure even started and responsibility to be found within the bodies official control.