Nas últimas décadas a tecnologia de realidade virtual tem sido cada vez mais utilizada em várias aplicações na sociedade. Particularmente a partir do início da década de 90, observamos o advento da realidade virtual baseada em multiprojeções, com o surgimento do paradigma de construção de sistemas de realidade virtual totalmente imersivos como por exemplo o CAVE™. Esta tese tem por objetivo apresentar pesquisas e desenvolvimentos relacionados com a implementação do primeiro sistema de multiprojeção totalmente imersivo baseado em aglomerado de computadores convencionais, sistema este denominado de CAVERNA Digital. O trabalho aqui apresentado é composto por um panorama atual do estado da arte das tecnologias de realidade virtual baseadas em multiprojeção. O conceito de aglomerados de computadores convencionais para realidade virtual, ou especificamente VRCluster é apresentado, bem como uma taxonomia de organização interna dos VRClusters. O sistema de multiprojeção da CAVERNA Digital é apresentado, descrevendo em detalhe as opções dos inúmeros subsistemas como projetores, telas, subsistema de vídeo, dispositivos de interação e outros. Outra contribuição desta tese é pela inovação de uma plataforma de visualização interativa voltada para ambientes de realidade virtual imersivos, plataforma esta denominada de JINX, baseada no padrão aberto X3D. Aspectos relacionados com a operação destes sistemas de realidade virtual avançados são apresentados como é o caso das interface de gerenciamento de ambientes imersivos denominado de SIRIUS e do núcleo de gerenciamento de ambientes imersivos denominado de ZEUS. Por fim vários testes de desempenho são realizados para a validação da integração dos inúmeros recursos utilizados na CAVERNA Digital. / In the last decades, virtual reality technology has been increasingly used in many applications for the society. Particularly in the beginning of 90’s, we can observe the advent of virtual reality based in multi-projections, leading to the construction paradigm of CAVE™ like virtual reality systems. The goal of this thesis is to present the research and developments related to the construction of the first multi projection completely immersive system based on commodity computer clusters called CAVERNA Digital. The work here presented is composed by an updated panorama of the state-of-art multi-projection virtual reality technologies. The concept of commodity computer clusters for virtual reality, or specifically VRCluster is shown, as well as the taxonomy for internal organization of the VRClusters. The CAVERNA Digital multi-projection system is shown, including details of the options of uncountable subsystems, like projectors, screens, video, and interaction devices, among others. This thesis contributes with another innovation: the visualization platform, called JINX, based on the open standard X3D. Aspects related to the operation of these advanced virtual reality systems are presented, which is the case of the user interface for immersive environments called SIRIUS and the management core for immersive environments called ZEUS. Finally, various performance tests were conducted to validate the integration of the uncountable resources used in the CAVERNA Digital.

Existe um crescente aumento nos gastos mundiais em inovação, com maior participação de áreas como a computação, a eletrônica, a saúde, a área automotiva e a área industrial. Mecanismos diferenciados, assimétricos, tais como o estudado neste trabalho, necessitam de maiores investigações, como a realização de ensaios normatizados. Para se contribuir com esse cenário propõe-se a análise de um sistema robótico, de arquitetura paralela, para experimentos de múltiplas finalidades. O presente trabalho aborda desde a construção de uma máquina paralela de topologia assimétrica, passando por seu controle, até a obtenção de informações sobre essa nova arquitetura. A sua construção é dividida em cinco subsistemas, que se interrelacionam: o mecânico, o elétrico, o de atuação, o de controle e o de interface. Sete estratégias de controle foram comparadas de acordo com os seguintes critérios: a exatidão na trajetória, o comprimento controlável, a dispersão das trajetórias em diferentes períodos de tempo, e o consumo de energia. Os resultados foram gerados por meio de registro, em folha de papel, da trajetória do efetuador da máquina. As curvas geradas foram digitalizadas e comparadas entre si. Os resultados mostraram que os controles dinâmicos podem permitir o funcionamento adequado da máquina, sendo possível, inclusive, velocidades maiores que as observadas no controle descentralizado PID. Neste trabalho em particular, o maior desafio observado foi o valor da menor frequência natural amortecida, que se mostrou baixo e resultou em baixos esforços de controle. Em ordem decrescente, os tipos de controle que apresentaram melhores resultados foram o PID descentralizado, o controle por torque computado com feedforward, e o controle por modos deslizantes, também com feedforward. / There is a steady increase in global spending on innovation, with an increased share of areas such as computing, electronics, health, automotive and industrial area. Differentiated, asymmetric mechanisms, such as the one proposed in this work, need further investigations, such as standardized tests. To contribute to this scenario the analysis of a robotic system, with parallel architecture and for multi-purpose experiments, is proposed. This work covers the construction of a parallel machine with asymmetric topology, its control, and the collection of information on this new architecture. Its construction is divided into five sub-systems, which are interrelated: the mechanical, the electrical, the actuation, the control and its interface. Seven control strategies were compared, according to four criteria. The chosen criteria are the following: track accuracy, stability range, dispersion of the paths at different periods and energy consumption. The results were generated by recording, on a sheet of paper, the trajectory of the machine\'s end-effector. The plots were digitalized and compared. The results showed that the dynamic controls can allow the machine to behave appropriately, even at speeds higher than those with the decentralized PID. The main challenge in this case was the lowest damped frequency, with a low value that resulted in low control efforts. In decreasing order, the best results were achieved with the decentralized PID, the feedforward computed torque control and the feedforward sliding modes control.

Tradicionalmente, em aplicações industriais predominam robôs cujas arquiteturas correspondem a estruturas cinemáticas seriais, ou seja, seus atuadores e peças movidas são dispostos em série, um após o outro, formando uma única cadeia cinemática aberta, de modo a posicionar o órgão terminal, a parte do robô que comumente contém uma garra ou um eletrodo de solda. Esses robôs apresentam desempenho insatisfatório em aplicações que demandem precisão, rigidez, alta freqüência natural e baixo tempo de ciclo. Sendo assim, tanto a comunidade acadêmica como a industrial têm manifestado um interesse crescente pela utilização de outro tipo de estrutura cinemática, denominada paralela, que se caracteriza pela presença de várias cadeias cinemáticas independentes, atuando de forma paralela e simultânea sobre o órgão terminal. Essa arquitetura não-convencional apresenta, potencialmente, uma série de vantagens, como: alta rigidez, leveza, rapidez, precisão e alta capacidade de carga. No entanto, existe uma série de problemas abertos que necessitam de uma investigação mais profunda, de modo a garantir que essa mudança de tendência venha a ser implementada com eficácia. O objetivo desta pesquisa é contribuir para o desenvolvimento de uma máquina fresadora de arquitetura paralela que seja promissora quanto à sua simplicidade construtiva, bem como a precisão de posicionamento da ferramenta, se comparada com os robôs paralelos tradicionais. Esses dois requisitos simplicidade e precisão serão alcançados mediante o emprego de uma estrutura modular e a utilização de uma barra de ancoragem ativa, de forma que a estrutura final apresente três atuadores operando em conjunto. Sendo assim, serão empregados três membros, todos ativos, formando uma estrutura cinemática redundante com mobilidade igual a dois. A avaliação do comportamento da arquitetura proposta para a fresadora será realizada por meio de simulações, com o mapeamento dos erros estáticos, de modo a identificar a sua precisão de posicionamento ao longo dos seus eixos de movimentação. / Traditionally, in industrial activities, there is a preference over robots whose architectures correspond to serial kinematic structures, i.e., its actuators and moving parts are arranged in series, one after another, forming a single open kinematic chain, in order to position the body terminal, the part of the robot that commonly contain a claw or a welding electrode. However, these robots have poor performance in applications that require precision, rigidity, high natural frequency and low cycle time. Due to these factors, both academic and industrial communities have expressed a growing interest in the use of another type of kinematic structure, called parallel, which is characterized by the presence of several independent kinematic chains, operating in parallel and simultaneously on the terminal organ. This unconventional architecture has potentially a number of advantages, such as high stiffness, lightness, speed, precision and high load capacity. However, there are a number of open problems that need further investigation in order to ensure that this trend change will be implemented effectively. The objective of this research is to contribute for the development of a parallel milling machine that presents a promising behavior in terms of precision and simplicity in construction, compared with the traditional parallel robots. Both requirements simplicity and precision will be achieved with the utilization of a modular structure and the introduction of an active docking bar, so that the final structure has three actuators working simultaneously. Thus, three members will be used, all active, forming a kinematic redundant structure with mobility equal to two. The expected behavior of the proposed architecture for the milling machine is evaluated through simulations, with the mapping of static errors that allow the identification of its positioning accuracy along the motion axes.

Nas últimas décadas a tecnologia de realidade virtual tem sido cada vez mais utilizada em várias aplicações na sociedade. Particularmente a partir do início da década de 90, observamos o advento da realidade virtual baseada em multiprojeções, com o surgimento do paradigma de construção de sistemas de realidade virtual totalmente imersivos como por exemplo o CAVE™. Esta tese tem por objetivo apresentar pesquisas e desenvolvimentos relacionados com a implementação do primeiro sistema de multiprojeção totalmente imersivo baseado em aglomerado de computadores convencionais, sistema este denominado de CAVERNA Digital. O trabalho aqui apresentado é composto por um panorama atual do estado da arte das tecnologias de realidade virtual baseadas em multiprojeção. O conceito de aglomerados de computadores convencionais para realidade virtual, ou especificamente VRCluster é apresentado, bem como uma taxonomia de organização interna dos VRClusters. O sistema de multiprojeção da CAVERNA Digital é apresentado, descrevendo em detalhe as opções dos inúmeros subsistemas como projetores, telas, subsistema de vídeo, dispositivos de interação e outros. Outra contribuição desta tese é pela inovação de uma plataforma de visualização interativa voltada para ambientes de realidade virtual imersivos, plataforma esta denominada de JINX, baseada no padrão aberto X3D. Aspectos relacionados com a operação destes sistemas de realidade virtual avançados são apresentados como é o caso das interface de gerenciamento de ambientes imersivos denominado de SIRIUS e do núcleo de gerenciamento de ambientes imersivos denominado de ZEUS. Por fim vários testes de desempenho são realizados para a validação da integração dos inúmeros recursos utilizados na CAVERNA Digital. / In the last decades, virtual reality technology has been increasingly used in many applications for the society. Particularly in the beginning of 90’s, we can observe the advent of virtual reality based in multi-projections, leading to the construction paradigm of CAVE™ like virtual reality systems. The goal of this thesis is to present the research and developments related to the construction of the first multi projection completely immersive system based on commodity computer clusters called CAVERNA Digital. The work here presented is composed by an updated panorama of the state-of-art multi-projection virtual reality technologies. The concept of commodity computer clusters for virtual reality, or specifically VRCluster is shown, as well as the taxonomy for internal organization of the VRClusters. The CAVERNA Digital multi-projection system is shown, including details of the options of uncountable subsystems, like projectors, screens, video, and interaction devices, among others. This thesis contributes with another innovation: the visualization platform, called JINX, based on the open standard X3D. Aspects related to the operation of these advanced virtual reality systems are presented, which is the case of the user interface for immersive environments called SIRIUS and the management core for immersive environments called ZEUS. Finally, various performance tests were conducted to validate the integration of the uncountable resources used in the CAVERNA Digital.

Esta tese apresenta um estudo sobre a implementação de sistema de detecção e reconhecimento de faces no processador CELL na plataforma CBE, utilizando um sistema Playstation 3. Inicialmente, diversas abordagens para reconhecimento e detecção de faces são estudadas, bem como arquiteturas de processador multi núcleos. São apresentadas três implementação, sendo a segunda implementação premiada com quarto colocado no IBM CELL UNIVERSITY CHALLENGE 2007 para desenvolvimento de programas para plataforma Cell BE. A terceira implementação apresenta os resultados interessantes relacionados a vetorização do processamento dos dados da detecção de objetos e os recursos adotados para obter o melhor desempenho. / This thesis presents a study of face detection implementation on CBE plataform and employ the system with Playstation 3 hardware. Several approaches for face detection and recognition are studied as well as multicore processor architetures. We implemented three versions of system. First implementation was a naive reference implementation with worst performance. Second implementation granted fourth prize in IBM CELL UNIVERSITY CHALLENGE 2007 that incentive development on CBE plataform. Third implementation had most interesting results with vectorized approaches on code of object detection.

Cette thèse présente nos travaux de recherche qui ont comme principal objectif d'assurer la portabilité des performances et le passage à l'échelle des applications scientifiques complexes exécutées sur des plates-formes multi-coeurs parallèles et hiérarchiques. La portabilité des performances est obtenue lorsque l'ordonnancement des tâches d'une application permet de réduire les périodes d'inactivité des coeurs de la plate-forme. Cette portabilité des performances peut être affectée par différents problèmes tels que des déséquilibres de charge, des communications coûteuses et des surcoûts provenant de l'ordonnancement des tâches. Le déséquilibre de charge est la conséquence de comportements de charges irrégulières et dynamiques, où le volume de calcul varie dynamiquement en fonction de la tâche et de l'étape de simulation. Les communications coûteuses sont provoquées par un ordonnancement qui ne prend pas en compte les différents temps de communication entre tâches sur une plate-forme hiérarchique. Cela est accentué par des communications non uniformes et asymétriques au niveau mémoire et réseau. Enfin, ces surcoûts peuvent être générés par des algorithmes de placement trop complexes dont les coûts ne seraient pas compensés par les gains de performance.Pour atteindre cet objectif de portabilité des performances, notre approche repose sur une récolte d'informations précises sur la topologie de la machine qui vont aider les algorithmes d'ordonnancement de tâches à prendre les bonnes décisions. Dans ce contexte, nous avons proposé une modélisation générique de la topologie des plates-formes parallèles. Le modèle comprend des latences et des bandes passantes mesurées de la mémoire et du réseau qui mettent en évidence des asymétries. Ces informations sont utilisées par nos trois algorithmes d'équilibrage de charge nommés NucoLB, HwTopoLB, et HierarchicalLB. De plus, ces algorithmes utilisent des informations provenant de l'exécution de l'application. NucoLB se concentre sur les aspects non uniformes de plates-formes parallèles, alors que HwTopoLB considère l'ensemble de la hiérarchie pour ses décisions, et HierarchicalLB combine ces algorithmes hiérarchiquement pour réduire son surcoût d'ordonnancement de tâches. Ces algorithmes cherchent à atténuer le déséquilibre de charge et des communications coûteuses tout en limitant les surcoûts de migration des tâches.Les résultats expérimentaux avec les trois régulateurs de charge proposés ont montré des améliorations de performances sur les meilleurs algorithmes de l'état de l'art: NucoLB a présenté jusqu'à 19% d'amélioration de performances sur un noeud de calcul; HwTopoLB a amélioré les performances en moyenne de 19%, et HierarchicalLB a surclassé HwTopoLB de 22% en moyenne sur des plates-formes avec plus de dix noeuds de calcul. Ces résultats ont été obtenus en répartissant la charge entre les ressources disponibles, en réduisant les coûts de communication des applications, et en gardant les surcoûts d'équilibrage de charge faibles. En ce sens, nos algorithmes d'équilibrage de charge permettent la portabilité des performances pour les applications scientifiques tout en étant indépendant de l'application et de l'architecture du système. / This thesis presents our research to provide performance portability and scalability to complex scientific applications running over hierarchical multicore parallel platforms. Performance portability is said to be attained when a low core idleness is achieved while mapping a given application to different platforms, and can be affected by performance problems such as load imbalance and costly communications, and overheads coming from the task mapping algorithm. Load imbalance is a result of irregular and dynamic load behaviors, where the amount of work to be processed varies depending on the task and the step of the simulation. Meanwhile, costly communications are caused by a task distribution that does not take into account the different communication times present in a hierarchical platform. This includes nonuniform and asymmetric communication costs at memory and network levels. Lastly, task mapping overheads come from the execution time of the task mapping algorithm trying to mitigate load imbalance and costly communications, and from the migration of tasks.Our approach to achieve the goal of performance portability is based on the hypothesis that precise machine topology information can help task mapping algorithms in their decisions. In this context, we proposed a generic machine topology model of parallel platforms composed of one or more multicore compute nodes. It includes profiled latencies and bandwidths at memory and network levels, and highlights asymmetries and nonuniformity at both levels. This information is employed by our three proposed topology-aware load balancing algorithms, named NucoLB, HwTopoLB, and HierarchicalLB. Besides topology information, these algorithms also employ application information gathered during runtime. NucoLB focuses on the nonuniform aspects of parallel platforms, while HwTopoLB considers the whole hierarchy in its decisions, and HierarchicalLB combines these algorithms hierarchically to reduce its task mapping overhead. These algorithms seek to mitigate load imbalance and costly communications while averting task migration overheads.Experimental results with the proposed load balancers over different platform composed of one or more multicore compute nodes showed performance improvements over state of the art load balancing algorithms: NucoLB presented improvements of up to 19% on one compute node; HwTopoLB experienced performance improvements of 19% on average; and HierarchicalLB outperformed HwTopoLB by 22% on average on parallel platforms with ten or more compute nodes. These results were achieved by equalizing work among the available resources, reducing the communication costs experienced by applications, and by keeping load balancing overheads low. In this sense, our load balancing algorithms provide performance portability to scientific applications while being independent from application and system architecture.

As emerging portable multimedia applications demand more and more computational throughput with limited energy consumption, the need for high-efficiency, high-throughput embedded processing is becoming an important challenge in computer architecture. In this regard, this dissertation addresses application-, architecture-, and technology-level issues in existing processing systems to provide efficient processing of multimedia in many, or ideally all, of its form. In particular, this dissertation explores color imaging in multimedia while focusing on two architectural enhancements for memory- and performance-hungry embedded applications: (1) a pixel-truncation technique and (2) a color-aware instruction set (CAX) for embedded multimedia systems. The pixel-truncation technique differs from previous techniques (e.g., 4:2:2 and 4:2:0 subsampling) used in image and video compression applications (e.g., JPEG and MPEG) in that it reduces the information content in individual pixel word sizes rather than in each dimension. Thus, this technique drastically reduces the bandwidth and memory required to transport and store color images without perceivable distortion in color. At the same time, it maintains the pixel storage format of color image processing in which each pixel computation is performed simultaneously on 3-D YCbCr components, which are widely used in the image and video processing community. CAX supports parallel operations on two-packed 16-bit (6:5:5) YCbCr data in a 32-bit datapath processor, providing greater concurrency and efficiency for processing color image sequences. This dissertation presents the impact of CAX on processing performance and on both area and energy efficiency for color imaging applications in three major processor architectures: dynamically scheduled (superscalar), statically scheduled (very long instruction word, VLIW), and embedded single instruction multiple data (SIMD) array processors. Unlike typical multimedia extensions, CAX obtains substantial performance and code density improvements through direct support for color data processing rather than depending solely on generic subword parallelism. In addition, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. In summary, CAX, coupled with the pixel-truncation technique, provides an efficient mechanism that meets the computational requirements and cost goals for future embedded multimedia products.

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The turbo codes are a well known channel coding technique widely used because of their outstanding error decoding performance close to the Shannon limit. These codes were proposed using a clever pragmatic approach where a set of concepts that had been previously introduced, together with the iterative processing of data, are successfully combined to obtain close to optimal decoding performance capabilities. However, precisely because this iterative processing, high latency values appear and the achievable decoder throughput is limited. At the beginning of our research activities, the fastest turbo decoder architecture introduced in the literature achieved a throughput peak value around 700 Mbit/s. There were also several works that proposed architectures capable of achieving throughput values around 100 Mbit/s. Research opportunities were then available in order to establish architectural solutions that enable the decoding at a few Gbit/s, so that the industrial requirements are fulfilled and future high performance digital communication systems can be conceived. The first part of this work is devoted to the study of the turbo codes at an algorithmic level. Several SISO decoder algorithms are explored, and different parallel turbo decoder techniques are analyzed. The convergence of parallel turbo decoder is specially considered. To this end the EXtrinsic Information Transfer (EXIT) charts are used. Conclusions derived from these kind of diagrams have served to propose a novel SISO decoder schedule to be used in shuffled turbo decoder architectures. The architectural issues when implementing high parallel turbo decoder are considered in the second part of this thesis. We propose a high throughput low complexity radix-16 SISO decoder. This decoder is intended to break the bottleneck that appears because of the recursive operations in the heart of the turbo decoding algorithm. The design of this architecture was possible thanks to the elimination of parallel paths in a radix-16 trellis diagram transition. The proposed SISO decoder implements a high speed radix-8 Add Compare Select (ACS) unit which exhibits a lower hardware complexity and lower critical path compared with a radix-16 ACS unit. Our radix-16 SISO decoder degrades the turbo decoder error correcting performance. Therefore, we have proposed two techniques so that the architecture can be used in practical applications. Thus, architectural solutions to build high parallel turbo decoder architectures, which integrate our SISO decoder, are presented. Finally, a methodology to efficiently explore the design space of parallel turbo decoder architectures is described. The main objective of this approach is to reduce the time to market constraint by designing turbo decoder architectures for a given throughput.

Este trabalho define um modelo de execução para cláusulas Prolog, a partir do modelo abstrato de Máquinas de Cláusulas, e o Projeto de uma arquitetura paralela que suporte o modelo proposto. São também introduzidos alguns aspectos sobre as linguagens Lógicas e as máquinas Prolog visto que estes elementos estão relacionados intimamente tanto com o modelo quanto com a arquitetura propostos. Na proposta do modelo de execução são definidos uma representação para os elementos do modelo abstrato (predicados, arcos e clausulas) e um conjunto de algoritmos que permitem a operacionalização do modelo de forma a que tanto o paralelismo como a concorrência inerentes ao modelo abstrato sejam exploradas de forma integral. Na proposta da arquitetura são, primeiramente, discutidas algumas opções de arquitetura básica e, posteriormente, descrita a arquitetura escolhida tanto a nível de blocos bem como dos seus componentes principais, a saber: interface de mem6ria, processador e rede de interconexão. Para cada um destes componentes são descritas as principais instruções e são apresentados os algoritmos que as implementam. Junto com a descrição da arquitetura é definida uma estrutura de dados que permite a implementação da representação descrita no modelo de execuqao e é definido também o algoritmo de unificação que percorre a estrutura proposta. Na validação é feito o cálculo da largura de banda máxima alcançada pela arquitetura proposta, calculo este baseado no algoritmo de unificação descrito. E também feita uma avaliação do ganho de performance da arquitetura proposta em relação a um processador bem como é justificado o numero de processadores escolhidos comparando a performance alcançada na arquitetura proposta com a performance alcançada por conjuntos maiores e menores de processadores. Por fim na conclusa o são feitos comentários sobre os objetivos atingidos e sobre possíveis extensões a este trabalho. / The present work defines a execution model for Prolog clauses based on the clause machines abstract model and then proposes a parallel architecture for the execution model. Some topics about Logic languages and Prolog machines were therefore introduced because they are closely related with, both, the model and the architecture proposed. In the execution model the representation of the abstract model elements (predicates, arcs and clauses) and the set of algoritms that allow the operation of the model were defined so that the parallelism of the model can be integraly achieved. In the architecture proposal, first some options for the basic architecture were discussed and then the chosen architecture is describeb at block level as much as at its components level. The most importants components reported are the memory interface, the processor and the interconection net, for each one of them the possible instructions were describeb as well as their algoritms. Together with the especification of the architecture, the data estructure that allows the implementation of the execution model representation and the concerning unification algorit that scans the proposed representation were especified too. In the validation the thoughtput permited by the proposal architecture is calculated based on the unification algoritm earlier described. Besides that the performance gain compared with an architecture with only one processor was estimated, as much as the confrontation of the performance of lesser and greater sets of processors elements were made in order to validate the chossen number. At last, in the conclusion, some coments about the fulfilled goals and about eventual extends for the work.