The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

In this report a phase locked loop (PLL) system for grid voltage phase tracking has been investigated. The grid voltage phase angle contains critical information for connecting a power plant, such as a wave energy converter, to the grid. A synchronous reference frame PLL system with PI-regulator gains calculated with the symmetrical optimum method has been designed and simulations in SIMULINK have been made. For ideal grid conditions the phase angle was tracked fast and accurate. For non-ideal conditions the phase angle was tracked but with less accuracy, due to slow dynamics of the system, but still within acceptable margins. In order to test this system further it has to be implemented in a control system and tested when connected to the grid.

In the current transmission systems, the transmission capacity is still not enough. The information bandwidth of the optical fiber communication system is limited by the optical amplifier bandwidth, and more efficient use of the bandwidth is a very important issue. Therefore, the amplitude and phase shift keying (APSK) is one attractive method of multi-bit per symbol modulation scheme to improve the spectral efficiency, and it can effectively increase the transmission capacity. To improve the capacity and the spectral efficiency, the advanced modulation format is effective, and the coherent detection scheme is also effective. However, an optical phase-locked loop (PLL) to lock the local oscillator (LO) phase and the signal phase required for the homodyne detection is still difficult to realize and it makes the receiver circuit complicated. Using the digital coherent receiver, the optical carrier phase information can be recovered by means of the digital signal processing (DSP), and this scheme enables to eliminate the optical PLL circuit by the phase estimation algorithm through the DSP. The stored data can be offline processed by using the MATLAB program. This master thesis is focusing on studying the transmission performance of the APSK format using the DSP in the digital coherent receiver. 497km transmission experiment has been conducted. Subsequently, the stored data are offline processed by the algorithms of the DSP. Then, the APSK performances between back-to-back and 497km transmission are compared.

A successive approximation register (SAR) circuit is adopted to control the digital delay line in the delay-locked loop (DLL) to achieve very fast locking effect in this proposed thesis. And in order to get low power consumption results, a loop state controller (LSC) is utilized to disable most of circuit. Because it is more easily to design and the advantages of high stability of delay-locked loop (DLL) compared to phase-locked loop (PLL), delay-locked loop (DLL) is more widely used in the adjustment of the clock error in the high frequency situation. This proposed delay locked loop (DLL) is added a register and a multiplexer in the feedback path. And the multiplexer does select which n-bit digital control code shall be read into the delay line; as the loop is locked, the path goes through the register is chosen to enter the sleep state ,and disable part of the circuit to make it into power saving mode. When entering the sleep state, the register provides the fixed input code; the phase error comparator (PEC) will keep tracking whether the frequency changes due to process, voltage, temperature and load (PVTL) variation uninterruptedly. Once there is something changed, the PEC will send a signal to inform the loop state controller (LSC) to enable the circuit from the sleep state, when the clock has to be locked again. And it just has 6 cycles time to relock, the lock range is form 150MHz to 900MHz. The power consuming are 15mW in lock mode and 9mW in sleep mode.

The grid voltage is normally required to avoid transient current of the inverter due to asynchronously grid-paralleling connection. This paper presents a seamless transition method to allow the inverter to connect to the grid at any time with no requirement of the grid voltage. The control of the inverter consists of the droop control and the riding-through control. In the droop-controlled mode, the inverter can connect to the utility and supply power according to its rated capacity. On the other hand, the riding-through mode is proposed to suppress the transient current due to asynchronous paralleling. In this mode, the zero-current control is realized to reduce transient current and a phase-locked loop is designed to correct the angle of the inverter output voltage. In addition, the virtual inductance is implemented to improve transient current resulting from the mode transition back to the droop control mode. Design considerations of the seamless transition method are provided and test results are conducted to verify its effectiveness.

Circuit optimization is extremely important in order to design today's high performance integrated circuits. As systems become more and more complex, traditional optimization techniques are no longer viable due to the complex and simulation intensive nature of the optimization problem. Two examples of such problems include clock mesh skew reduction and optimization of large analog systems, for example Phase locked loops. Mesh-based clock distribution has been employed in many high-performance microprocessor designs due to its favorable properties such as low clock skew and robustness. However, such clock distributions can become quite complex and may consist of hundreds of nonlinear drivers strongly coupled via a large passive network. While the simulation of clock meshes is already very time consuming, tuning such networks under tight performance constraints is an even daunting task. Same is the case with the phase locked loop. Being composed of multiple individual analog blocks, it is an extremely challenging task to optimize the entire system considering all block level trade-offs. In this work, we address these two challenging optimization problems i.e.; clock mesh skew optimization and PLL locking time reduction. The expensive objective function evaluations and difficulty in getting explicit sensitivity information make these problems intractable to standard optimization methods. We propose to explore the recently developed asynchronous parallel pattern search (APPS) method for efficient driver size tuning. While being a search-based method, APPS not only provides the desirable derivative-free optimization capability, but also is amenable to parallelization and possesses appealing theoretically rigorous convergence properties. In this work it is shown how such a method can lead to powerful parallel optimization of these complex problems with significant runtime and quality advantages over the traditional sequential quadratic programming (SQP) method. It is also shown how design-specific properties and speeding-up techniques can be exploited to make the optimization even more efficient while maintaining the convergence of APPS in a practical sense. In addition, the optimization technique is further enhanced by introducing the feature to handle non-linear constraints through the use of penalty functions. The enhanced method is used for optimizing phase locked loops at the system level.

This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages. We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.

Abstract¡G For the fractional-N frequency synthesizers using delta-sigma modulation techniques, the noise source dominant to degrade the spectral purity comes from phase intermodulation of quantization noise due to the PLL nonlinearity. To study and improve the PLL nonlinearity effect, this thesis applies the theory of white quantization noise and nonlinear analysis method to simulate the frequency responses of quantization noises in delta-sigma modulators (DSM) with different order and in various architecture. With the help of Agilent EEsof¡¦s ADS tool, the phase noise performance of the studied fractional-N frequency synthesizers can be well predicted. For demonstration, this thesis work implements a 2.4 GHz fractional-N frequency synthesizer hybrid module, and measures the phase noise under considering various combinations of DSM order and architecture, PLL bandwidth and reference frequency. Another demonstration of this thesis is to implement a PLL IC using 0.18 £gm CMOS process. The implemented PLL IC operates in the frequency range from 2120 to 2380 MHz with a supply voltage of 1.8 V and a current consumption of 27 mA. Under the test condition of reference frequency and PLL bandwidth equal to 20 MHz and 50 kHz, respectively, the measured phase noise is 90 dBc/Hz at an offset frequency of 100 kHz and the measured stable time is about 40 £gs for a frequency jump of 80MHz.

Phase locking of external-cavity diodes laser¡]ECDL¡^ to the stabilized optical frequency combs of a femtosecond mode-locked laser. Optical frequency combs of a femtosecond mode-locked laser can be the reference standard of dual-wavelength external-cavity diode lasers (ECDLs). Frequency stabilization of two external-cavity diode laser is also demonstrated simultaneously.Suppression of the frequency fluctuation of two ECDLs from hundreds MHz to 200 Hz is demonstrated and characterized. Meanwhile, frequency tunable continuous-wave Tera-Hertz (cw THz) wave is generated and observed by photomixing of the output of two frequency stabilized ECDLS with tunable relative frequency difference on a photoconductive antennas. In our experiment, cw THz wave is demonstrated and with tuning range from 0.200 to 1.240THz and could be attribute as frequency standard of THz.

Recently, there has been increasing interest within the potential user community of Global Positioning System (GPS) for high precision navigation problems such as aircraft non precision approach, river and harbor navigation, real-time or kinematic surveying. In view of more and more GPS applications, the reliability of GPS is at this issue. The Global Positioning System (GPS) is a space-based radio navigation system that provides consistent positioning, navigation, and timing services to civilian users on a continuous worldwide basis. The GPS system receiver provides exact location and time information for an unlimited number of users in all weather, day and night, anywhere in the world. The work in this thesis will mainly focuss on how to model a Mathematical expression for tracking GPS Signal using Phase Locked Loop filter receiver. Mathematical formulation of the filter are of two types: the first order and the second order loops are tested successively in order to find out a compromised on which one best provide a zero steady state error that will likely minimize noise bandwidth to tracks frequency modulated signal and returns the phase comparator characteristic to the null point. Then the Z-transform is used to build a phase-locked loop in software for digitized data. Finally, a Numerical Methods approach is developed using either MATLAB or Mathematica containing the package for Gaussian elimination to provide the exact location or the tracking of a GPS in the space for a given a coarse/acquisition (C/A) code.