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近幾年再生能源的議題非常的熱門，各種再生能源產業的風力發電、太陽能電池、生質能、燃料電池等產業資料，相關創業與投資訊息不斷的傳播。各種科技看起來，好像都是明日之星。對於一個要準備創業的創業家，那一個產業那一個區間才是適合的機會？在投入創業前要透過何種有效的篩選工具才能選出適當的創業機會？ 本研究先從史考特‧夏恩(2005) 的科技創業聖經十個面向，再到創新者的解答與創新者的解答中的所提出的破壞性創新的觀念，先以質性研究的紮根理論探討檢視潛在創業產業及個案的可行性探討，對於經過第一階段質性研究考驗的個案，再以折價現金流量（Discount Cash-Flow）建立量化研究的財務模型，以求得資本內部報酬率（Equity Internal Return Ratio）及淨現金流量（Net Present Value）並以敏感性分析及情境分析探討財務可行性，期望找出一個創業機會能完全符合所有前訴的條件。本研究歷經三年的探討，檢視過數十個個案，包括風力發電、燃料電池、生質酒精、生質柴油、太陽能產業上中下游等創業機會，若要在台灣的環境創業又要提高創業成功機率，且又要能滿足創業團隊財務的報酬率的期望，能經過這麼多條件考驗的個案少之又少。 本研究最後選定以太陽能產業最上游的多晶矽改良式冶金法做為創業探討的個 案，最主要的原因是太陽能產業是屬於一種再生能源，有很大的機會成為長期高速成長的產業，且台灣因半導體產業及面板產業已為太陽能產業建立了基礎，多晶矽改良式冶金法又是一種破壞性創新，能提高創業成功的機會，且若在上游產業成功創業，能建立很高的進入障礙，對太陽能產業的發展佈局能具有策略性的地位。多晶矽改良式冶金法創業計畫在經過財務模型試算後，資本內部報酬率及淨現金流量，即使以改變投資條件進行創業投資的敏感性分析，或以不同情境進行探討，都能符合財務需求條件，仍能滿足創業投資的要求。 / Re-newable energy is very hot in these few years. There is lots of information mention about start-up and invest of renewable energy industry including win-power, solar-cell, bio-energy, fuel-cell. Seems every technology will be a future star industry. Which sector of what kind of re-newable energy technology will be the proper opportunity for an entrepreneur? What are effective tools to sieve the proper start-up chance out？ This research first using quality research grounding theories, this research verify proper industry and to find out the feasibility for the specific case. The technology management theories including , Shane’s （2005）「Find Fertile Ground – Indentifying Extraordinary Opportunities for New Ventures 」 10 procedures and Christensen ( 1997) 「 The innovator’s Dilemma 」、 Christensen & Raynor (2004) 「The innovator’s Solution：The creating and sustaining successful growth 」- Disruptive innovation technology theories . When the specific case through the quality detected, go to quantity study. Th quantity study include building a finance model,calculate Discount Cash-Flow, Equity Internal Return Ratio, Net Present Value, Sensitive analysis Senarial analysis to find out the financial feasibility. This research hopes to find out a suitable star-up opportunity which could pass all the examination items of quality and quantity study. This research through three whole years to search start-up opportunities., examed dozens cases, and the industies including win-power, solar-cell, bio-energy, fuel-cell and stream sector contain up-stream, middle-stream, down-stream After through this research process, shows that it is really hard to find out a suitable, profitable and could content the financial expection ratio with high win-odds opportunities to run start-up. After three years, this research finally pick up the solar upest-stream sector （modified metelology poly-silicon）as the research case. The first reason is that solar industry belongs to re-newable energy, which has strong protenial to become a long term and high conpound growing rate industy. The second reason：Taiwan have been developing semi- ductor and LCD industries over twenty years and built firmly industy knowledge foundation.Modified metelology poly-silicon is a disruptive innovation, could enlarge the start-up winodds. The third reason is that to start-up in the solar industy up-stream sector could build a high barrier and keep a strategy position in the solar industry. The third reason is that the financial result will fit in with the investor’s expect.

Passivating-contact technologies fabricated from polycrystalline-silicon (poly-Si) are increasingly considered by the crystalline silicon (c-S) PV industry to be key enablers towards record performance. This is largely thanks to their ability to provide excellent carrier collection and surface passivation, while being compatible with industrial scale production. Poly-Si based passivating contacts consist of a stack of an ultrathin silicon oxide (SiOx) film on the surface of crystalline silicon (c-Si), covered by a doped silicon film. Thin films of SiOx can be grown by several different methods: chemically, thermally, or via UV-ozone exposure. However, each of these methods presents challenges towards industrial implementation. Here, we report an alternative method to grow SiOx films using an in-situ plasma process, where we subsequently deposit the doped poly-Si layer in the same process chamber by plasma enhanced chemical vapor deposition (PECVD). This process presents several advantages, such as ease of fabrication, inherently single-side oxide growth and poly-Si deposition, and the combined deposition in one chamber, lowering capital expenditure. Subsequently, we studied the structure of the SiOx films and the doped poly-Si(p+) capping layers using X-ray photoelectron spectroscopy (XPS) and ultraviolet photoelectron spectroscopy (UPS) in order to determine the films’ elemental composition, and the band alignment at the semiconductor/oxide interfaces. A less p-type polysilicon was observed grown on top of a wet SiOx/c-Si with the origin tentatively attributed to depletion of the boron dopant via pin holes evidenced by AFM. A surface photo-voltage (SPV) was observed by XPS under in-situ light bias (AM 1.5) and a representation of the band alignment of the c-Si/SiOx/p-polysilicon under illumination is derived. The SPV was attributed to the photo accumulation of holes at the p-polysilicon and a splitting of quasi-fermi levels with its magnitude correlated to the device measured iVoc . Finally, a valuable application for this contact technology is the integration of silicon with perovskite solar cells, in the so-called monolithic tandem configuration. This approach is very promising to develop a new generation of PV with unmatched performances. Here, poly-Si contacts offer a variety of advantages, thanks to their broader material selection and to the stability at high processing temperature.

Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 nm CMOS generation. Fully silicidation metal gate (FUSI) is one of the most promising solutions. Furthermore, FUSI metal gate reduces gate-line sheet resistance, prevents boron penetration to channels, and has good process compatibility with high-k gate dielectric. Poly-SiGe gate technology is another solution because of its enhancement of boron activation and compatibility with the conventional CMOS process. Combination of these two technologies for the formation of fully germanosilicided metal gate makes the approach very attractive. In this paper, the deposition of undoped Poly-Si₁₋xGex (0 < x < 30% ) films onto SiO₂ in a low pressure chemical vapor deposition (LPCVD) system is described. Detailed growth conditions and the characterization of the grown films are presented. / Singapore-MIT Alliance (SMA)

Silicon photovoltaic (PV) is a promising solution for energy shortage and environmental pollution. We are experiencing an era when PV is exponentially increasing. Global cumulative installation had reached 380 GW in 2017. Among which, silicon-based PV productions share more than 90% market. Performance of the first two-generation commercial popular silicon solar cells - Al-BSF and PERC - are limited by metal/Si contacts, where interface defects significantly reduce the open-circuit voltage. In this context, full-area passivation concepts are proposed for c-Si solar cells, with expectation to enhance the efficiency via reducing carrier recombination loss at the contact regions. In this thesis, poly silicon on oxide (POLO) passivating contact is developed for high efficiency c-Si solar cells. We unveiled the working mechanisms of POLO cells and then optimized the device performance based on our conclusion. We use boiling nitric acid to oxidize c-Si surface, which is of significance to determine the POLO working mechanisms. Phosphorus and boron doped silicon films are deposited by plasma enhanced vapor deposition (PECVD) or low-pressure vapor deposition (LPCVD) followed by high temperature (>800°C) annealing. SiOx structural evolution process under different annealing temperature was observed and the corresponding effects on passivation have been elucidated. The carrier transport mechanisms in the POLO contact annealed at high temperature, e.g. 800°C  900°C, were explored. We unveil that carrier transport in POLO structure is a combination of tunneling and pinhole transport, but dominant at varied temperature regions. Phosphorus-doped n-type POLO contact is optimized by several parameters, such as doping concentration, film thickness, annealing temperature, film deposition temperature, film relaxation time during annealing process, etc. We successfully obtained minority carrier lifetime over 10ms and contact resistivity lower than 30 mΩ·cm2. Boron-doped p-type POLO contact is also optimized by changing the doping concentration and annealing temperature. Finally, further hydrogen passivation is applied to enhance p-type POLO contact passivation, achieving an iVoc>690 mV, J0 <5 fA/cm2 and contact resistivity 1.3 mΩ·cm2. With the optimized n-type and p-type POLO contacts, an efficiency over 18% is achieved on n-type c-Si solar cells with a flat front surface.

Pour les futures applications en télécommunications 5G, des substrats à base de silicium présentant une faible perte de signal et une excellente linéarité sont nécessaires. Parmi les solutions envisagées, la technologie RF-SOI est la plus avancée. Son empilement contient une couche de Haute Résistivité (HR), riche en pièges pour les porteurs de charges, composée de silicium polycristallin (poly-Si) de haute pureté déposée sur l’oxyde natif d'un substrat HR (HR-Si). Ce système présente certaines limitations provenant essentiellement de l'interface HR-Si/SiO2 et de sa stabilité thermique, mais également de la résistivité insuffisante de la couche riche en pièges. L'objectif principal de cette thèse était d'explorer des approches innovantes pour résoudre ces difficultés tout en restant compatible avec la technologie silicium. Afin d’atteindre ces objectifs, du carbone a été ajouté dans le système au cours des différentes étapes d'élaboration: i) remplacement de la couche interfaciale de SiO2 par une couche mince de 3C-SiC et ii) ajout de carbone pendant le dépôt de poly-Si.En utilisant la technique de dépôt chimique en phase vapeur à pression atmosphérique, des couches HR de poly-Si à l'état de l'art ont été déposée sur oxyde natif avec une épaisseur pouvant aller jusqu'à quelques dizaines de µm. Les résultats ont montré que la résistivité de la couche de poly-Si n'était pas directement dépendante de la taille moyenne des grains. Le remplacement de l'oxyde interfacial par une couche mince de mono- ou de poly-SiC, ainsi que l'adaptation des conditions de croissance ont permis d'atteindre des propriétés équivalentes à l'état de l'art des couches HR de poly-Si. Cet empilement a l'avantage d'être plus stable thermiquement en évitant la dissolution de la couche interfaciale. Cependant, ces améliorations sont accompagnées d’une chute de la résistivité à l’interface attribuée à la conductivité importante du matériau SiC. Par ailleurs, les propriétés de la couche HR et sa stabilité thermique peuvent être améliorées en dopant le poly-Si avec du Carbone, si une concentration adéquate de cette impureté est utilisée. L'insertion périodique de couches minces de SiC dans le poly-Si conduit à la stabilité thermique la plus élevée et à une augmentation de la résistivité moyenne de la couche. Néanmoins, des diminutions périodiques de la résistivité sont observées à chaque insertion de SiC / For future 5G telecommunication applications, Si-based substrates with low signal loss and excellent linearity are required. Among the envisaged solutions, RF-SOI is the most advanced. Its stack contains a High Resistivity (HR) Trap-Rich (TR) layer composed of high purity polycrystalline silicon (poly-Si) deposited on thin SiO2 native oxide of a HR-Si substrate (HR-Si). Some limitations of such system come from the HR-Si/SiO2 interface and its thermal stability, while increasing the resistivity of the TR-layer is also suited. The main objective of this thesis was to explore innovative approaches for solving these difficulties while staying Si-compatible. Towards this end, carbon was added in the system at different elaboration stages by i) replacing the SiO2 interfacial layer by 3C-SiC and by ii) C-engineering of the poly-Si layer during deposition.Using Atmospheric Pressure Chemical Vapor Deposition technique, state-of-the-art poly-Si TR-layers were grown on native oxide with thickness up to few tens of µm. It was found that the resistivity of the poly-Si was not directly dependent on the average grain size. Replacing the interfacial oxide by a thin mono- or poly-SiC layer and adapting the growth process allowed reaching equivalent properties of the poly-Si with the benefit of superior thermal stability by avoiding the interfacial layer dissolution. But it is accompanied by the presence of a resistivity drop at the interface due to the conductivity of the SiC material. By doping the poly-Si with C, both the TR-layer properties and thermal stability can be improved when adequate concentration of this impurity is used. Periodic insertion of thin SiC layers inside the poly-Si led to the highest thermal stability and an increase of the layer mean resistivity while periodic resistivity reductions were observed at each SiC insertion

In order to meet the requests of the application as pixel switch and current driver in next generation active-matrix liquid crystal displays (AMLCD) and active-matrix organic light-emitting diodes (AMOLED). The materials of low temperature poly-silicon (LTPS) and metal-oxide are supposed to be the most potential material for active layer of thin-film transistors (TFTs) due to their high mobility compared to the traditional amorphous silicon TFTs. Therefore, in order to make the LTPS TFTs and metal-oxide TFTs affordable for the practical applications, the understanding of instability and reliability is critically important. In the first part, we studied the nonvolatile memory characteristics of polycrystalline-silicon thin-film-transistors (poly-Si TFTs) with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant gate induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection method to counteract programmed electrons and this method can exhibit good sustainability because the injected hot holes can remain in the nitride layer after repeated operations. On the other hand, we also investigated the degradation behavior of SONOS-TFT under off-state stress. After the electrical stress, the significant on-state degradation indicates that the interface states accompanied with hot-hole injection. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Furthermore, we also performed the identical off-state stress for the device with different memory states. The different degradation behavior under different memory states is attributed to the different overlap region of injected holes and trap states. In the second part, the degradation mechanism of indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs) caused by gate-bias stress performed in the dark and light illumination was investigated. The parallel threshold voltage indicates that charge trapping model dominates the degradation behavior under positive gate-bias stress. However, the degradation of negative gate bias stress is much slighter than the positive gate bias stress since the IGZO material is hard to induced hole inversion layer. In addition, the hole mobility is much lower than electron resulting in ignorable hole trapping effect. On the other hand, the identical positive and negative gate bias stress performed under light illumination exhibit opposite degradation behavior compared with dark stress. This degradation variation under dark and light illumination can be attributed to the effectively energy barrier variation of electron and hole trapping. Furthermore, to further investigate the light induced instability for IGZO TFTs, the device with and without a SiOx passivation were investigated under light illumination. The experiment results indicate that oxygen adsorption and desorption dominate the light induced instability for unpassivated device and the trap states caused during the passivation layer deposition process will induce apparent subthreshold photo-leakage current under light illumination. In the third part, we investigated the degradation mechanism of IGZO TFTs under hot-carrier and self-heating stress. Under hot-carrier stress, except the electron trapping induced positive Vt shift, an apparent on-current degradation behavior indicates that trap states creation. On the other hand, the identical hot-carrier stress performed in the asymmetric source/drain structure exhibits different degradation behavior compared with symmetric source/drain structure. For asymmetric structure, the strong electrical field in the I-shaped drain electrode will induce channel hot electron injection near the drain side and cause asymmetric threshold voltage degradation. In this part we also investigated the degradation behavior under self-heating stress. The apparent positive threshold voltage (Vt) shift and on-current degradation indicate that the combination of trap states generation and electron trapping effect occur during stress. The trap states generation is caused by the combination of Joule heating and the large vertical field. Moreover, the Joule heating generated by self-heating operation can enhance electron trapping effect and cause larger Vt shift in comparison with the gate-bias stress. Finally, the electrical properties and photo sensitivity of dual gate IGZO TFTs were investigated. The asymmetric electrical properties and photo sensitivity under top gate and bottom gate operation is attributed to the variation of gate control region. Furthermore, the obvious asymmetric photo sensitivity can be utilized to the In-cell touch panel technology and lower the process cost compared with the traditional a-Si TFTs due to the elimination of black matrix.