<p>In this thesis we report on the metal-mediated-thermally induced changes of the structural and optical properties of hydrogenated amorphous silicon deposited by hot-wire CVD, where aluminium and nickel were used to induce crystallization. The metal-coated amorphous silicon was subjected to a thermal annealing regime of between 150 and 520&deg / C. The structural measurements, obtained by Raman spectroscopy, show partial crystallization occurring at 350 &deg / C. At the higher annealing temperatures of 450&deg / C and 520&deg / C complete crystallization occurs. Reflection and transmission measurements in the UV-visible range were then used to extract the optical properties. By adopting the effective medium approximation a single optical model could be constructed that could successfully model material that was in different structural phases, irrespective of metal contamination. Changes in the absorption of the material in various stages of transition were confirmed with a directly measured absorption technique, and the modelled absorption closely followed the same trends This study forms part of the larger overall solar cell research project, of which the primary aim is to eventually develop a silicon solar panel that optimises the characteristics for best performance.</p>

<p>Hydrogenated amorphous silicon (a-Si:H) is second only to crystalline silicon in volume manufacturing of solar cells due to its attractive characteristics for solar panel manufacturing. These are lower manufacturing costs, and the fact that it can be deposited on any surface, and in any shape even on flexible substrates. The metal induced crystallization of hydrogenated amorphous silicon has been the subject of intense scrutiny in recent years. By combining the technology of hydrogenated amorphous silicon thin films with the superior characteristics of c-Si material, it is hoped that more efficient solar cells can be produced. In this thesis we report on the metal-mediated-thermally induced changes of the structural and optical properties of hydrogenated amorphous silicon deposited by hot-wire CVD, where aluminium and nickel were used to induce crystallization. The metal-coated amorphous silicon was subjected to a thermal annealing regime of between 150 and 520&deg / C. The structural measurements, obtained by Raman spectroscopy, show partial crystallization occurring at 350 &deg / C. At the higher annealing temperatures of 450&deg / C and 520&deg / C complete crystallization occurs. Reflection and transmission measurements in the UV-visible range were then used to extract the optical properties. By adopting the effective medium approximation a single optical model could be constructed that couldsuccessfully model material that was in different structural phases, irrespective of metal contamination. Changes in the absorption of the material in various stages of transition were confirmed with a directly measured absorption technique, and the modelled absorption closely followed the same trends This study forms part of the larger overall solar cell research project, of which the primary aim is to eventually develop a silicon solar panel that optimises the characteristics for best performance.</p>

<p>Hydrogenated amorphous silicon (a-Si:H) is second only to crystalline silicon in volume manufacturing of solar cells due to its attractive characteristics for solar panel manufacturing. These are lower manufacturing costs, and the fact that it can be deposited on any surface, and in any shape even on flexible substrates. The metal induced crystallization of hydrogenated amorphous silicon has been the subject of intense scrutiny in recent years. By combining the technology of hydrogenated amorphous silicon thin films with the superior characteristics of c-Si material, it is hoped that more efficient solar cells can be produced. In this thesis we report on the metal-mediated-thermally induced changes of the structural and optical properties of hydrogenated amorphous silicon deposited by hot-wire CVD, where aluminium and nickel were used to induce crystallization. The metal-coated amorphous silicon was subjected to a thermal annealing regime of between 150 and 520&deg / C. The structural measurements, obtained by Raman spectroscopy, show partial crystallization occurring at 350 &deg / C. At the higher annealing temperatures of 450&deg / C and 520&deg / C complete crystallization occurs. Reflection and transmission measurements in the UV-visible range were then used to extract the optical properties. By adopting the effective medium approximation a single optical model could be constructed that couldsuccessfully model material that was in different structural phases, irrespective of metal contamination. Changes in the absorption of the material in various stages of transition were confirmed with a directly measured absorption technique, and the modelled absorption closely followed the same trends This study forms part of the larger overall solar cell research project, of which the primary aim is to eventually develop a silicon solar panel that optimises the characteristics for best performance.</p>

<p>In this thesis we report on the metal-mediated-thermally induced changes of the structural and optical properties of hydrogenated amorphous silicon deposited by hot-wire CVD, where aluminium and nickel were used to induce crystallization. The metal-coated amorphous silicon was subjected to a thermal annealing regime of between 150 and 520&deg / C. The structural measurements, obtained by Raman spectroscopy, show partial crystallization occurring at 350 &deg / C. At the higher annealing temperatures of 450&deg / C and 520&deg / C complete crystallization occurs. Reflection and transmission measurements in the UV-visible range were then used to extract the optical properties. By adopting the effective medium approximation a single optical model could be constructed that could successfully model material that was in different structural phases, irrespective of metal contamination. Changes in the absorption of the material in various stages of transition were confirmed with a directly measured absorption technique, and the modelled absorption closely followed the same trends This study forms part of the larger overall solar cell research project, of which the primary aim is to eventually develop a silicon solar panel that optimises the characteristics for best performance.</p>

Philosophiae Doctor - PhD / In this thesis we report on the metal-mediated-thermally induced changes of the structural and optical properties of hydrogenated amorphous silicon deposited by hot-wire CVD, where aluminium and nickel were used to induce crystallization. The metal-coated amorphous silicon was subjected to a thermal annealing regime of between 150 and 520°C. The structural measurements, obtained by Raman spectroscopy, show partial crystallization occurring at 350 °C. At the higher annealing temperatures of 450°C and 520°C complete crystallization occurs. Reflection and transmission measurements in the UV-visible range were then used to extract the optical properties. By adopting the effective medium approximation a single optical model could be constructed that could successfully model material that was in different structural phases, irrespective of metal contamination. Changes in the absorption of the material in various stages of transition were confirmed with a directly measured absorption technique, and the modelled absorption closely followed the same trends This study forms part of the larger overall solar cell research project, of which the primary aim is to eventually develop a silicon solar panel that optimises the characteristics for best performance. / South Africa

The doctoral thesis deals with the structure and properties of the polycrystalline silicon layers deposited on the silicon wafers backside. The wafers are further used for production of semiconductor devices. This work is focused on detailed description of the layers structure and study of the gettering properties and residual stress of the layers. The main goal of this work is to develop two novel technologies. The first one leads to improvement of the temperature stability of the gettering properties of the layers, and the second one solves the deposition of the layers with pre-determined residual stress. This doctoral thesis was created with the support of the company ON Semiconductor Czech Republic, Rožnov pod Radhoštěm.

The efficiency of multicrystalline (mc) silicon solar cells depends strongly on the fraction of recombination active crystal defects. This work focuses on a systematic analysis of how the area fraction of recombination active crystal defects and thus the solar cell efficiency is af-fected by the grain structure of mc-silicon wafers, i.e. grain size, grain orientation and type of the grain boundaries between adjacent grains. For that purpose a new characterization method was developed which allows the measurement of the grain orientation and grain boundary type of full 156x156 mm² mc-silicon wafers. The results of the grain structure analysis were correlated with the etch pit density, the recombination active area fraction measured by photo-luminescence imaging, and the solar cell efficiency in order to quantify the most important features of the grain structure, which were relevant to obtain high quality mc-silicon wafer material. For the determination of the grain orientation and grain boundary type two metrology sys-tems were combined. The so-called grain detector determines the geometrical data of each grain (size and form) by a reflectivity measurement. Afterwards the wafer with the geomet-rical information of all grains is transferred into the so-called Laue Scanner. This system irra-diates each grain larger 3 mm² with white x-rays and creates a backscatter diffraction pattern (Laue pattern) for each grain. From this Laue pattern the grain orientation and the grain boundary type of neighboured grains is calculated and statistically analysed in combination with the geometrical data of the grain detector. In this work the grain structure of twelve industrially grown mc-silicon bricks, which were produced by different manufacturers, and two laboratory grown bricks were investigated. Seven of these bricks show a fine grain structure. This material named class F is considered to be typical for so-called High Performance Multi (HPM) silicon. The other bricks show a coarse-grained structure. This grain structure was called class G and corresponds to the con-ventional mc-silicon material. The results show that the grain structures of the start of the crystallization process differ sig-nificantly between class F and class G. The class F mc-silicon wafers have a uniform initial grain size (characterized by coefficient of variation CV¬KG < 2.5) and grain orientation (charac-terized by coefficient of variation CVKO < 1.5) distribution with a small mean grain size (< 4 mm²) and a high length fraction of random grain boundaries (> 60 %) in comparison to the class G wafers. Despite the totally different initial grain structure for the class F and class G bricks, the grain structure of the wafers which represent the end of the crystallization process is more or less comparable. It can be concluded that the development of the grain structure along the crystal height of the class F bricks is driven by an energy minimization due to the surface energy and the grain boundary energy, that means that the share of (111) oriented grains having the lowest surface energy and the share of ∑3 grain boundaries having the lowest interface energy increase from the start of crystallization to the end. This phenomenon could not be observed for the class G bricks, which show a decreasing ∑3 length fraction and a decreasing area fraction of {111} oriented grains. This energetically unfavourable grain structure development is not clear so far but it means another kind of energy minimization effect must exist within class G. This could be for instance the formation of dislocations. The grain structure investigations show clearly that especially the initially fine-grained struc-ture of the class F bricks, i.e. at the start of crystallization, influences beneficially the area fraction of recombination active defects and the solar cell efficiency subsequently. This ob-servation can be explained as follows. Reduced dislocation cluster formation: • The small grain sizes in combination with the low length fraction of ∑3 grain bounda-ries capture the dislocations within a grain. Dislocations are not able to move across the grain boundaries which have not the ∑3-type within moderate stress and tempera-ture fields. This prohibits the formation and expansion of large dislocation cluster. • The previously described energetically driven grain selection and the continuously in-creasing grain size from bottom to top leads to an overgrowth of grains. This means that also dislocated grains will disappear which also prohibits the formation of large dislocation cluster. Reduced possibility of dislocation formation: • Compared to the class G bricks the area fraction of {111} oriented grains is reduced. Therefore, the possibility of the formation of dislocations is reduced, because they would be activated first in {111} oriented grains taking the Schmidt factor in account which is lowest for {111} oriented grains. After the dislocation generation within a {111} oriented grain, the dislocation can move forward on 3 of 4 possible {111} slip planes which have an angle of 19.5° with regard to the growth direction. No other ori-entation has more slip planes for the dislocation movement which have an angle smaller 20° with regard to the growth direction. These arguments in combination with the high reproducibility of the characteristic initial class F structure can explain the observed low recombination active area fraction from start to end of crystallization which was smaller 5 % and especially the low variation of 2 % of the electrical active wafer area in between the class F bricks. One can also easily explain the higher recombination active area fraction up to 14 % and the large variation of 10 % between the class G bricks due to the obtained grain structure data. These differences in the recombination active area fractions are reflected in the solar cell efficiency which is 0.4 % higher for the class F bricks compared to the class G bricks. In consideration of the above mentioned reasons it is not beneficial for the industrial ingot production technology to increase the ingot height further, due to the fact that the advanta-geous initial grain structure properties of class F bricks disappear with increasing crystal height.

Flash memories are solid-state non-volatile memories. They play a vital role especially in information storage in a wide range of consumer electronic devices and applications including smart phones, digital cameras, laptop computers, and satellite navigators. The demand for high density flash has surged as a result of the proliferation of these consumer electronic portable gadgets and the more features they offer – wireless internet, touch screen, video capabilities. The increase in the density of flash memory devices over the years has come as a result of continuous memory cell-size reduction. This size scaling is however approaching a dead end and it is widely agreed that further reduction beyond the 20 nm technological node is going to be very difficult, as it would result to challenges such as cross-talk or cell-to-cell interference, a high statistical variation in the number of stored electrons in the floating gate and high leakage currents due to thinner tunnel oxides. Because of these challenges a wide range of solutions in form of materials and device architectures are being investigated. Among them is three-dimensional (3-D) flash, which is widely acclaimed as the ideal solution, as they promise the integration of long-time retention and ultra-high density cells without compromising device reliability. However, current high temperature (>600 °C) growth techniques of the Polycrystalline silicon floating gate material are incompatible with 3-D flash memory; with vertically stacked memory layers, which require process temperatures to be ≤ 400 °C. There already exist some low temperature techniques for producing polycrystalline silicon such as laser annealing, solid-phase crystallization of amorphous silicon and metal-induced crystallization. However, these have some short-comings which make them not suitable for use in 3-D flash memory, e.g. the high furnace annealing temperatures (700 °C) in solid-phase crystallization of amorphous silicon which could potentially damage underlying memory layers in 3-D flash, and the metal contaminants in metal-induced crystallization which is a potential source of high leakage currents. There is therefore a need for alternative low temperature techniques that would be most suitable for flash memory purposes. With reference to the above, the main objective of this research was to develop a novel low temperature method for growing silicon structures at ≤ 400 °C. This thesis thus describes the development of a low-temperature method for polycrystalline silicon growth and the application of the technique in a capacitor-like flash memory device. It has been demonstrated that silicon structures with polycrystalline silicon-like properties can be grown at ≤ 400 °C in a 13.56 MHz radio frequency (RF) plasma-enhanced chemical vapour deposition (PECVD) reactor with the aid of Nickel Formate Dihydrate (NFD). It is also shown that the NFD coated on the substrates, thermally decomposes in-situ during the deposition process forming Ni particles that act as nucleation and growth sites of polycrystalline silicon. Silicon films grown by this technique and without annealing, have exhibited optical band gaps of ~ 1.2 eV compared to 1.78 eV for films grown under identical conditions but without the substrate being coated. These values were determined from UV-Vis spectroscopy and Tauc plots. These optical band gaps correspond to polycrystalline silicon and amorphous silicon respectively, meaning that the films grown on NFD-coated substrates are polycrystalline silicon while those grown on uncoated substrates remain amorphous. Moreover, this novel technique has been used to fabricate a capacitor-like flash memory that has exhibited hysteresis width corresponding to charge storage density in the order of 1012 cm-2 with a retention time well above 20 days for a device with silicon films grown at 300 °C. Films grown on uncoated films have not exhibit any significant hysteresis, and thus no flash memory-like behaviour. Given that all process temperatures throughout the fabrication of the devices are less than 400 °C and that no annealing of any sort was done on the material and devices, this growth method is thermal budget efficient and meets the crucial process temperature requirements of 3-D flash memory. Furthermore, the technique is glass compatible, which could prove a major step towards the acquisition of flash memory-integrated systems on glass, as well as other applications requiring low temperature polycrystalline silicon.

In this dissertation, we investigates the electrical stress induced degradation in low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs) applied for system-on-panel (SOP), including the electrical degradations of device for switch operation in active matrix flat-panel displays, driving circuit and nonvolatile memory. Finally, we also present the reliability of LTPS TFTs applied for flexible displays. In first part, electrical degradation of conventional and pattered metal-shielding LTPS TFTs under darkened and illuminated dynamic AC stresses are investigated. Experimental results reveal that competitive mechanisms are generated in conventional LTPS TFTs during illuminated stress, namely, carrier increase and electric field weakening. This phenomenon is verified by stressing the patterned source/drain open metal-shielding LTPS TFTs, which determines that the electric field weakening dominates; conversely, the carrier increase is dominated the electrical degradation in channel open metal-shielding device under illuminated stress. In addition, an improvement in anomalous on-current and subthreshold swing (S.S.) in n-channel LTPS TFTs after positive gate bias stress are studied. These improved electric properties are due to the hole trapping at SiO2 above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the S.S.. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. Secondly, a mechanism of anomalous capacitance in p-channel LTPS TFTs was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. Besides, by fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and Thermal-Field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. In third part, in order to realize the reliability in p-channel TFTs under illuminated environment operation, the degradation of negative bias temperature instability (NBTI) with illumination effect is investigated. The generations of interface state density (Nit) are identical under various illuminated intensity DC NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap) under illumination was more significant than for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrap degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region that from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase of Ntrap degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in poly-Si bulk, affecting photosensitivity in LTPS TFTs. Besides, the transient effect assisted NBTI degradation in p-channel LTPS TFTs under dynamic stress is also presented, in which the degradation of the Ntrap becomes more significant as rise time decreases to 1 £gs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrap increase is assisted by this transient effect. Fourthly, we study the electric properties of n- and p-channel LTPS TFTs under the mechanical tensile strain. The improved on-current for tensile strained n-channel TFTs is originated form an increase in energy difference between 2- and 4-fold valleys, reducing the inter-valley scattering and further improving the carrier mobility. On the contrary, the hole mobility decreases in p-channel, suggesting the split between the light hole and heavy hole energy bands and an increase in hole population on the heavy hole energy band of poly-Si when the uniaxial tensile strain is parallel to the channel direction. In addition, the Nit and Ntrap degradations induced by NBTI for tensile strained LTPS TFTs are more pronounced than in the unstrained. Extracted density-of-states (DOS) and conduction activation energy (EA) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during the NBTI stress. Therefore, the NBTI degradation is more significant after tensile strain than in an unstrained condition. Finally, the SONOS-TFT applied to nonvolatile memory is prepared and studied. In the gate disturb stress, a parasitic capacitance and resistance in off-state region are identified as electrons trapped in the gate-insulator (GI) near the defined gate region. Meanwhile, these trapping electrons induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

科学研究費補助金 研究種目:基盤研究(A)(2) 課題番号:09355002 研究代表者:後藤 俊夫 研究期間:1997-1999年度