The Australian music industry is growing and developing yet specific information about the ways in which distribution systems develop is limited. In this study I examined the growth and change of the Australian music value chain. This includes the development of digital distribution systems and the effect that peer-to-peer technology has on system development, specifically the disintermediation between consumers and artists to the detriment of the multinational value chains. The drivers of this change are broken into social and technical elements in order to describe the growth and change occurring. The method used included a comprehensive literature review and use of secondary data from key music industry associations. The Australian music industry is a subset of the global industry and is led by foreign markets and their methods in which music content moves from the creators to the consumers. The consumption patterns of Australian music consumers are changing. The overall value of the music industry is dropping as the new digital downloads market emerges and the overall volume of sales increases; this reflects similar trends in foreign markets. CD single sales have dropped and digital single sales (in MP3 format) have increased. However, there needs to be a balance in the future development of Australian music distribution systems between the needs of music consumers and the sustainability of music companies, where there is both connectivity and steady revenue flow. There are technical elements that have caused a movement away from the traditional forms of music distribution as new technologies facilitate the change, such as Apple's iPod and broadband Internet connections. Advancement of distribution systems has increased piracy levels and the response has been the implementation of digital rights management (DRM), which prevents connectivity. There are also social elements that affect growth and change such as connectivity, or the consumers freedom to choose when, where and how to listen to their music. When music product has a restriction placed upon it its value to the consumer drops. Multinational music companies have failed to recognise the value users place on the freedom to pick and choose and have tried to control rather than to co-develop systems that meets both parties needs.

Made available in DSpace on 2010-04-20T21:00:38Z (GMT). No. of bitstreams: 4 Caio Virgilio Bueno Magano.pdf.jpg: 2608 bytes, checksum: b5a70714a999071fc1425270ace18755 (MD5) Caio Virgilio Bueno Magano.pdf.txt: 95868 bytes, checksum: 9d7fd7da02405bc294abc9b910f035ee (MD5) license.txt: 4712 bytes, checksum: 4dea6f7333914d9740702a2deb2db217 (MD5) Caio Virgilio Bueno Magano.pdf: 622476 bytes, checksum: 23bef7a31891f0ff3e8b42b57ac6e628 (MD5) Previous issue date: 2010-02-05T00:00:00Z / Esta dissertação avalia quais foram os resultados da introdução da portabilidade no mercado de telefonia móvel brasileiro procurando entender os fatores que influenciaram este processo negativamente. Ela investiga especificamente como se comportou, depois da regulação, a participação de mercado das prestadoras de serviço em diferentes localidade do país. O principal questionamento realizado é se, no momento da transição, quando os entraves econômicos percebidos pelos usuários diminuíram, a concentração de mercado caiu ou se a presença de promoções em tarifas de ligações efetuadas dentro de uma mesma rede eventualmente induziu o comportamento inverso. / This thesis evaluates what were the results of the introduction of portability in the Brazilian mobile market trying to understand what were the factors that influenced this process negatively. It specifically investigates how the market share of service providers behaved after regulation in different location of the country. The main question been made is whether, at the time of transition, when economic barriers perceived by users decreased, market concentration has fallen or if the presence of discounts on fares of calls within the same network eventually induced the opposite pattern.

1. Main Contributions made by the supplicant: This thesis proposes an Open Computing Language (OpenCL) framework to address the challenges of implementation of graph algorithms on parallel architectures and large scale graph processing. The proposed framework uses the front-end of the existing Falcon DSL compiler, andso, programmers enjoy conventional, imperative and shared memory programming style. The back-end of the framework generates implementations of graph algorithms in OpenCL to target single device architectures. The generated OpenCL code is portable across various platforms, e.g., CPU and GPU, and also vendors, e.g., NVIDIA, Intel and AMD. The framework automatically generates code for thread management and memory management for the devices. It hides all the lower level programming details from the programmers. A few optimizations are applied to reduce the execution time. The large graph processing challenge is tackled through graph partitioning over multiple devices of a single node and multiple nodes of a distributed cluster. The programmer codes a graph algorithm in Falcon assuming that the graph fits into single machine memory and the framework handles graph partitioning without any intervention by the programmer. The framework analyses the Abstract Syntax Tree (AST) generated by Falcon to find all the necessary information about communication and synchronization. It automatically generates code for message passing to hide the complexity of programming in a distributed environment. The framework also applies a set of optimizations to minimize the communication latency. The thesis reports results of several experiments conducted on widely used graph algorithms: single source shortest path, pagerank and minimum spanning tree to name a few. Experimental evaluations show that the reported results are comparable to the state-of-art non-portable graph DSLs and frameworks on a single node. Experiments in a distributed environment to show the scalability and efficiency of the framework are also described. 2. Summary of the Referees' Written Comments: Extracts from the referees' reports are provided below. A copy of the written replies to the clarifications sought by the external examiner is appended to this report. Referee 1: This thesis extends the Falcon framework with OpenCL for parallel graph processing on multi-device and multi-node architectures. The thesis makes important contributions. Processing large graphs in short time is very important, and making use of multiple nodes and devices is perhaps the only way to achieve this. Towards this, the thesis makes good contributions for easy programming, compiler transformations and efficient runtime systems. One of the commendable aspects of the thesis that it demonstrates with graphs that cannot be accommodated In the memory of a single device. The thesis is generally written well. The related work coverage is very good. The magnitude of thesis excellent for a Masters work. The experimental setup is very comprehensive with good set of graphs, good experimental comparisons with state-of-art works and good platforms. Particularly. the demonstration with a GPU cluster with multiple GPU nodes (Chapter 5) is excellent. The attempt to demonstrate scalability with 2, 4 and 8 nodes is also noteworthy. However, the contributions on optimizations are weak. Most of the optimizations and compiler transformations are straight-forward. There should be summary observations on the results in Chapter 3, especially given that the results are mixed and don't quite clearly convey the clear advantages of their work. The same is the case with multi-device results in chapter 4, where the results are once again mixed. Similarly, the speedups and scalability achieved with multiple nodes are not great. The problem size justification in the multi-node results is not clear. (Referee 1 also indicates a couple of minor changes to the thesis). Referee 2: The thesis uses the OpenCL framework to address the problem of programming graph algorithms on distributed systems. The use of OpenCL ensures that the generated code is platform-agnoistic and vendor-agnoistic. Sufficient experimentation with large scale graphs and reasonable size clusters have been conducted to demonstrate the scalability and portability of the code generated by the framework. The automatically generated code is almost as efficient as manually written code. The thesis is well written and is of high quality. The related work section is well organized and displays a good knowledge of the subject matter under consideration. The author has made important contributions to a good publication as well. 3. An Account of the Open Oral Examination: The oral examination of Ms. Parita Patel took place during 10 AM and 11AM on 27th November 2017, in the Seminar Hall of the Department of Computer Science and Automation. The members of the Oral Examination Board present were, Prof. Sathish Vadhiyar, external examiner and Prof. Y. N. Srikant, research supervisor. The candidate presented the work in an open defense seminar highlighting the problem domain, the methodology used, the investigations carried out by her, and the resulting contributions documented in the thesis before an audience consisting of the examiners, some faculty members, and students. Some of the questions posed by the examiners and the members of the audience during the oral examination are listed below. 1. How much is the overlap between Falcon work and this thesis? Response: We have used the Falcon front end in our work. Further, the existing Falcon compiler was useful to us to test our own implementation of algorithms in Falcon. 2. Why are speedup and scalability not very high with multiple nodes? Response: For the multi-node architecture, we were not able to achieve linear scalability because, with the increase in number of nodes, communication cost increases significantly. Unless the computation cost in the nodes is significant and is much more than the communication cost, this is bound to happen. 3. Do you have plans of making the code available for use by the community? Response: The code includes some part of Falcon implementation (front-end parsing/grammar) also. After discussion with the author of Falcon, the code can be made available to the community. 4. How can a graph that does not fit into a single device fit into a single node in the case of multiple nodes? Response: Single node machine used in the experiments of “multi-device architecture” contains multiple devices while each node used in experiments of “multi-node architecture” contains only a single device. So, the graph which does not fit into single-node-single-device memory can fit into single-node-multi-device after partitioning. 5. Is there a way to permit morph algorithms to be coded in your framework? Response: Currently, our framework does not translate morph algorithms. Supporting morph algorithms will require some kind of runtime system to manage memory on GPU since morph algorithms add and remove the vertices and edges to the graph dynamically. This can be further explored in future work. 6. Is it possible to accommodate FPGA devices in your framework? Response: Yes, we can support FPGA devices (or any other device that is compatible for OpenCL) just by specifying the device type in the command line argument. We did not work with other devices because CPU and GPU are generally used to process graph algorithms. The candidate provided satisfactory answers to all the questions posed and the clarifications sought by the audience and the examiners during the presentation. The candidate's overall performance during the open defense and the oral examination was very satisfactory to the oral examination board. 4. Certificate of Corrections and Changes: All the necessary corrections and changes suggested by the examiners have been made in the thesis and these have been verified by the members of the oral examination board. The thesis has been recommended for acceptance in its revised form. 5. Final Recommendation: In view of the recommendations of the referees and the satisfactory performance of the candidate in the oral examination, the oral examination board recommends that the thesis of Ms. ParitaPatel be accepted for the award of the M.Sc(Engg.) Degree of the Institute. Response to the comments by the external examiner on the M.Sc(Engg.) thesis “Compilation of Graph Algorithms for Hybrid, Cross-Platform, and Distributed Architectures” by Parita Patel 1. Comment: The contributions on optimizations are weak. Response: The novelty of this thesis is to make the Falcon platform agnostic, and additionally process large scale graphs on multi-devices of a single node and multi-node clusters seamlessly. Our framework performs similar to the existing frameworks, but at the same time, it targets several types of architectures which are not possible in the existing works. Advanced optimizations are beyond the scope of this thesis. 2. Comment: The translation of Falcon to OpenCL is simple. While the translation of Falcon to OpenCL was not hard, figuring out the details of the translation for multi-device and multi-node architectures was not simple. For example, design of implementations for collection, set, global variables, concurrency, etc., were non-trivial. These designs have already been explained in the appropriate places in the thesis. Further, such large software introduced its own intricacies during development. 3. Comment: Lines between Falcon work and this work are not clear. Response: Appendix-A shows the falcon implementation of all the algorithms which we used to run the experiments. We compiled these falcon implementations through our framework and subsequently ran the generated code on different types of target architectures and compared the results with other framework's generated code. These falcon programs were written by us. We have also used the front-end of the Falcon compiler and this has already been stated in the thesis (page 16). 4. Comment: There should be a summary of observations in chapter 3. Response: Summary of observations have been added to chapter 3 (pages 35-36), chapter 4 (page 46), and chapter 5 (page 51) of the thesis. 5. Comment: Speedup and scalability achieved with multiple nodes are not great. Response: For the multi-node architecture, we were not able to achieve linear scalability because, with the increase in number of nodes, communication cost increases significantly. Unless the computation cost in the nodes is significant and is much more than the communication cost, this is bound to happen. 6. Comment: It will be good to separate the related work coverage into a separate chapter. Response: The related work is coherent with the flow in chapter 1. It consists of just 4.5 pages and separating it into a separate chapter would make both (rest of) chapter 1 and the new chapter very small. Therefore, we do not recommend it. 7. Comment: The code should be made available for use by the community. Response: The code includes some part of Falcon code (front-end parsing/grammar) also. After discussion with the author of Falcon, the code can be made available to the community. 8. Comment: Page 28: Shouldn’t the else part be inside the kernel? Response: There was some missing text and a few minor changes in Figure 3.14 (page 28) which have been incorporated in the corrected thesis. 9. Comment: Figure 4.1 needs to be explained better. Response: Explanation for Figure 4.1 (pages 38-39) has been added to the thesis. 10. Comment: The problem size justification in the multi-node results is not clear. Response: Single node machine used in the experiments of “multi-device architecture” contains multiple devices while each node used in experiments of “multi-node architecture” contains only a single device. So, the graph which does not fit into single-node-single-device memory can fit into single-node-multi-device after partitioning. Name of the Candidate: Parita Patel (S.R. No. 04-04-00-10-21-14-1-11610) Degree Registered: M.Sc(Engg.) Department: Computer Science & Automation Title of the Thesis: Compilation of Graph Algorithms for Hybrid, Cross-Platform and Graph algorithms are abundantly used in various disciplines. These algorithms perform poorly due to random memory access and negligible spatial locality. In order to improve performance, parallelism exhibited by these algorithms can be exploited by leveraging modern high performance parallel computing resources. Implementing graph algorithms for these parallel architectures requires manual thread management and memory management which becomes tedious for a programmer. Large scale graphs cannot fit into the memory of a single machine. One solution is to partition the graph either on multiple devices of a single node or on multiple nodes of a distributed network. All the available frameworks for such architectures demand unconventional programming which is difficult and error prone. To address these challenges, we propose a framework for compilation of graph algorithms written in an intuitive graph domain-specific language, Falcon. The framework targets shared memory parallel architectures, computational accelerators and distributed architectures (CPU and GPU cluster). First, it analyses the abstract syntax tree (generated by Falcon) and gathers essential information. Subsequently, it generates optimized code in OpenCL for shared-memory parallel architectures and computational accelerators, and OpenCL coupled with MPI code for distributed architectures. Motivation behind generating OpenCL code is its platform-agnostic and vendor-agnostic behavior, i.e., it is portable to all kinds of devices. Our framework makes memory management, thread management, message passing, etc., transparent to the user. None of the available domain-specific languages, frameworks or parallel libraries handle portable implementations of graph algorithms. Experimental evaluations demonstrate that the generated code performs comparably to the state-of-the-art non-portable implementations and hand-tuned implementations. The results also show portability and scalability of our framework.

La portabilité des données personnelles des consommateurs est encore une question récente dans le domaine de la protection de la vie privée. Parmi les normes étudiées dans ce travail, le Règlement Général sur la Protection des Données a été le premier à aborder la portabilité et le concept qu'il a établi guide d'autres législations, telles que celles du Québec et du Canada. L'objet de ce mémoire est de discuter de la mise en œuvre de ce nouveau droit lié aux technologies de l'information et à la circulation des données personnelles, en se concentrant sur les consommateurs et les entreprises qui feront partie de la portabilité des données personnelles. Cette étude est divisée en trois chapitres. Le premier explore les concepts de base liés au droit à la portabilité, tels que les données personnelles, les données liées à la relation avec le consommateur, la conceptualisation de la portabilité, son application et des exemples d'opérabilité. Le deuxième chapitre décrit comment le droit à la portabilité a été adopté dans la législation de l'Union européenne, dans le projet de loi fédérale actuellement examiné par le Parlement canadien et dans la nouvelle loi québécoise. La troisième traite de la mise en œuvre de la portabilité. Elle aborde le point de vue des entreprises, le maintien de la portabilité en tant que droit, le besoin de régulation, l'interopérabilité et les risques. / The portability of consumers' personal data is still a recent subject in the field of privacy protection. Among the standards studied in this work, the General Data Protection Regulation was the first to address portability and the concept it established guides other legislation, such as that of Quebec and Canada. The purpose of this dissertation is to discuss the implementation of this new right linked to information technologies and the circulation of personal data, focusing on the consumers and businesses that will be affected by the portability of personal data. This study is divided into three chapters. The first explores the basic concepts related to the right to portability, such as personal data, data related to the relationship with the consumer, the conceptualisation of portability, its application and examples of operability. The second chapter describes how the right to portability has been adopted in European Union legislation, in the federal bill currently before the Canadian Parliament and in the new Quebec law. The third deals with the implementation of portability. It addresses the point of view of businesses, the maintenance of portability as a right, the need for regulation, interoperability, and risks.

The thesis deals with the numbering plan, PBX, tariffs, draft disable tariff system and its possible extensions. Within numbering plans work deals with shapes of national and international figures, describes different types of these numbers, description of the structure and definition of fields, including the length of these fields. Within countries and regions of the Czech Republic are given individual prefix for both fixed and mobile networks. There are mentioned special shapes that are different in length compared to standard types. All these types of shapes are listed according to ITU-T. Within the exchanges are given generation switches, PBXs use within the telephone network and a description of the selected functions. Furthermore, there are kinds of pricing and options of valuation call. The work contains a description of automated acconting system, according to the principle of work of the program and a description of the individual steps and functions that thanks to the cooperation process individually each calls, convert numbers to international form, assigns the call tariff and appreciate the call according to the tariff. Finally, there are described possible extensions of this automated acconting system.

The implementation of portable electroencephalography (EEG) systems has been known to be complex. During ambulation, the integrity of recorded EEG signals is often impaired by motion artifacts and the time and effort required to set up the system is excessive. The use of single-channel EEG systems with dry, active electrodes (AEs) for signal acquisition is a topic of current interest. AEs are electrodes which have integrated bioamplifier circuitry and are known to be less susceptible to motion artifacts and environmental interference. In this report, the design of an AE preamplifier for the purpose of improving single-channel EEG recordings is presented. Initially, a thorough literature review was performed, exploring the available knowledge and state-of-the-art technology. Thereafter, the design specifications were set and the appropriate topology and circuit design techniques were selected to maximize the amplifier’s performance. Ultimately, three different preamplifier topologies were designed and their performance compared with one another as well as with established medical device standards and state-of-the-art AEs. The results of one preamplifier showed comparable performance with state-of-the-art AEs. Therefore, this topology was selected for a deep analysis and physical layout design. The layout of the selected preamplifier was designed and its parasitics extracted. The post layout performance of the design proved to be comparable to the schematic level performance, with a CMRR of 153dB, IRNV of 0.89µVRMS and an electrode offset tolerance of 450mV. The preamplifier design presented in this report has proven to be comparable with state-of-the-art AE preamplifiers and demonstrates potential for the advancement of AE performance in single-channel EEG systems. / Implementeringen av bärbara elektroencefalografisystem (EEG) har varit känd för att vara komplex. Vid rörelse påverkas ofta reliabiliteten av de inspelade EEGsignalerna av rörelseartefakter samt av att tiden och det arbete som krävs för att ställa in systemet blir överdrivet lång. Användandet av singelkanals EEG-system, med torra aktiva elektroder (AE) under inspelningen, är ett aktuellt ämne. En AE är en elektrod som har en integrerad bioförstärkarkrets och är känd för att vara både mindre mottaglig för rörelseartefakter och för störning från omgivningen. I denna rapport presenteras utformningen av en AE-förförstärkare för singelkanals EEGinspelningar. Inledningsvis utfördes en grundlig litteraturöversikt där den rådande kunskapen och toppmoderna tekniken undersöktes. Därefter bestämdes designspecifikationerna, lämpliga topologier samt kretsdesigntekniker, för att maximera förstärkarens prestanda. Slutligen konstruerades tre olika förstärkares topologier och deras prestanda jämfördes med varandra liksom med etablerade medicin tekniska standarder och toppmoderna AE. Resultaten av en förförstärkare visade sig ha jämförbar prestanda med toppmoderna AE. Därför valdes denna topologi ut för en djupanalys och för fysisk layoutkonstruktion. Layouten för den valda förförstärkaren utformades och dess parasiter extraherades. Utformningen av postlayouten visade sig vara jämförbar med prestanda på en schematisk nivå, med en CMRR på 153dB, IRNV på 0.89µVRMS och en elektrodoffsettolerans på 450mV. Förförstärkarens design som presenteras i denna rapport har visat sig vara jämförbar med toppmoderna AE-förförstärkare och visar potential till framsteg för AEprestanda i singelkanals EEG-system