This master thesis describes a system capable of real-time characterization of power performance and power quality of wind turbines, based mainly on the IEC 61400-21 and IEC 61400-12-1 standards. To verify the performance of the proposed system, a fixed-speed wind turbine was emulated in laboratory. As experimental results, the power performance and power quality characteristics of the given wind turbine are shown. / Esta dissertação de mestrado descreve um sistema capaz de realizar em tempo real a caracterização da qualidade de energia e desempenho de potência de turbinas eólicas, com base nas normas IEC 61400-21 e IEC 61400-12-1. Para verificação do funcionamento do sistema proposto, uma turbina eólica de velocidade fixa foi emulada em laboratório. Como resultados experimentais, são apresentadas as características de qualidade de energia e desempenho de potência calculados para a turbina eólica em estudo.

Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. Dynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations. The research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.

Submitted by Edileide Reis (leyde-landy@hotmail.com) on 2013-04-15T14:00:08Z No. of bitstreams: 1 Irena Carneiro Martins.pdf: 492924 bytes, checksum: adb1e49b063679e6e3940d77a1771caa (MD5) / Approved for entry into archive by Rodrigo Meirelles(rodrigomei@ufba.br) on 2013-05-09T17:39:33Z (GMT) No. of bitstreams: 1 Irena Carneiro Martins.pdf: 492924 bytes, checksum: adb1e49b063679e6e3940d77a1771caa (MD5) / Made available in DSpace on 2013-05-09T17:39:33Z (GMT). No. of bitstreams: 1 Irena Carneiro Martins.pdf: 492924 bytes, checksum: adb1e49b063679e6e3940d77a1771caa (MD5) Previous issue date: 2008 / Este trabalho tratou de investigar as origens do instituto da limitação da responsabilidade dos sócios e estabelecer a importância de tal limitação – a partir da harmonização entre os princípios constitucionais de proteção aos direitos sociais e os princípios – igualmente constitucionais – da livre iniciativa do qual decorre também o princípio da preservação da empresa. De modo semelhante buscou se estabelecer a importância da delimitação da responsabilização dos administradores que não possuem vínculo societário com as empresas por eles administradas tanto no âmbito legislativo quanto judicial. Nesse contexto buscou-se demonstrar – para além dos prejuízos – a ociosidade da aplicação da teoria da desconsideração da personalidade jurídica em face dos remédios jurídicos já existentes no ordenamento jurídico brasileiro para as ocasiões em que se verifique a ocorrência de fraude simulação e prática dos atos ultra vires. Advoga-se neste trabalho a possibilidade de se buscar a preservação da empresa atendendo ao chamado do devido processo legal e – simultaneamente– ao chamado da busca pela satisfação do crédito ou reparação de prejuízos ensejados mediante o abuso. da pessoa jurídica seja por administrador seja por sócio fortalecendo assim os caros institutos da segurança jurídica e previsibilidade das decisões judiciais. Concorrem também para a consagração do tudo quanto aqui exposto uma redução do ativismo judicial que se verifica em preterimento de direitos processuais que gozam de status constitucional como os da ampla defesa e do contraditório. Além disso buscou-se evidenciar a necessidade de diálogo entre Direito – através dos magistrados – e Economia a partir da compreensão por parte daqueles dos reflexos de sua atuação para o desenvolvimento econômico e consequentemente para o desenvolvimento social. Nesse tocante acredita-se útil a colaboração que pode ser fornecida pela Psicanálise a partir de uma das três instâncias do aparelho psíquico: o superego no entendimento do Judiciário como superego da sociedade. / Salvador

Large flexible software systems tend to incur “bloat”, here defined as the runtime overhead induced by the accumulation of excess functionality and objects. Removing bloat is hard as these overheads are a side-effect of the same trends that have fuelled software growth. Even defining and measuring bloat is non-trivial, as software doesn’t come with built-in labels that indicate which portions of computation are necessary for a given application and which lead to bloat. Much progress has been made in novel analysis tools that aid (human experts in) the process of finding bloat by highlighting signs of excessive activity and data flow. However, there has been very little research focus on understanding the connection between sources of bloat and its system level implications. In particular, excess resource usage due to bloat could be a significant source of power-performance inefficiencies, but the relation between bloat and energy efficient design remains unexplored. In order to systematically devise effective mechanisms for reaping power-performance benefits through bloat mitigation, we require a deeper insight into exactly when excess features can originate bloat, when the resource overheads of bloat are most pronounced and when bloat matters for power performance. This dissertation explores the problem of software bloat and its energy efficiency implications from multiple perspectives to develop a better understanding of these connections. First, we establish the need for a whole systems perspective in assessing potential energy efficiency benefits of bloat reduction, based on a systematic empirical and analytical study that highlights a curious interplay between bloat, energy proportionality and system bottlenecks. Second, we present a novel static analysis algorithm to perform an automated code transformation for object reuse that mitigates bloat involving the generation of excess temporary objects within loops. Third, we introduce the idea of concern augmented program analysis (CAPA), to identify sources of bloat due to excess features; the technique uses externally supplied information about program concerns and their properties as an abstraction of underlying intent. Fourth, as an early diagnostic aid, we use a statistical topic model to automatically discover latent concerns from source code statements and then correlate these latent concerns with resource usage properties that vary at statement granularity. The statistical model has a built-in sensitivity to the context of individual statements so that it can discover even diffused concerns without any apriori concern information. Together, our findings show that presence of excess features, in itself, may not lead to (runtime) bloat, unless these features have some structural interaction with essential features. Further, the overheads due to such structural interactions, in turn, may not cause substantial bloat in the resource consumption of a long running (server) application unless incurred repeatedly during program execution. Finally, even such bloated resource usage has a pronounced impact on power-performance only if it affects a system bottleneck or a hardware resource that has a high degree of energy proportionality and consumes a high fraction of power compared to the other system resources. We conclude that energy wastage due to bloat need not be an inevitable consequence of over-provisioning flexibility. Instead, the extent to which excess features result in runtime bloat and poor power-performance is determined by certain characteristics of the program structure and of the underlying hardware system --these represent potential control points that could be exercised to develop principled design approaches for mitigating bloat without sacrificing flexibility or productivity.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.