The unabated continuation of the Moore's law has allowed the doubling of the number of transistors per unit area of a silicon die every 2 years or so. At the same time, an increasing demand on consumer electronics and computing equipments to run sophisticated applications has led to an unprecedented complexity of hardware designs. These factors have necessitated the abstraction level of design-entry of hardware systems to be raised beyond the Register-Transfer-Level (RTL) to Electronic System Level (ESL). However, power envelope on the designs due to packaging and other thermal limitations, and the energy envelope due to battery life-time considerations have also created a need for power/energy efficient design. The confluence of these two technological issues has created an urgent need for solving two problems: (i) How do we enable a power-aware design flow with a design entry point at the Electronic System Level? (ii) How do we enable power aware High Level Synthesis to automatically synthesize RTL implementation from ESL? This dissertation distinguishes itself by addressing the following two issues: (i) Since power/energy consumption of electronic systems largely depends on implementation details, and high-level models abstract away from such details, power/energy estimation at such levels has not been addressed thoroughly. (ii) A lot of work has been done in applying various techniques on control-data-flow graphs (CDFG) to find power/area/latency pareto points during behavioral synthesis. However, high level C-based functional models of various compute-intensive components, which could be easily synthesized as co-processors, have many opportunities to reduce power. Some of these savings opportunities are traditional such as clock-gating, operand-isolation etc. The exploration of alternate granularities of these techniques with target applications in mind, opens the door for traditional power reduction opportunities at the high-level. This work therefore concentrates on the aforementioned two areas of inadequacy of hardware design methodologies. Our proposed solutions include utilizing ESL simulation traces and mapping those to lower abstraction levels for power estimation, derivation of statistical power models using regression based learning for power estimation at early design stages, etc. On the HLS front, techniques that insert the power saving features during the synthesis process using exploration of granularity and scope of clock-gating, sequential clock-gating are proposed. Finally, this work shows how to marry two domains, that is estimation and reduction. In this regard, a power model is proposed, which helps in predicting power savings obtained using clock-gating and further guiding HLS to selectively insert clock-gating. / Ph. D.

This paper investigates the potential of mathematical algorithms, based on the principles of data mining, applied to data from a local power grid to identify customers with large fluctuations in their power curves. A literature study was performed to facilitate algorithm formation. The data provided by the local grid owners, Falkenberg Energi AB, was analysed in MATLAB and two novel algorithms was created. The results show that, by normalizing all the data, it is possible to find and select customers with large fluctuations in their power curves. Key performance indicators were then used to determine which algorithm performed better. One of the algorithms performed better in all tested indicators and was used to create a list with interesting customers to Falkenberg Energi AB. The conclusion of the study shows that the proposed algorithms can be applied on a local power grid to select customers, but more research is needed to validate these methods. The conclusion also indicates that a reduction of the power peaks, at the identified customers, mainly affect the local power grid and not the power supply from the overhead regional power grid.

No description available.

The energy consumption in the world continues to increase, which makes energy saving measures important. In Sweden, where buildings account for a large part of total energy use, heat exchangers in ventilation are important to reduce energy consumption. However, Sweden's winters are often cold over large parts of the country, causing frost in the heat exchanger and high and uneven heating power requirements for ventilation units. The heating system in the building is required to manage the biggest power demand that may arise. From the ventilation unit, the greatest heating power requirement is arise in the event of frost conditions, as the power requirement from the heating coil increases during defrosting. By installing an accumulator tank together with the ventilation unit, the power requirement can be evened out. Power requirement for three different scenarios where the storage tank is used has been calculated. By using thermodynamic equations and measurements from Swegon counter flow heat exchanger results were accomplished. Optimal defrosting cycle times were evaluated by theory and equations. Other defrosting methods have been calculated to be compared to the solution with the accumulator tank. In a case with 600 litres per seconds supply and exhaust air flow, outdoor temperature at -10 ° C, the power requirement to the unit could be reduced by 67 % using an accumulator tank. An accumulator tank with a volume of 73 litres was required. By using an accumulator tank with the ventilation unit, investment costs could decrease by approximately 18 000 SEK when district heating is used as energy source. However, the solution with the storage tank will not be able to reduce district heating costs more than reduced flow cost for the district heating. If a heat pump I used approximately 95 000 SEK in investment cost could be saved when using an accumulator tank. Electricity cost could also be reduced but not much. Compared to other defrosting methods, the solution with accumulator tank will require the lowest power requirement for the ventilation unit, heat recover  most energy in the heat exchanger and at the same time create an even heat power requirement at frost conditions. / Energianvändningen i världen fortsätter öka vilket gör energisparåtgärder viktiga. I Sverige där byggnader står för en stor del av den totala energianvändningen är värmeväxlare inom ventilation viktiga för att minska energiförbrukningen. Dock är Sveriges vintrar ofta kalla över stora delar av landet vilket orsakar frostproblem i värmeväxlaren och högt och ojämnt värmeeffektbehov till ventilationsaggregat. Byggnadens värmesystem måste dimensioneras efter det största effektbehov som kan uppstå. Från ventilationsaggregatet sker det största värmeeffektbehovet vid frostförhållanden eftersom effektbehovet från värmebatteriet ökar vid avfrostning. Genom att installera en ackumulatortank tillsammans med ventilationsaggregatet skulle effektbehovet kunna jämnas ut. Effektbehov för tre olika scenarion där ackumulatortank används har beräknats. Det skedde genom användande av termodynamiska ekvationer och mätningar från Swegons motströmsvärmeväxlare. Tiden för hur lång avfrostningscykel som är optimal har utvärderas genom teori och ekvationer. Andra avfrostnings metoder har beräknats för att kunna jämföras med lösningen med ackumulatortank. I ett fall med till-och frånluftflöde på 600 l/s och dimensionerande utomhustemperatur på -10 °C kunde effektbehovet fram till aggregatet minskas med 67% genom att använda en ackumulatortank. En ackumulatortank med volymen 73 liter krävdes. Genom att använda en ackumulatortank tillsammans med ventilationsaggregatet kunde investeringskostnaden kunna minskamed cirka 18000 kr när fjärrvärme används som energikälla. Lösningen med ackumulatortank kommer dock inte kunna minska fjärrvärmekostnaden mer än att minska eventuell flödeskostnad för fjärrvärmen. Vid användande av bergvärmepump skulle cirka 95000 kr i investeringskostnad kunna sparas vid användande av ackumulatortank. Eleffektkostnaden kunde även minskas men relativt lite. Jämfört med andra avfrostningsmetoder kommer en lösning med ackumulatortank kräva lägst effektbehov till ventilationsaggregatet, återvinna mest energi i värmeväxlaren och samtidigt skapa ett jämt värmeeffektbehov under frostförhållanden.

Green computing techniques aim to reduce the power foot print of modern embedded devices with particular emphasis on processors, the power hot-spots of these devices. In this thesis we propose compiler-driven and profile-driven optimizations that reduce power consumption in a modern embedded processor. We show that these optimizations reduce power consumption in functional units and memory subsystems with very low performance loss. We present three new techniques to reduce power consumption in processors, namely, transition aware scheduling, leakage reduction in data caches using criticality analysis, and dynamic power reduction in data caches using locality analysis of data regions. A novel instruction scheduling technique to address leakage power consumption in functional units is proposed. This scheduling technique, transition aware scheduling, is motivated by idle periods that arise in the utilization of functional units during program execution. A continuously large idle period in a functional unit can be exploited to place the unit in low power state. This novel scheduling algorithm increases the duration of idle periods without hampering performance and drives power gating in these periods. A power model defined with idle cycles as a parameter shows that this technique saves up to 25% of leakage power with very low performance impact. In modern embedded programs, data regions can be classified as critical and non-critical. Critical data regions significantly impact the performance. A new technique to identify such data regions through profiling is proposed. This technique along with a new criticality based cache policy is used to control the power state of the data cache. This scheme allocates non-critical data regions to low-power cache regions, thereby reducing leakage power consumption by up to 40% without compromising on the performance. This profiling technique is extended to identify data regions that have low locality. Some data regions have high data reuse. A locality based cache policy based on cache parameters like size and associativity is proposed. This scheme reduces dynamic as well as static power consumption in the cache subsystem. This optimization reduces 25% of the total power consumption in the data caches without hampering the execution time. In this thesis, the problem of power consumption of a program is decoupled from the number of processor cores. The underlying architecture model is simplified to abstract away a variety of processor scenarios. This simplified model can be scaled up to be implemented in various multi-core architecture models like Chip Multi-Processors, Simultaneous Multi-Threaded Processors, Chip Multi-Threaded Processors, to name a few. The three techniques proposed in this thesis leverage underlying hardware features like low power functional units, drowsy caches and split data caches. These techniques reduce power consumption of a wide range of benchmarks with low performance loss.

Power dissipated during scan testing is becoming increasingly important for today’s very complex sequential circuits. It is shown that the power dissipated during test mode operation is in general higher than the power dissipated during functional mode operation, the test mode average power may sometimes go upto 3x and the peak power may sometimes go upto 30x of normal mode operation. The power dissipated during the scan operation is primarily due to the switching activity that arises in scan cells during the shift and capture operation. The switching in scan cells propagates to the combinational block of the circuit during scan operation, which in turn creates many transition in the circuit and hence it causes higher dynamic power dissipation. The excessive average power dissipated during scan operation causes circuit damage due to higher temperature and the excessive peak power causes yield loss due to IR-drop and cross talk. The higher peak power also causes the thermal related issue if it last for sufficiently large number of cycles. Hence, to avoid all these issues it is very important to reduce the peak power during scan testing. Further, in case of multi-module SoC testing the reduction in peak power facilitates in reducing the test application time by scheduling many test sessions parallelly. In this dissertation we have addressed all the above stated issues. We have proposed three different techniques to deal with the excessive peak power dissipation problem during test. The first solution proposes an efficient graph theoretic methodology for test vector reordering to achieve minimum peak power supported by the given test vector set. Three graph theoretic problems are formulated and corresponding algorithms to solve the problems are proposed. The proposed methodology also minimizes average power for the given minimum peak power. Further, a lower bound on minimum achievable peak power for a given test set is defined. The results on several benchmarks show that the proposed methodology is able to reduce peak power significantly. To address the peak power problem during scan test-cycle (the cycle between launch and capture pulse) we have proposed a scan chain reordering technique. A new formulation for scan chain reordering as TSP (Traveling Sales Person) problem and a solution is proposed. The experimental results show that the proposed methodology is able to minimize considerable amount of peak power compared to the earlier proposals. The capture power (power dissipated during capture cycle) problem in testing multi chip module (MCM) is also addressed. We have proposed a methodology to schedule the test set to reduce capture power. The scheduling algorithm consist of reordering of test vector and insertion of idle cycle to prevent capture cycle coincidence of scheduled cores. The experimental results show the significant reduction in capture power without increase in test application time.

While FPGAs provide flexibility for performing high performance DSP functions, they consume a significant amount of power. Often, a large portion of the dynamic power is wasted on unproductive signal glitches. Reducing glitching reduces dynamic energy consumption. In this study, retiming is used to reduce the unproductive energy wasted in signal glitches. Retiming can reduce energy by up to 92%. Evaluating energy consumption is an important part of energy reduction. In this work, an activity rate-based power estimation tool is introduced to provide FPGA architecture independent energy estimations at the gate level. This tool can accurately estimate power consumption to within 13% on average. This activation rate-based tool and retiming are combined in a single algorithm to reduce energy consumption of FPGA designs at the gate level. In this work, an energy evaluation metric called energy area delay is used to weigh the energy reduction and clock rate improvements gained from retiming against the area and latency costs. For a set of benchmark designs, the algorithm that combines retiming and the activation rate-based power estimator reduces power on average by 40% and improves clock rate by 54% for an average 1.1x area cost and a 1.5x latency increase.

Dans le contexte énergétique français actuel, deux principaux enjeux émergent. À court terme, des pointes de consommation électrique croissantes sont observées les dernières années pendant la période hivernale. Ces pointes sont fortement liées au chauffage électrique et ont des conséquences économiques, environnementales et sociales importantes. Dans un long terme, des objectifs environnementaux ambitieux ont été fixés au niveau national et européen, nécessitant la technologie de stockage thermique et une gestion efficace de l'environnement bâti. Les Matériaux à Changement de Phase (MCP) ainsi que les dispositifs de type échangeurs thermiques offrent des résultats promettant grâce au stockage thermique et le déplacement des consommations. Dans ce cadre, l’objectif de cette thèse est de développer des solutions de déplacement des consommations énergétiques qui prennent en compte le confort thermique des occupants et la qualité de l’air intérieur. Pour ce faire, deux outils sont nécessaires: un échangeur thermique expérimental (prototype) et un modèle numérique capable de simuler son comportement. L'échangeur contient du MCP macroencapsulé (paraffine) et est conçu de manière à faciliter son intégration dans un système de ventilation. Il a comme but de décaler la consommation due au chauffage électrique vers la période hors pointe. Le dispositif a été caractérisé expérimentalement lors des cycles thermiques complets (charge et décharge) en utilisant une quantité importante de capteurs. Il a ensuite été couplé à une cellule expérimentale, afin de tester des stratégies de contrôle préliminaires. Le modèle numérique est basé sur la discrétisation spatiale et l’établissement du bilan de chaleur des couches considérées, la méthode de la capacité thermique apparente, ainsi que l’utilisation des différences finies. Après validation à l’aide des données expérimentales, le modèle a été utilisé pour optimiser la performance de l'échangeur. Plusieurs paramètres ont été étudiés, y compris les dimensions de l'échangeur, la quantité et les propriétés du MCP, en cherchant la configuration avec le compromis optimal entre la chaleur emmagasinée et le temps nécessaire pour la charge et la décharge. Le modèle numérique a été couplé à un modèle de simulation du bâtiment et un logement de 80m2 a été conçu pour la mise en oeuvre et l'évaluation des stratégies de contrôle, en investiguant différents scénarios sur une période hivernal d’un mois. Les scénarios varient avec une complexité croissante, d'abord en considérant l’effacement énergétique et le confort thermique, ensuite en ajoutant le prix final de la consommation électrique et enfin en prenant compte la qualité de l'air intérieur avec la présence d'une famille de quatre personnes. 6 Cette étude a été menée dans le cadre d'un projet financé par l'Agence National de la Recherche (Stock-Air: ANR-Stock-E) et a également été soutenu par le ministère de l'Ecologie, du Développement durable et de l'Energie. / Considering the current French energy context, two major challenges are emerging. In the short term, significant peak power consumption has been observed in the past few years during the winter season. These peaks are strongly linked to electrical space heating and have important economic, environmental and social implications. In the long term, ambitious environmental goals have been set at national and European levels, requiring thermal storage technology and efficient management of the built environment. As part of the solution, Phase Change Materials (PCM) and heat exchanger applications offer promising results through thermal storage and load shifting techniques. Within this framework, the objective of this thesis is to develop load shifting solutions which also take into account the thermal comfort of the occupants and the indoor air quality. To achieve this, two tools were necessary: an experimental heat exchanger unit (prototype) and a numerical model that accurately simulates its behavior. The exchanger contains macroencapsumated PCM (paraffin) and is conceived in a way that facilitates its integration in a ventilation system. It is aimed to shift space heating electrical consumption from peak to off-peak period. The unit was experimentally characterized, using an important amount of sensors through full thermal cycles (charging and discharging) and was coupled to an experimental test cell, which led to the testing of preliminary control strategies. The numerical model is based on the heat balance approach and the apparent heat capacity method, using finite differences for differential equation solution under Matlab/Simulink environment. After validation with experimental data, the model was used to optimize the performance of the exchanger. Several parameters were investigated, including heat exchanger dimensions, PCM quantity and properties, seeking the configuration with the optimal compromise between stored heat and the time needed for the charging / discharging process. The numerical model was coupled to a building simulation model and an 80m2 dwelling was conceived for control strategies implementation and evaluation, by investigating different scenarios over a one- month winter period. The scenarios vary with increasing complexity, first considering load shifting and thermal comfort, then adding the final price of electricity consumption and finally taking into account the indoor air quality with the presence of a four-person family. This study has been conducted within the framework of a project funded by the French National Research Agency (Stock-Air: ANR-Stock-E) and was also financially supported by the French Ministry of Sustainable Development.

Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode. / Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.