This Master’s report presents the research leading to the development of a low power Wireless Sensor Network (WSN) and a discussion of an implementation of the WSN. This report assesses the power reduction techniques further by reviewing their influences upon functionality, throughput, latency, and data reliability. The software techniques were implemented on evaluation boards and actual performance gains were observed. Furthermore, the report provides insight into the selection of the processor, wireless protocol, and WSN architecture by comparing other options in regards to the power reduction, functionality, and data reliability. The architecture of the WSN consists of four sensor nodes, and a backbone router connected to a PC. The sensor nodes contain an application processor and a radio processor. The application processor is a Texas Instruments MSP430F5438 which is located on an MSP-EXP430F5438 evaluation board. The radio processor is a NIVIS Versa Node 210 that is located on a VS210 development board. The wireless protocol investigated is the ISA100.11a. / text

There has been a constant need for low power techniques to achieve high performance at the lowest possible power dissipation. Lots of works have been done to achieve this target. These works have focused on the different aspects of power reduction. One of these aspects of power saving is Dynamic power reduction. This thesis work is focused on this aspect of power saving by reducing the unnecessary transitioning in the circuit. To achieve this, new method called data gating, is proposed here which stops unnecessary toggling in the circuit using different forms of gating mechanisms. This thesis is organized as follows; first chapter is about the low power design of CMOS circuits. That chapter covers the sources of power dissipation in ICs as well as the techniques that have been used to minimize the power consumption. Second chapter talks more about dynamic power consumption. Techniques used for reducing dynamic power consumption through reduction in switching activities are mentioned in that chapter. Also the new technique, Data Gating, to reduce dynamic power is proposed in second chapter. Third chapter talks about simulation setup, tools used for simulation. Results obtained from different simulations are presented in that chapter. Fourth Chapter is about the analysis of simulation results. It also outlines some possible limitations of the proposed method as well as certain points that need to be considered before applying new technique. Fifth and final chapter summarizes the conclusion and possible future work that can be done to enhance the proposed technique, Data Gating. / text

Three high performance circuits for a low power supply DRAM¡¦s are presented in this thesis. First, a modified multi-stage sense amplifier is proposed, that utilizes the auxiliary transmission gate and charge recycling technique. The auxiliary NMOS transistor of the multi-stage sense amplifier is replaced by the transmission gate to improve the sensing speed. In addition, the charge recycling technique is used to reduce the power dissipation of multi-stage sense amplifier. It improves the sensing time by 6.1ns (24.4%) compared to that of the conventional multi-stage sense amplifier and the power saving percentage of 25.6% compared to that of the conventional one. Second, an improved Standby Power Reduction (SPR) Circuit is reported. The capacitor boosting technique is utilized in our proposed Static Current Cut-off Standby Power Reduction (SCCSPR) Circuit, which turns off the always-on MOS transistor of SPR circuit. The power consumption is 30.9% reduced by our design compared to that of the conventional SPR circuit. Third, an improved voltage doubler is developed. The indirect switch is utilized in our proposed circuit, it provides larger gate source bias applied to the PMOS pass transistor. Thus, the current drivability is arisen and the pumping speed is improved as well. In the 2V supply voltage, the pumping speed of our modified voltage doubler is arisen about 18.6% compared to that of the conventional voltage doubler. These high performance circuits in this thesis are applied in a 1-Kbit DRAM circuits. A data access time of 36ns and total power consumption 52.58mW are attained when the supply voltage is 2V. The access time of 10.3ns (22.2%) and power consumption of 6.44mW (11%) are reduced compared to that of the conventional DRAM.

Global on-chip interconnects in deep sub-micron CMOS present challenges in satisfying delay constraints in the presence of noise and dramatic temperature variations, while minimizing energy consumption due to leakage and static power. Although repeaters are typically used to reduce delay and maintain signal integrity in long interconnects, they introduce significant area, power (both dynamic and leakage), delay, noise and design overhead as well as exacerbating variations due to their local power supply noise and temperature. Current-Sensing is an alternative to repeaters that transfers signals with no intermediate circuits by sensing current rather than voltage at the end of a long interconnect. Among the current sensing circuits, Differential Current-Sensing (DCS), which uses conventional CMOS inverters to drive differential signal, is preferred because of its high common-mode noise rejection. The DCS circuit is fast and simple in layout compared to repeater insertion despite significant static and leakage power which remains a barrier for broad application. Temperature variation throughout the chip also causes the timing uncertainty on interconnects to increase. This thesis addresses current-sensing interconnect circuit design in several aspects. First, it provides an improved differential current-sensing circuit called the differential leakage-aware sense amplifier (DLASA), that uses local power gating that results in 39.6% reduced leakage and static power compared to conventional differential current sensing. Secondly, thermal impact on interconnect is studied and temperature sensitivity is analyzed for interconnect circuits. Theoretical analysis is discussed as a base design guideline, then accurate simulation based experiments in 65nm, 45nm and 32nm CMOS technologies are used for verification from 25OC to 150OC. Thus this project provides a view of the year of technology toward 2013.

Η αυξημένη ζήτηση για λήψη δεδομένων της πολυμεσικής Broadcast/Multicast υπηρεσίας από τους χρήστες των δικτύων κινητών επικοινωνιών τρίτης γενιάς, απαιτεί την κατανάλωση μεγάλων ποσών ισχύος για την εξυπηρέτησή τους, ενώ η διαθέσιμη ισχύς των δικτύων είναι περιορισμένη. Με στόχο, την αποδοτικότερη χρήση των ποσών ισχύος του συστήματος, και την εξυπηρέτηση με τον τρόπο αυτό περισσότερων χρηστών, αλλά με ταυτόχρονη διατήρηση της ποιότητας της υπηρεσίας, έχουν προταθεί κάποιες τεχνικές οι οποίες οδηγούν σε μείωση της εκπεμπόμενης ισχύος. Στην διπλωματική αυτή εργασία, αναλύονται αρχικά τα δίκτυα τρίτης γενιάς καθώς και η πολυμεσική Broadcast/Multicast υπηρεσία. Στη συνέχεια, περιγράφονται όλες οι τεχνικές που έχουν προταθεί, και με την χρήση κατάλληλου λογισμικού προσομοιώνεται μία από τις τεχνικές αυτές. Τα ποσοστά μείωσης ισχύος, που προκύπτουν ως αποτελέσματα της προσομοίωσης αυτής, αποδεικνύουν την σημαντική μείωση της εκπεμπόμενης ισχύος που μπορεί να επιτευχθεί με την χρήση της τεχνικής αυτής. / The increased demand for data download of the Multimedia Broadcast/Multicast service by the users of the mobile third generation networks, requires the consumption of large power amounts for their service, while the available power of the networks is limited. With the view of more efficient usage of the system power resources, and the service in this way of more users, but with the simultaneous maintenance of the quality of service, they have been proposed some techniques which lead to the reduction of the transmitted power. In this work, initially, the third generation networks and the Multimedia Broadcast/Multicast service are being analyzed. Afterwards, all the techniques that they have been proposed are being described, and with the usage of the appropriate software, one of these techniques is being simulated. The power reduction percentages, that they come of as a result of this simulation, prove the significant transmitted power reduction, which can be achieved with the usage of this technique.

A complexidade dos sistemas embarcados está crescendo devido à agregação de funcionalidades em um único dispositivo eletrônico e a heterogeneidade de comportamento das aplicações que compõe estas funcionalidades agrava este cenário. Atualmente, os projetistas de processadores estão buscando outro paradigma de computação para ser empregado neste tipo de dispositivo. A aceleração da execução dos processadores Superescalares está estagnada, a extração do paralelismo no modelo Von- Neumann está chegando ao limite teórico. Arquiteturas Dataflow são uma possível solução para este problema, entretanto a área disponível em silício da tecnologia atual não comporta a implementação deste tipo de arquitetura. Arquiteturas reconfiguráveis aparecem como uma solução viável para a exploração de um alto nível de paralelismo, sendo factível a implementação deste tipo de arquitetura nas atuais tecnologias CMOS. Entretanto, a inserção do hardware reconfigurável ocasiona uma elevação na área ocupada e, conseqüentemente, na potência consumida. É neste cenário que este trabalho se insere. Uma arquitetura reconfigurável foi escolhida como estudo de caso, sendo acoplada a um processador MIPS R3000. Além disto, foi desenvolvida uma ferramenta que, automaticamente, constrói um hardware otimizado através da exploração de recursos necessários para obter o máximo grau de paralelismo da execução de um conjunto de aplicações. O acoplamento desta ferramenta com a técnica de tradução binária utilizada nesta arquitetura reconfigurável provê uma exploração estática/dinâmica. Estática pelo ponto de vista de construção de uma nova unidade reconfigurável otimizada em área antes da fabricação do chip. Dinâmica devido a adaptabilidade da execução do tradutor binário, após a fabricação da unidade otimizada gerada pela ferramenta, a unidade otimizada alcança as mesmas acelerações demonstradas na unidade não otimizada com uma menor área ocupada e potência consumida. Além disto, neste trabalho é demonstrado o impacto na potência consumida pelo sistema fornecido por uma técnica de desligamento de blocos da unidade funcional reconfigurável. Assim, as explorações da área e do consumo de potência demonstraram ser factível a inserção da arquitetura reconfigurável proposta em um dispositivo embarcado. / Nowadays, the large amount of complex and heterogeneous functionalities that are found on a single embedded device has driven designers to create novel solutions to increase the performance of embedded processors and, at the same time, maintain power dissipation as low as possible. While the instruction level parallelism exploitation is reaching the theoretical limit, Dataflow architectures are seen as a reasonable proposal to solve this problem. However, even for near future CMOS technologies, the price to pay for using such architectures is still too high. Reconfigurable architectures could be a possible solution to explore higher-levels of parallelism, and their deployment on current CMOS technologies is feasible. However, the fusion of a reconfigurable hardware with a general-purpose processor still implies in a high area overhead, besides the elevated power consumption. The proposal of this work is to couple static and dynamic techniques to achieve a low-power, high performance reconfigurable architecture that can show speed ups for several heterogeneous applications with the minimum possible area overhead. At design time, the static exploitation produces a new reconfigurable unit optimized in area. Thanks to the proposed dynamic reconfiguration mechanism, the optimized reconfigurable unit provides acceleration and low power dissipation, adapting to the different degrees of parallelism available in the application, and accelerating applications not foreseen at design time.

A complexidade dos sistemas embarcados está crescendo devido à agregação de funcionalidades em um único dispositivo eletrônico e a heterogeneidade de comportamento das aplicações que compõe estas funcionalidades agrava este cenário. Atualmente, os projetistas de processadores estão buscando outro paradigma de computação para ser empregado neste tipo de dispositivo. A aceleração da execução dos processadores Superescalares está estagnada, a extração do paralelismo no modelo Von- Neumann está chegando ao limite teórico. Arquiteturas Dataflow são uma possível solução para este problema, entretanto a área disponível em silício da tecnologia atual não comporta a implementação deste tipo de arquitetura. Arquiteturas reconfiguráveis aparecem como uma solução viável para a exploração de um alto nível de paralelismo, sendo factível a implementação deste tipo de arquitetura nas atuais tecnologias CMOS. Entretanto, a inserção do hardware reconfigurável ocasiona uma elevação na área ocupada e, conseqüentemente, na potência consumida. É neste cenário que este trabalho se insere. Uma arquitetura reconfigurável foi escolhida como estudo de caso, sendo acoplada a um processador MIPS R3000. Além disto, foi desenvolvida uma ferramenta que, automaticamente, constrói um hardware otimizado através da exploração de recursos necessários para obter o máximo grau de paralelismo da execução de um conjunto de aplicações. O acoplamento desta ferramenta com a técnica de tradução binária utilizada nesta arquitetura reconfigurável provê uma exploração estática/dinâmica. Estática pelo ponto de vista de construção de uma nova unidade reconfigurável otimizada em área antes da fabricação do chip. Dinâmica devido a adaptabilidade da execução do tradutor binário, após a fabricação da unidade otimizada gerada pela ferramenta, a unidade otimizada alcança as mesmas acelerações demonstradas na unidade não otimizada com uma menor área ocupada e potência consumida. Além disto, neste trabalho é demonstrado o impacto na potência consumida pelo sistema fornecido por uma técnica de desligamento de blocos da unidade funcional reconfigurável. Assim, as explorações da área e do consumo de potência demonstraram ser factível a inserção da arquitetura reconfigurável proposta em um dispositivo embarcado. / Nowadays, the large amount of complex and heterogeneous functionalities that are found on a single embedded device has driven designers to create novel solutions to increase the performance of embedded processors and, at the same time, maintain power dissipation as low as possible. While the instruction level parallelism exploitation is reaching the theoretical limit, Dataflow architectures are seen as a reasonable proposal to solve this problem. However, even for near future CMOS technologies, the price to pay for using such architectures is still too high. Reconfigurable architectures could be a possible solution to explore higher-levels of parallelism, and their deployment on current CMOS technologies is feasible. However, the fusion of a reconfigurable hardware with a general-purpose processor still implies in a high area overhead, besides the elevated power consumption. The proposal of this work is to couple static and dynamic techniques to achieve a low-power, high performance reconfigurable architecture that can show speed ups for several heterogeneous applications with the minimum possible area overhead. At design time, the static exploitation produces a new reconfigurable unit optimized in area. Thanks to the proposed dynamic reconfiguration mechanism, the optimized reconfigurable unit provides acceleration and low power dissipation, adapting to the different degrees of parallelism available in the application, and accelerating applications not foreseen at design time.

A complexidade dos sistemas embarcados está crescendo devido à agregação de funcionalidades em um único dispositivo eletrônico e a heterogeneidade de comportamento das aplicações que compõe estas funcionalidades agrava este cenário. Atualmente, os projetistas de processadores estão buscando outro paradigma de computação para ser empregado neste tipo de dispositivo. A aceleração da execução dos processadores Superescalares está estagnada, a extração do paralelismo no modelo Von- Neumann está chegando ao limite teórico. Arquiteturas Dataflow são uma possível solução para este problema, entretanto a área disponível em silício da tecnologia atual não comporta a implementação deste tipo de arquitetura. Arquiteturas reconfiguráveis aparecem como uma solução viável para a exploração de um alto nível de paralelismo, sendo factível a implementação deste tipo de arquitetura nas atuais tecnologias CMOS. Entretanto, a inserção do hardware reconfigurável ocasiona uma elevação na área ocupada e, conseqüentemente, na potência consumida. É neste cenário que este trabalho se insere. Uma arquitetura reconfigurável foi escolhida como estudo de caso, sendo acoplada a um processador MIPS R3000. Além disto, foi desenvolvida uma ferramenta que, automaticamente, constrói um hardware otimizado através da exploração de recursos necessários para obter o máximo grau de paralelismo da execução de um conjunto de aplicações. O acoplamento desta ferramenta com a técnica de tradução binária utilizada nesta arquitetura reconfigurável provê uma exploração estática/dinâmica. Estática pelo ponto de vista de construção de uma nova unidade reconfigurável otimizada em área antes da fabricação do chip. Dinâmica devido a adaptabilidade da execução do tradutor binário, após a fabricação da unidade otimizada gerada pela ferramenta, a unidade otimizada alcança as mesmas acelerações demonstradas na unidade não otimizada com uma menor área ocupada e potência consumida. Além disto, neste trabalho é demonstrado o impacto na potência consumida pelo sistema fornecido por uma técnica de desligamento de blocos da unidade funcional reconfigurável. Assim, as explorações da área e do consumo de potência demonstraram ser factível a inserção da arquitetura reconfigurável proposta em um dispositivo embarcado. / Nowadays, the large amount of complex and heterogeneous functionalities that are found on a single embedded device has driven designers to create novel solutions to increase the performance of embedded processors and, at the same time, maintain power dissipation as low as possible. While the instruction level parallelism exploitation is reaching the theoretical limit, Dataflow architectures are seen as a reasonable proposal to solve this problem. However, even for near future CMOS technologies, the price to pay for using such architectures is still too high. Reconfigurable architectures could be a possible solution to explore higher-levels of parallelism, and their deployment on current CMOS technologies is feasible. However, the fusion of a reconfigurable hardware with a general-purpose processor still implies in a high area overhead, besides the elevated power consumption. The proposal of this work is to couple static and dynamic techniques to achieve a low-power, high performance reconfigurable architecture that can show speed ups for several heterogeneous applications with the minimum possible area overhead. At design time, the static exploitation produces a new reconfigurable unit optimized in area. Thanks to the proposed dynamic reconfiguration mechanism, the optimized reconfigurable unit provides acceleration and low power dissipation, adapting to the different degrees of parallelism available in the application, and accelerating applications not foreseen at design time.

En la presente Tesis se proponen soluciones para aliviar el alto coste, en rendimiento y consumo, de las comunicaciones intra-chip a través de los alambres globales. En concreto, se propone utilizar redes heterogéneas que permiten una mejor adaptación a las necesidades de los diferentes tipos de mensajes de coherencia.Nuestra primera propuesta consiste en dividir las respuestas con datos en un mensaje corto crítico, enviado usando enlaces de baja latencia, y un mensaje largo no crítico enviado usando enlaces de bajo consumo. La segunda propuesta utiliza la compresión de direcciones en el contexto de una red de interconexión heterogénea que permite la compresión de mayoría de los mensajes críticos en unos pocos bytes, siendo transmitidos usando enlaces de muy baja latencia. Finalmente, se explora el uso de la prebúsqueda por hardware para aliviar los problemas derivados de las altas latencias de los enlaces globales. / In this thesis we propose different ways to alleviate the high cost, in terms of performance and power consumption, of the intra-chipcommunications using global wires. In particular, we considerheterogeneous networks to obtain a better match between thenetwork-on-chip and the needs of the different types of coherencemessages.Our first contribution proposes the partitioning of reply messages with data into a short critical message, which is sent using low-latency links, as well as a long non-critical message sent using low-power links. The second contribution exploits the use of address compression in the context of a heterogeneous interconnect to allow most of the critical messages to be compressed in a few bytes and transmitted using very low latency links. Finally, we explore the use of heterogeneous networks in the context of hardware prefetching to alleviate the problems caused by high latencies of global links.

Le sujet de cette thèse est la réduction de consommation dans les circuits digitaux, et plus particulièrement dans ce cadre les méthodes basées sur la réduction de la fréquence de commutation moyenne, au niveau transistor. Ces méthodes sont structurelles, au sens où elles ne sont pas liées à l’optimisation des caractéristiques physique du circuit mais sur la structure de l’implémentation logique, et de ce fait parfaitement indépendantes de la technologie considérée. Nous avons développé dans ce cadre deux méthodes nouvelles. La première est basée sur l’optimisation de la structure de la partie combinatoire d’un circuit pendant la synthèse logique. La seconde est centrée sur la partie séquentielle du circuit. Elle consiste en la recherche de conditions permettant de détecter qu’un sous-circuit devient inactif, de sorte à pouvoir désactiver ce sous-circuit en coupant la branche correspondante de l’arbre d’horloge, et utilise des méthodes formelles pour prouver que la fonctionnalité du circuit n’en serait pas affectée. / The topic of this thesis are methods for power reduction in digital circuits by reducing average switching on the transistor level. These methods are structural in the sense that they are not related to tuning physical properties of the circuitry but to the internal structure of the implemented logic an d therefore independent on the particular technology. We developed two novel methods. One is based on optimizing the structure of the combinatorial part of a circuit during synthesis. The second method is focused on sequential part of the circuit. It looks for clock gating conditions that can be used to disable idle parts of a circuit and uses formal methods to prove that the function of the circuit will not be altered.