Reconfigurable circuits (Field Programmable Gate Arrays (FPGAs)) for accelerating applications have been a key technology for many years. Thus, the world’s leading data center operators and providers of cloud infrastructures, namely Microsoft, IBM, and soon Amazon, are using FPGAs on their application platforms. The central question of this contribution is how FPGAs can be virtualized for a flexible and dynamic deployment in cloud infrastructures. In addition to the virtualization of FPGA resources, service models for the provision of virtualized FPGAs are developed and embedded into a resource management system in order to evaluate the cloud system’s behaviour. The objective of this work is not to build a cloud architecture, but rather to examine selected aspects of cloud systems with regard to the integration of reconfigurable hardware. The FPGAs are not only virtualized but, unlike in many other projects, the entire system and the application are taken into account. As a result, the vFPGAs are used dynamically and adaptively at different locations and topologies in the cloud architecture, depending on the user’s requirements. Furthermore, a prototypical implementation of a cloud system has been developed, and evaluated in several projects. The virtualization using state-of-the-art FPGAs has shown that the establishment of homogenous environments is possible. The Migration of a partial FPGA context is also possible with current FPGA architectures, but is associated with high costs in form of hardware resources. Furthermore, a simulation was carried out to determine whether virtualization and migration, could contribute to a more efficient utilization of resources in a larger cloud system or impair the service level agreement. In summary, both the developed virtualization and the possibility of a migration make it possible to reduce the amount of necessary resources in a modern cloud system. / Rekonfigurierbare Schaltkreise wie Field Programmable Gate Arrays (FPGAs) stellen seit Jahren für viele Unternehmen eine Schlüsseltechnologie zur Hintergrundbeschleunigung von Anwendungen und Cloud- Diensten dar. Als weltweit führende Betreiber von Rechenzentren und Anbieter von Cloud-Infrastrukturen setzten mittlerweile Microsoft, IBM und demnächst auch Amazon in ihren Systemen FPGAs auf Anwendungsebene ein, um sowohl die Rechenleistung zu erhöhen als auch die Verlustleistung und damit die Betriebskosten zu reduzieren. Ebenso stellt die Erhöhung der Zugangssicherheit durch Nutzung von FPGAs einen weiteren bedeutenden Aspekt dar. Die zentrale Fragestellung dieser Arbeit besteht darin, wie FPGAs durch Virtualisierung effizient auf der Anwendungsebene nutzbar gemacht werden können. Das Ziel besteht darin, die FPGAs wie andere Komponenten flexibel und dynamisch in der Cloud einzusetzen. Um ein Cloud-System mit FPGAs evaluieren zu können, werden zunächst Servicemodelle für eine Bereitstellung der virtualisierten FPGAs entwickelt und in eine Ressourcenverwaltung eingebettet. Ziel der Arbeit ist hierbei nicht der Aufbau einer Cloud-Architektur selbst, sondern vielmehr die Untersuchung ausgewählter Aspekte mit Hinblick auf die Integration rekonfigurierbarer Hardware in eine Cloud. Dabei wird die klassische System-Virtualisierung auf die rekonfigurierbare Hardware übertragen, um eine Abstraktion vom physischen FPGA zu erreichen und diesen möglichst effizient auslasten zu können. Das Ziel besteht hierbei darin, mehrere unabhängige, nebenläufig arbeitende Nutzerkerne auf demselben physischen FPGA zu realisieren und durch Migration auf andere Rechenknoten zu übertragen sowie von der physischen Größe und der Architektur des FPGAs zu abstrahieren. Dabei wird nicht nur der FPGA virtualisiert, sondern – anders als bei der Mehrzahl vergleichbarer Arbeiten – das Gesamtsystem und der Einsatzzweck berücksichtigt. Ein prototypisch entwickeltes Cloud-System wurde im Rahmen mehrerer Projekte evaluiert. Durch diese prototypische Umsetzung wird nachgewiesen, dass eine FPGA-Virtualisierung auf aktuellen FPGAs möglich ist und welche Kosten dazu erforderlich sind. Ebenso zeigt sich, dass aufgrund bestimmter fester Strukturen eine Etablierung von homogenen Bereichen notwendig ist, um die Migration eines partiellen FPGA-Kontextes zu ermöglichen und eine effiziente Lastverteilung in der Cloud zu realisieren. Die prototypische Implementierung zeigt, dass eine Migration mit aktuellen FPGA-Architekturen möglich, aber mit Kosten in Form von FPGA-Ressourcen verbunden ist. Des Weiteren wird mittels Simulation untersucht, ob die in einem komplexen Anwendungsszenario angewendete Migration auch in einem größeren Cloud-System zu einer effizienteren Auslastung der Ressourcen beitragen kann. Zusammenfassend ist sowohl durch die entwickelte Virtualisierung als auch durch die Möglichkeit einer Migration die Einsparung von Hardware-Ressourcen und somit auch Energie in einem modernen Cloud-System möglich.

The Frequency Disturbance Recorder (FDR) is a specialized data acquisition device designed to monitor fluctuations in the overall power system. The device is designed such that it can be attached by way of a standard wall power outlet to the power system. These devices then transmit their calculated frequency data through the public internet to a centralized data management and storage server. By distributing a number of these identical systems throughout the three major North American power systems, Virginia Tech has created a Frequency Monitoring Network (FNET). The FNET is composed of these distributed FDRs as well as an Information Management Server (IMS). Since frequency information can be used in many areas of power system analysis, operation and control, there are a great number of end uses for the information provided by the FNET system. The data provides researchers and other users with the information to make frequency analyses and comparisons for the overall power system. Prior to the end of 2004, the FNET system was made a reality, and a number of FDRs were placed strategically throughout the United States. The purpose of this thesis is to present the elements of a new generation of FDR hardware design. These elements will enable the design to be more flexible and to lower reliance on some vendor specific components. Additionally, these enhancements will offload most of the computational processing required of the system to a commodity PC rather than an embedded system solution that is costly in both development time and financial cost. These goals will be accomplished by using a Field Programmable Gate Array (FPGA), a commodity off-the-shelf personal computer, and a new overall system design. / Master of Science

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / As the rates and numbers of serial telemetry data streams increase, the cost of timely, efficient and robust distribution of those streams increases faster. Without alternatives to traditional pointto- point serial distribution, the complexity of the infrastructure will soon overwhelm potential benefits of the increased stream counts and rates. Utilization of multiplexing algorithms in Field- Programmable Gate Arrays (FPGA), coupled with universally available Internet Protocol (IP) switching technology, provides a low-latency, time-data correlated multi-stream distribution solution. This implementation has yielded zero error IP transport and regeneration of multiple serial streams, maintaining stream to stream skew of less than 10 nsec, with end-to-end latency contribution of less than 15 msec. Adoption of this technique as a drop-in solution can greatly reduce the costs and complexities of maintaining pace with the changing serial telemetry community.

ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / Multiple-Input Multiple-Output (MIMO) systems have at least two transmitting antennas, each generating unique signals. However some applications may require three, four, or more transmitting devices to achieve the desired system performance. This paper describes the design of a scalable MIMO transmitter, based on field programmable gate array (FPGA) technology. Each module contains a FPGA, and associated digital-to-analog converters, I/Q modulators, and RF amplifiers needed to power one of the MIMO transmitters. The system was designed to handle up to a 10 Mbps data rate, and transmit signals in the unlicensed 2.4 GHz ISM band.

No description available.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design was assembled incorporating a routing architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final chip is presented and discussed followed by a discussion on testing. This thesis demonstrates the successful implementation of a fully functional reprogrammable logic device using RSFQ circuitry.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The availability of high density FPGAs has made the use of soft-core processors an attractive proposition for the low volume space market. Soft-core processors combine the power of programmable logic with the ease of use of a conventional processor to provide a highly customisable solution. However, the SRAM FPGAs used as implementation platform are especially susceptable to radiation induced single event upsets, due to the sensitivity of their configuration memory. To safely use these processors in a space environment requires the modification of the processor to safely mitigate these effects. This thesis presents the process followed to develop and test a fault tolerant implementation of an 8-bit PicoBlaze soft-core processor on a Xilinx Spartan-3 SRAM FPGA. A thorough investigation was made into the available methods that can be used to mitigate single event upsets, in order to identify the most suitable ones. Guidelines for the application of SEU mitigation techniques to SRAM FPGAs were proposed. A single event upset simulator was designed and constructed to compare the different techniques. It mimics SEUs by injecting errors into the configuration memory of an FPGA. The results of error injection were used to develop a PicoBlaze implementation with limited overhead, while it still offers a high degree of error mitigation. Three different designs were tested by proton irradiation to verify the protection afforded by the mitigation techniques. It was found that protected designs were more robust. The cross-section of the FPGA was also determined, which can be used with the SEU simulator to predict the dynamic cross-section of designs. The work contained in this thesis demonstrates the use of open-source intellectual property with commercial-off-the-shelf components to develop a robust component for use in the miniature spacecraft market.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited. This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community. This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum. To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.

Master of Science / Department of Electrical Engineering / Dwight Day / Power consumption has become a large concern in many systems including portable electronics and supercomputers. Creating efficient hardware that can do more computation with less power is highly desirable. This project proposes a possible avenue to complete this goal by hardware accelerating a conjugate gradient solve using a Field Programmable Gate Array (FPGA). This method uses three basic operations frequently: dot product, weighted vector addition, and sparse matrix vector multiply. Each operation was accelerated on the FPGA. A power monitor was also implemented to measure the power consumption of the FPGA during each operation with several different implementations. Results showed that a decrease in time can be achieved with the dot product being hardware accelerated in relation to a software only approach. However, the more memory intensive operations were slowed using the current architecture for hardware acceleration.