The research presented in this thesis leverages silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology to develop microwave front-end electronics for active phased-array antennas. The highly integrated electronics will reduce costs and improve the feasibility of snow measurements from airborne and space-borne platforms. Chapter 1 presents the motivation of this research, focusing on the technological needs of snow measurement missions. The fundamentals and benefits of SiGe HBTs and phased-array antennas for these missions are discussed as well. Chapter 2 discusses SiGe power amplifier design considerations for radar systems. Basic power amplifier design concepts, power limitations in SiGe HBTs, and techniques for increasing the output power of SiGe HBT PAs are reviewed. Chapter 3 presents the design and characterization of a robust medium power X-band SiGe power amplifier for integration into a SiGe transmit/receive module. The PA design process applies the concepts presented in Chapter 2. A detailed investigation into measurement-to-simulation discrepancies is outlined as well. Chapter 4 discusses the development and characterization of a single-chip X-band SiGe T/R module for integration into a very thin, lightweight active phased array antenna panel. The system-on-package antenna combines the high performance and integration potential of SiGe technologies with advanced substrates and packaging techniques to develop a high performance scalable antenna panel using relatively low-cost materials and silicon-based electronics. The antenna panel presented in this chapter will enable airborne SCLP measurements and advance the technology towards an eventual space-based SCLP measurement instrument that will satisfy a critical Earth science need. Finally, Chapter 5 provides concluding remarks and discusses future research directions.

Inkjet-printing is a technology which has for the last decade been exploited to fabricate flexible RF components such as antennas and planar circuit elements. However, the limitations of feature size and single layer fabrication prevented the demonstration of compact, and high efficiency RF components operating above 10 GHz into the mm-Wave regime which is critical to silicon integration and fully-printed modules. To overcome these limitations, a novel vertically-integrated fully inkjet-printed process has been developed and characterized up to the mm-Wave regime which incorporates up to five highly conductive metal layers, variable thickness dielectric layers ranging from 200 nm to 200 um, and low resistance through-layer via interconnects. This vertically-integrated inkjet printed electronics process, tagged VIPRE, is a first of its kind, and is utilized to demonstrate fully additive RF capacitors, inductors, antennas, and RF sensors operating up to 40 GHz. In this work, the first-ever fully inkjet printed multi-layer RF devices operating up to 40 GHz with high-performance are demonstrated, along with a demonstration of the processing techniques which have enabled the printing of multi-layer RF structures with multiple metal layers, and dielectric layers which are orders of magnitude thicker than previoulsy demonstrated inkjet-printed structures. The results of this work show the new possibilities in utilizing inkjet printing for the post-processing of high-efficiency RF inductors, capacitors, and antennas and antenna arrays on top of silicon to reduce chip area requirements, and for the production of entirely printed wireless modules.

The objective of this research is to develop an understanding of the trade-offs between performance and reliability in sub 100-nm silicon-on-insulator (SOI) CMOS technologies. Such trade-offs can be used to demonstrate high performance reliable circuits in scaled technologies. Several CMOS reliability concerns such as hot-carrier stress, ionizing irradiation damage, RF stress, temperature effects, and single-event effects are studied. These reliability mechanisms can cause temporary or permanent damage to the semiconductor device and to the circuits using them. Several improvements are made to the device layout and process to achieve optimum performance. Parasitics are shown to play a dominant role in the performance and reliability of sub 100-nm devices. Various techniques are suggested to reduce these parasitics, such as the use of the following: a) optimum device-width, b) optimum gate-finger to gate-finger spacing, c) optimum source/drain metal contact spacing, and d) floating-body/body-contact. The major contributions from this research are summarized as follows: 1) Role of floating-body effects on the performance and reliability of sub 100-nm CMOS-on-SOI technologies is investigated for the first time [1], [2]. It is demonstrated through experimental data and TCAD simulations that floating-body devices have improved RF performance but degraded reliability compared to body-contacted devices. 2) Floating-body effects in a cascode core is studied. Cascode cores are demonstrated to achieve much larger reliability lifetimes than a single device. A variety of cascode topologies are studied to achieve the trade-o s between performance and reliability for high-power applications [2]. 3) The use of body-contact to modulate the performance of devices and single-poledouble- throw (SPDT) switches is studied. The SPDT switch performance is shown to improve with a negative body-bias. 4) The impact of device width on the RF performance and reliability is studied. Larger width devices are shown to have greater degradation, posing challenging questions for RF design in strained-Si technologies [3]. 5) A novel study showing the e ect of source/drain metal contact spacing and gate-finger to gate-finger spacing on the device RF performance is carried out. Further, the impact of above on the hot-carrier, RF stress, and total-dose irradiation tolerance is studied [3], [4]. 6) Latchup phenomenon in CMOS is shown to be possible at cryogenic temperatures (below 50 K), and its consequences are discussed [5]. 7) A time-dependent device degradation model has been developed in technology computer aided design (TCAD) to model reliability in CMOS and SiGe devices. 8) The total-dose irradiation tolerance and hot-carrier reliability of 32-nm CMOSon- SOI technology is reported for the first time. The impact of HfO2 based gate dielectric on the performance and reliability is studied [6]. 9) The impact of technology scaling from 65-nm to 32-nm on the performance and reliability of CMOS technologies is studied [6]. 10) Cryogenic performance and reliability of 45-nm nFETs is investigated. The RF performance improves significantly at 77 K. The hot-carrier device reliability is shown to improve at low temperatures in short-channel CMOS technologies.

Thesis (M. App. Sc.)--Carleton University, 2005. / Includes bibliographical references (p. 79-82). Also available in electronic format on the Internet.

No description available.

The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (μn) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and iii device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.

This thesis discusses the investigation and utilization of a new promising thin-film material, liquid crystal polymer (LCP), for microwave and millimeter-wave (mm-wave [>30 GHz]) components and packages. The contribution of this research is in the determination of LCP's electrical and mechanical properties as they pertain to use in radio frequency (RF) systems up to mm-wave frequencies, and in evaluating LCP as a low-cost substrate and packaging material alternative to the hermetic materials traditionally desired for microwave circuits at frequencies above a few gigahertz (GHz). A study of LCP's mm-wave material properties was performed. Resonant circuit structures were designed to find the dielectric constant and loss tangent from 2-110 GHz under both ambient and elevated temperature conditions. Several unique processes were developed for the realization of novel multilayer LCP-based RF circuits. These processes include thermocompression bonding with tight temperature control (within a few degrees Celsius), precise multilayer alignment and patterning, and LCP laser processing with three different types of lasers. A proof-of-concept design that resulted from this research was a dual-frequency dual-polarization antenna array operating at 14 and 35 GHz. Device characterization such as mechanical flexibility testing of antennas and seal testing of packages were also performed. A low-loss interconnect was developed for laser-machined system-level thin-film LCP packages. These packages were designed for and measured with both RF micro-electromechanical (MEM) switches and monolithic microwave integrated circuits (MMICs). These research findings have shown LCP to be a material with uniquely attractive properties/capabilities for vertically integrated, compact multilayer LCP circuits and modules.

The potential of implementing subthreshold radio frequency circuits in deep sub-micron CMOS technology was investigated for developing low-power front-ends for wireless personal area network (WPAN) applications. It was found that the higher transconductance to bias current ratio in weak inversion could be exploited in developing low-power wireless front-ends, if circuit techniques are employed to mitigate the higher device noise in subthreshold region. The first fully integrated subthreshold low noise amplifier was demonstrated in the GHz frequency range requiring only 260 μW of power consumption. Novel subthreshold variable gain stages and down-conversion mixers were developed. A 2.4 GHz receiver, consuming 540 μW of power, was implemented using a new subthreshold mixer by replacing the conventional active low noise amplifier by a series-resonant passive network that provides both input matching and voltage amplification. The first fully monolithic subthreshold CMOS receiver was also implemented with integrated subthreshold quadrature LO (Local Oscillator) chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage amplification, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling were combined to lower the total power consumption to 2.6 mW. Extremely compact resistive feedback CMOS low noise amplifiers were presented as a cost-effective alternative to narrow band LNAs using high-Q inductors. Techniques to improve linearity and reduce power consumption were presented. The combination of high linearity, low noise figure, high broadband gain, extremely small die area and low power consumption made the proposed LNA architecture a compelling choice for many wireless applications.

The development of radio frequency integrated circuits (RFICs), especially the dream of integrating analog, digital and radio frequency (RF) components on the same chip that is commonly known as System-on-a-Chip (SoC), is crucial to mobile communications of the future. Such SoC approach offers enhanced performance, greater reliability, and substantially less power consumption of integrated circuits while reducing overall physical size and thus manufacturing cost. However, the progress has been stalled by the lack of miniaturized inductor elements. Rise of unwanted parasitic effects limits down-scaling of the inductor structures and leaves the use of magnetic coating as a viable and attractive option to enhance the inductance and thus inductance density. It is also essential to shift from perm alloy and other amorphous alloys to ferrites and hex ferrites as the core material because of their very high electrical resistivity so as to keep losses in check, a criterion that cannot be compromised on in GHz frequency applications. This is viable, however, only if the integration of the magnetic core (film), particularly a ferrite film, is fully compatible with the CMOS fabrication process. Various approaches have been taken to meet this requirement, including investigations of employing layers of ferrite materials to envelop the inductor loop. However, the deposition of thin films of ferrites, whether by PVD or CVD, usually calls for the deposited ferrite layer to be annealed at an elevated temperature to crystallize the layer so that its magnetic characteristics are appropriate for the optimum performance of the circuit element. Such annealing is incompatible with CMOS process flow required for aggressive device geometries, as the inductor element is added after the active semiconductor circuit is processed, and any exposure of the processed circuit to elevated temperatures risks disturbing precise doping profiles employed and the integrity of the inter-layer dielectrics. What is called for is a low-temperature process for the deposition of a ferrite layer on top of the patterned inductor element – a layer of thickness such that most of the fringe field is encapsulated – while ensuring that the layer comprises crystallites of uniform size that leads to uniform magnetic behaviour. Recognizing the difficulty of meeting the various stringent requirements, it has recently been remarked that such a goal is a formidable challenge. In an attempt to address this challenge, in this work, we have adopted a counter-intuitive approach - the deposition of the desired ferrite composition on a processed die (that contains the inductor structures along with active semiconductor circuits) by immersing it into a chemical (reactant) solution, followed by a brief irradiation of microwave frequency. However, to identify the desired ferrite composition and the appropriate recipe to deposit them, a systematic effort had to be made first, to understand the inter-relationship between synthesis process, structure of resulting material, and its physical and chemical properties. Therefore, at the beginning, a general introduction in which key concepts related to the magnetic-core inductors, the microwave-irradiation-assisted synthesis of nanostructures, the ‗state of the art‘ in the field of integration of appropriate magnetic material to the RFICs, are all outlined. As a proof of concept, microwave-irradiation-assisted solution-based deposition of zinc ferrite thin films on the technologically important Si (100) substrate is demonstrated. The highlight of the process is the use of only non-toxic metal organic precursors and aqua-alcoholic solvents for the synthesis, which is complete in 10 minutes @< 100 °C, without any poisonous by-products. Effects of various process parameters such as solute concentrations, surfactant types, and their concentrations are investigated. A wide range of deposition rates (10 - 2000 nm/min) has been achieved by tweaking the process parameters. The simultaneous formation of zinc ferrite nanocrystallites (ZFNC) along with deposition of thin film is the hallmark of this synthesis technique. Unlike its bulk counterpart, both film and powder are found upon investigation to be rich in magnetic behavior– owing to plausible cationic distribution in the crystal lattice, induced by the inherently quick and far-from-equilibrium nature of the process. The accurate estimation of magnetic characteristics in film is, however, found to be difficult due to the high substrate-to-film mass ratio. The simultaneously prepared ZFNC is examined to arrive at the optimized process recipe that imparts the desired magnetic properties to the zinc ferrite system. The crystallographic cationic distribution in zinc ferrite powder is, however, difficult to study due to the nanoscale dimension of the as prepared material. To enable crystal growth, slow and rapid annealing in air at two different temperatures are employed. The effects of these annealing schemes on various attributes (magnetic properties in particular) are studied. Rapid annealing turns out to be an interesting pathway to promote rapid grain-growth without disturbing the crystallographic site occupancies. The presence of inversion, i.e., the amount of Fe3+ in the ‗A‘-sites in the spinel structure that ideally is zero in normal spinel structure of zinc ferrite, is evident in all annealed ZFNC, as determined by Riveted analysis. Such partially inverted ZFNC exhibits soft magnetic behavior with high saturation magnetization, which can easily be ―tuned‖ by choosing appropriate annealing conditions. However, a few unique strategic modifications to the same microwave-irradiation-assisted solution-based synthesis technique are tried for the formation of nanocrystalline powder with desired sizes and properties without the necessity of anneal. The approach eventually appears to pave a way for the formation of oriented structures of zinc ferrite. The effects of anneal, nevertheless, are studied with the help of neutron powder diffractometry and magnetic measurements. The magnetic ordering at various temperatures is analyzed and connected to the magnetic measurements. The study shows that long-range magnetic ordering, present even at room temperate, originates from the distribution of cations in the partially inverted spinel structures, induced by the rapid and kinetically driven microwave synthesis. Keeping the mild nature (<200 °C) of the processing in mind, a large degree of inversion (~0.5) is a surprise and results in a very high saturation magnetization, as much as 30 emu/g at room temperature (paramagnetic in bulk), in the ZFNC system. Based on the knowledge of process-structure-property interrelationship, a recipe for the deposition of ferrite thin films by the microwave-assisted deposition technique is optimized. Successful deposition of smooth and uniform zinc ferrite thin films on various substrates is, then, demonstrated. The mystery behind the strong adherence of the film to the substrate - an unexpected outcome of a low-temperature process - is probed by XPS and the formation of silicates at the interface is identified as the probable reason. The uniformity and consistency of film composition is also examined in this chapter. Another salient feature of the process is its capability to coat any complex geometry conformally, allowing the possibility of depositing the material in a way to ―wrap around‖ the three-dimensional inductor structures of RF-CMOS. Integration of nanostructure zinc ferrite thin films onto on-chip spiral inductor structures has been demonstrated successfully. The magnetic-core inductors so obtained exhibit the highest inductance density (700 nH/mm2) and the highest Q factor (~20), reported to date, operate at 5 GHz and above, by far the highest reported to date. An increase in inductance density of as much as 20% was achieved with the use of just 1 µm thick film of zinc ferrite covering only the ―top‖ of the spiral structure, i.e., up to 20% of chip real estate can potentially be freed to provide additional functionality. The microwave-assisted solution-based deposition process described in this thesis is meant for ‗post-CMOS‘ processing, wherein the film deposited on some specific electronic components can add desired functionality to or improve the performance of a component (circuit) underneath. However, the effect of such ‗post-CMOS‘ processing on the active MOS devices, interconnects, and even inter-layer-dielectrics fabricated prior to the deposition has to be mild enough to leave the performance of delicate MOS characteristics intact. Such CMOS-compatibility of the present deposition process has been tested with a satisfactorily positive result.

Speed, power and reliability of analogue integrated circuits (IC) exhibit temperature dependency through the modulation of one or several of the following variables: band gap energy of the semiconductor, mobility, carrier diffusion, current density, threshold voltage, interconnect resistance, and variability in passive components. Some of the adverse effects of temperature variations are observed in current and voltage reference circuits, and frequency drift in oscillators. Thermal instability of a voltage-controlled oscillator (VCO) is a critical design factor for radio frequency ICs, such as transceiver circuits in communication networks, data link protocols, medical wireless sensor networks and microelectromechanical resonators. For example, frequency drift in a transceiver system results in severe inter-symbol interference in a digital communications system. Minimum transconductance required to sustain oscillation is specified by Barkhausen’s stability criterion. However it is common practice to design oscillators with much more transconductance enabling self-startup. As temperature is increased, several of the variables mentioned induce additional transconductance to the oscillator. This in turn translates to a negative frequency drift. Conventional approaches in temperature compensation involve temperature-insensitive biasing proportional-to-absolute temperature, modifying the control voltage terminal of the VCO using an appropriately generated voltage. Improved frequency stability is reported when compensation voltage closely follows the frequency drift profile of the VCO. However, several published articles link the close association between oscillation amplitude and oscillation frequency. To the knowledge of this author, few published journal articles have focused on amplitude control techniques to reduce frequency drift. This dissertation focuses on reducing the frequency drift resulting from temperature variations based on amplitude control. A corresponding hypothesis is formulated, where the research outcome proposes improved frequency stability in response to temperature variations. In order to validate this principle, a temperature compensated VCO is designed in schematic and in layout, verified using a simulation program with integrated circuit emphasis tool using the corresponding process design kit provided by the foundry, and prototyped using standard complementary metal oxide semiconductor technology. Periodic steady state (PSS) analysis is performed using the open loop VCO with temperature as the parametric variable in five equal intervals from 0 – 125 °C. A consistent negative frequency shift is observed in every temperature interval (≈ 11 MHz), with an overall frequency drift of 57 MHz. However similar PSS analysis performed using a VCO in the temperature stabilised loop demonstrates a reduced negative frequency drift of 3.8 MHz in the first temperature interval. During the remaining temperature intervals the closed loop action of the amplitude control loop overcompensates for the negative frequency drift, resulting in an overall frequency spread of 4.8 MHz. The negative frequency drift in the first temperature interval of 0 to 25 °C is due to the fact that amplitude control is not fully effective, as the oscillation amplitude is still building up. Using the temperature stabilised loop, the overall frequency stability has improved to 16 parts per million (ppm)/°C from an uncompensated value of 189 ppm/°C. The results obtained are critically evaluated and conclusions are drawn. Temperature stabilised VCOs are applicable in applications or technologies such as high speed-universal serial bus, serial advanced technology attachment where frequency stability requirements are less stringent. The implications of this study for the existing body of knowledge are that better temperature compensation can be obtained if any of the conventional compensation schemes is preceded by amplitude control. / Dissertation (MEng)--University of Pretoria, 2013. / Electrical, Electronic and Computer Engineering / unrestricted