Three main elements for an indoor positioning and navigation system design are the signal structure, the signal processing algorithm and the digital and RF prototype hardware. This thesis focuses on the design and development of RF prototype hardware. The signal structure being used in the precise positioning system discussed in this thesis is a Multicarrier-Ultra Wideband (MC-UWB) type signal structure. Unavailability of RF modules suitable for MC-UWB based systems, led to design and development of custom RF transmitter and receiver modules which can be used for extensive field testing. The lack of RF design guidelines for multicarrier positioning systems that operate over fractional bandwidth ranging from 10% to 25% makes the RF design challenging as the RF components are stressed using multicarrier signal in a way not anticipated by the designers. This thesis, first presents simulation based performance evaluation of impulse radio based and multicarrier based indoor positioning systems. This led to an important revelation that multicarrier based positioning system is preferred over impulse radio based positioning systems. Following this, ADS simulations for a direct upconversion transmitter and a direct downconversion receiver, using multicarrier signal structure is presented. The thesis will then discuss the design and performance of the 24% fractional bandwidth RF prototype transmitter and receiver custom modules. This optimized 24% fractional bandwidth RF design, under controlled testing environment demonstrates positioning accuracy improvement by 2-4 times over the initial 11% fractional bandwidth non-optimized RF design. The thesis will then present the results of various indoor wireless tests using the optimized RF prototype modules which led to better understanding of the issues in a field deployable indoor positioning system.

"Recently considerable attention has been paid to indoor geolocation using wireless local area networks (WLAN) and wireless personal area networks (WPAN) devices. As more applications using these technologies are emerging in the market, the need for accurate and reliable localization increases. In response to this need, a number of technologies and associated algorithms have been introduced in the literature. These algorithms resolve the location either by using estimated distances between a mobile station (MS) and at least three reference points (via triangulation) or pattern recognition through radio frequency (RF) fingerprinting. Since RF fingerprinting, which requires on site measurements is a time consuming process, it is ideal to replace this procedure with the results obtained from radio channel modeling techniques. Localization algorithms either use the received signal strength (RSS) or time of arrival (TOA) of the received signal as their localization metric. TOA based systems are sensitive to the available bandwidth, and also to the occurrence of undetected direct path (UDP) channel conditions, while RSS based systems are less sensitive to the bandwidth and more resilient to UDP conditions. Therefore, the comparative performance evaluation of different positioning systems is a multifaceted and challenging problem. This dissertation demonstrates the viability of radio channel modeling techniques to eliminate the costly fingerprinting process in pattern recognition algorithms by introducing novel ray tracing (RT) assisted RSS and TOA based algorithms. Two sets of empirical data obtained by radio channel measurements are used to create a baseline for comparative performance evaluation of localization algorithms. The first database is obtained by WiFi RSS measurements in the first floor of the Atwater Kent laboratory; an academic building on the campus of WPI; and the other by ultra wideband (UWB) channel measurements in the third floor of the same building. Using the results of measurement campaign, we specifically analyze the comparative behavior of TOA- and RSS-based indoor localization algorithms employing triangulation or pattern recognition with different bandwidths adopted in WLAN and WPAN systems. Finally, we introduce a new RT assisted hybrid RSS-TOA based algorithm which employs neural networks. The resulting algorithm demonstrates a superior performance compared to the conventional RSS and TOA based algorithms in wideband systems."

A realistic comparative performance evaluation of indoor Geolocation systems is a complex and challenging problem facing the research community. This is due to the fact that performance of these systems depends on the statistical variations of the fading multipath characteristics of the wireless channel, the density and distribution of the access points in the area, and the number of the training points used by the positioning algorithm. This problem, in particular, becomes more challenging when we address RFID devices, because the RFID tags and the positioning algorithm are implemented in two separate devices. In this thesis, we have designed and implemented a testbed for comparative performance evaluation of RFID localization systems in a controlled and repeatable laboratory environment. The testbed consists of a real-time RF channel simulator, several WiFi 802.11 access points, commercial RFID tags, and a laptop loaded with the positioning algorithm and its associated user interface. In the real-time channel simulator the fading multipath characteristics of the wireless channel between the access points and the RFID tags is modeled by a modified site-specific IEEE 802.11 channel model which combines this model with the correlation model of shadow fading existing in the literature. The testbed is first used to compare the performance of the modified IEEE 802.11 channel model and the Ray Tracing channel model previously reported in the literature. Then, the testbed with the new channel model is used for comparative performance evaluation of two different WiFi RFID devices.

"Microelectromechanical systems (MEMS) technology has been evolving for about two decades and, now it is integrated in many designs, including radio frequency (RF) switches characterized by µm dimensions. Today, designers are attempting o develop the ideal RF MEMS switch, yet electro-thermo-mechanical (ETM) effects still limit the design possibilities and adversely affect reliability of these microswitches. The ETM effects are a result of Joule heat generated at the microswitch contact areas. This heat is due to the current passing through the microswitch, characteristics of the contact interfaces, and other parameters characterizing a particular design. It significantly raises temperature of the microswitch, thus affecting the mechanical and electrical properties of the contacts, which may lead to welding, causing a major reliability issue. Advanced research was performed, in this thesis, to minimize the Joule heat effects on the contact areas, thus improving performance of the microswitch. Thermal analyses done computationally on a cantilever-type RF MEMS switch indicate heat-effected zones and the influences that various design parameters have on these zones. Uncertainty analyses were also performed to ensure accuracy of the computational results, which indicate contact temperatures on the order of 700˚C, for the cases considered in this thesis. Although these temperatures are well below the melting temperatures of the materials used, new designs of the microswitches will have to be developed, in order to lower their maximum operating temperatures and reduce temporal effects they cause, to increase reliability of the RF MEMS switches."

When we forget things, we feel anxious which can impact our day negatively. Some individuals believe they are forgetful, so emphatically, it disrupts their day. There has been little discussion about perceived forgetfulness in design and HCI, combined with few studied smart objects to aid with memory. However, embedded systems, radio frequency identification (RFID) and HCI research provides inspiration towards creating a solution. Challenges of creating a day-to-day smart object that can enhance a user's lifestyle are explored and recommended design guidelines for creating a smart object in a specific domain are the focus of this thesis. Using an experience-centred approach, 'Message Bag' and 'Tag Along' are two purpose built object-based memory aids that have emerged as a result of investigating the design processes for smart objects. The work examines smart objects in the context of forgetting what items to pack in a bag. A solution presented is a device consisting of an RFID system involving (a) pre-tagging essential items; (b) scanning those tagged items and; (c) viewing a corresponding light illuminate, to communicate to the user. Although the conceptual model is simple, success depends on a combination of technical design, usability and aesthetics. These scanning interactions result in a person feeling more confident as suggested through autoethnography reporting, real-world, third person engagements - single user walkouts, conference demos, professional critiques, and residential weekends with potential users (focus group) studies conducted. My work involved extensive autobiographical research and design-led enquiries. Testing was undertaken with investigative prototypes, followed by field testing high-fidelity prototypes. This involved an in-the-wild comparative study involving six users over several months. Results show that people feel more confident and respondents claim no longer needing to continually check items are packed, thus 'gaining time', and feeling less forgetful. Although the application of RFID is not new to ubiquitous computing, this implementation, styling and system immediacy is novel. This thesis presents the development of ten prototypes as well as design guidelines. The research provides a solid base for further exploration, and includes discovery of the importance of a user's style universe and extreme ease-of-use. I conclude with the presentation of early positive results including; (i) the unique form factor becomes a reminder itself and; (ii) usability coupled with the intuitive nature of the system is shown to be essential. We found that when you are creating a smart object, usability and an intuitive nature is even more important than in a standard system. When dealing within the domain of forgetfulness, this is paramount.

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1978. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Includes bibliographical references. / B.S.

Wireless communication circuits rely on the use of high-quality passive elements (inductor-capacitor resonant tanks) for the implementation of selective filters and high-purity frequency references (oscillators). Typically available CMOS, on-chip passives suffer from high losses, primarily inductors, and consume large areas that cannot be populated by transistors leading to a significant area penalty. Mechanical resonators exhibit significantly lower losses than their electrical counterparts due to the reduced parasitic loss mechanisms in the mechanical domain. Efficient transduction schemes such as the piezoelectric effect allow for simple electrical actuation and read-out of such mechanical resonators. Piezoelectric thin-film bulk acoustic resonators (FBARs) are currently among the most promising and widely used mechanical resonator structures. However, FBARs are currently only available as off-chip components, which must be connected to CMOS circuitry through wire-bonding and flip-chip schemes. The use of off-chip interfaces introduces considerable parasitics and significant limitations on integration density. Monolithic integration with CMOS substrates alleviates interconnect parasitics, increases integration density and allows for area sharing whereby FBARs reside atop active CMOS circuitry. Close integration of FBARs and CMOS transistors can also enable new circuit paradigms, which simultaneously leverage the strengths of both components. Described here, is a body of work conducted to integrate FBAR resonators with active CMOS substrates (180nm and 65nm processes). A monolithic fabrication method is described which allows for FBAR devices to be constructed atop the backend small CMOS dies through low thermal-budget (< 300°C) post-processing. Stand-alone fabricated devices are characterized and the extracted electrical model is used to design two oscillator chips. The chips comprise amplifier circuitry that functions along with the integrated FBARs to achieve oscillation in the 0.8-2 GHz range. The chips also include test structures to assess the performance of the underlying CMOS transistors before and after the resonator post-processing. A successful FBAR-CMOS oscillator is demonstrated in 65nm CMOS along with characterization of FBARs built on CMOS. The approach presented here can be used for experimenting with more complex circuits leveraging the co-integration of piezoelectric resonators and CMOS transistors.

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise.

The demand for broadband wireless communication is growing rapidly, requiring more spectrum resources. However, spectrum usage is inefficient today because different frequency bands are allocated for different communication standards and most of the bands are not highly occupied. Cognitive radio systems with dynamic spectrum access improve spectrum efficiency, but they require wideband tunable receiver hardware. In such a system, a preselect filter is required for the RF receiver front end, because an out-of-band (OB) interferer can block the front end or cause distortion, desensitizing the receiver. In a conventional solution, off-chip passive filters, such as surface-acoustic-wave (SAW) filters, are used to reject the OB interferer. However, such passive filters are hardly tunable, have large area, and are very expensive. On-chip, high-selectivity, linearly tunable RF filters are, therefore, a hot topic in RF front-end research. Switched-capacitor (SC) RF filters, such as N-path filters, feature good linearity and tunability, making them good candidates for tunable RF filters. However, N-path filters have some drawbacks: notably, a poor harmonic response and limited close-by blocker tolerance. This thesis presents the design and implementation of several interferer-tolerant receivers based on SC technology. We present an RF receiver with a harmonic-rejecting N-path filter to improve the harmonic response of the N-path bandpass filter. It features tunable narrowband filtering and high attenuation of the third- and fifth-order LO harmonics at the LNA output, which improves the blocker tolerance at LO harmonics. The 0.2-1 GHz RF receiver is implemented in a 65 nm CMOS process. The blocker 1 dB compression point (B1dB) is -2.4 dBm at a 20 MHz offset, and remains high at the third- and fifth-order LO harmonics. The LNA’s reverse isolation helps keep the LO emission below -90 dBm. A two-stage harmonic-rejection approach offers a > 51 dB harmonic-rejection ratio at the third- and fifth-order LO harmonics without calibration. To improve tolerance for close-by blockers, we further present an SC RF receiver achieving high-order, tunable, highly linear RF filtering. We implement RF input impedance matching, N-path filtering, high-order discrete-time infinite-impulse response (IIR) filtering and downconversion using only switches and capacitors in a 0.1-0.7 GHz prototype with tunable center frequency, programmable filter order, and very high tolerance for OB blockers. The 40 nm CMOS receiver consumes 38.5-76.5mA, achieves 40 dB gain, 24 dBm OB IIP3, 14.7 dBm B1dB for a 30MHz blocker offset, 6.8-9.7 dB noise figure, and > 66dB calibrated harmonic rejection ratio. The key drawback of our earlier SC receiver is the relatively high theoretical lower limit of the noise figure. To improve the noise performance, we developed a 0.1-0.6 GHz chopping SC RF receiver with an integrated blocker detector. We achieve RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping with passive SC circuits only. The 34-80 mW 65 nm receiver achieves 35 dB gain, 4.6-9 dB NF, 31 dBm OB-IIP3, and 15 dBm B1dB. The 0.2 mW integrated blocker detector detects large OB blockers with only a 1 us response time. The filter order can be adapted to blocker power with the blocker detector.

Radio Frequency Identification (RFID) has received a great deal of attention in past decades. It is an automatic identification system by replying and retrieving data remotely using RFID transponders. Basically, RFID systems can be divided into three main categories: short transmission range, medium transmission range, and long transmission range. / Short and medium range RFIDs generally are passive transponders while long range RFID is of either passive or active type. In this thesis, a short transmission range RFID transponder is presented. This is a passive transponder which generates power for internal circuitry by inductive coupling. For automatic identification applications such as electronic money tickets, the requirements of endurance, weight, size as well as cost appeal to use passive transponder rather than active transponder. Researches on the passive transponders have created a great challenge for engineers in terms of the tradeoff between power constraints, processing power and data transmission range. / The presented RFID transponder system adheres to the ISO 14443 standard Type B specification communication interface, which operates at 13.56MHz carrier frequency with a maximum read range around 50 mm. This research implemented a low power, high security, and long read range RFID transponder. For the analog RF interface, a series of novel architectures are adopted to improve the data transmission range. The digital core in the presented crypto-processor for data security. The asynchronous architecture has the advantages of fast computation time, low power consumption and small area. These are the attractive reasons to implement the core processing units using an asynchronous architecture. / This RFID system was fabricated with a 0.35um two-poly four-metal standard CMOS process with the silicon area of 1516 um x 1625 um. The measurement results show that the analog RF interface can generate a maximum 5.45mW power while the digital core circuit consumes only 2.77mW. In the wireless communication tests, the transponder read range can reach as far as 50 mm. / Leung, Pak Keung. / "June 2008." / Adviser: Choy Chin Sing. / Source: Dissertation Abstracts International, Volume: 70-03, Section: B, page: 1847. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.