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The feasibility of memory encryption and authenticationOwen, Donald Edward, Jr. 09 October 2013 (has links)
This thesis presents an analysis of the implementation feasibility of RAM authentication and encryption. Past research as used simulations to establish that it is possible to authenticate and encrypt the contents of RAM with reasonable performance penalties by using clever implementations of tree data structures over the contents of RAM. However, previous work has largely bypassed implementation issues such as power consumption and silicon area required to implement the proposed schemes, leaving implementation details unspecified. This thesis studies the implementation cost of AES-GCM hardware and software solutions for memory authentication and encryption and shows that software solutions are infeasible because they are too costly in terms of performance and power, whereas hardware solutions are more feasible. / text
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Dynamisches Verhalten ferroelektrischer Kondensatoren : Modellierung und Charakterisierung /Supriyanto, Eko. January 2004 (has links)
Helmut-Schmidt-Univ., Diss.--Hamburg, 2005.
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Dynamisches Verhalten ferroelektrischer Kondensatoren Modellierung und Charakterisierung /Supriyanto, Eko. Unknown Date (has links) (PDF)
Helmut-Schmidt-Universiẗat, Diss., 2005--Hamburg. / Erscheinungsjahr an der Haupttitelstelle: 2004.
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Výměna nástrojů u svislého soustruhu / Tool changing of vertical turning latheHuňka, Radek January 2012 (has links)
This master's thesis deals with the problems of tool changing of vertical turning lathe. Specifically about modular system of spindle locking in a ram. The master's thesis is shows types of structural design, choosing the best design with supporting technical - economics evaluation. After this is realized series of calculation controls. These define dimensions of the mechanical parts.
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A Robust Low Power Static Random Access Memory Cell DesignPusapati, A. V. Rama Raju 27 August 2018 (has links)
No description available.
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Molecular mechanisms of RAM and RNMT regulationLu, Yunqi 01 March 2024 (has links)
mRNA cap guanine-N7 methyltransferase (RNMT) catalyzes the S-adenosyl-dependent methylation of the 5’ cap on mRNA at the N-7 position of guanosine. RNA guanine-N7 methyltransferase activating subunit (RAM) allosterically binds to RNMT, which enhances its methyltransferase activity. RAM is phosphorylated at Ser36; however, how this post-translational modification impacts its interaction with RNMT is still unclear. Ser36 of RAM is positioned within a positively charged binding pocket of RNMT, indicating that phosphorylation would improve the binding affinity between these two proteins. Using protein semi-synthesis, we discovered that the first 45 amino acids of RAM is sufficient for full binding to RNMT, and that phosphorylation of Ser36 does increase the binding affinity around six-fold. / 2026-02-28T00:00:00Z
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Design of control electronics for the Ram Energy Distribution DetectorVenkatramanan, Adithya 03 September 2015 (has links)
The bulk motion of the neutral gas at altitudes between about 200 and 600 km is an important factor in predicting the onset of plasma instabilities that are known to distort and/or disrupt high frequency radio communications. A ram wind sensor is a space science instrument that, when mounted on a satellite in low-Earth orbit, makes in-situ measurements of the component of the neutral gas velocity that lies along the orbit track of the satellite. The instrument works by changing the voltage on one of a set of grids and measuring a corresponding electron current generated by ions flowing through the grid stack and detected by the microchannel plate, generating a function of current vs. voltage called an I-V curve. Traditionally, the size and power requirements of ram wind sensors has limited their use to larger satellites. In this thesis, the electrical design and basic testing of a cubesat compatible RWS known as the ram energy distribution detector (REDD) are described.
The mechanical design of the REDD sensor is first described, and the requirements of the electrical design are presented. The electrical requirements are based on both the characteristics of the ionosphereic flight environment, and on the size and power requirements typical of the small cubesat platforms for which the instrument is intended.
The electrical hardware is then described in detail. The microcontroller design is reviewed as well, including the instrument's operating mode, and timing scheme.
Test data showing the basic functionality of the instrument are then presented. Bench tests validate the design by confirming its ability to control voltages and measure small electron currents. End-to-end tests were also performed in a vacuum chamber to mimic the ionospheric environment. These data are presented to show the ability of the REDD sensor to meet or exceed its design specifications. / Master of Science
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Ram Pressure Stripping of Molecular Gas / MODELING MOLECULAR GAS SUSCEPTIBILITY TO RAM PRESSURE STRIPPING IN THE VIRGO CLUSTERGreis, Celine January 2024 (has links)
Ram pressure stripping (RPS) can be described as the constant wind a galaxy experiences when moving through a galaxy cluster. It is well-established that galaxies
undergoing this process lose substantial amounts of their atomic gas, but its effect on
the cold molecular gas component is still not fully understood. Using high-resolution
ALMA CO 2-1 data collected by the PHANGS and VERTICO surveys, I model the
detailed effect of RPS in 36 Virgo galaxies on a 150 pc and 720 pc scale by calculating
the ratio of ram pressure to the galaxy gravitational restoring force per unit area. If
the ram pressure exceeds the restoring pressure, we assume the molecular gas parcel
is susceptible to stripping. I reveal that roughly a quarter of our 36 galaxies are
susceptible to molecular gas RPS, with up to 70% of their molecular gas in the outer
disk (r > R50) being susceptible. As expected, low mass galaxies (log(M∗/M ) = 9.5)
seem to be most affected. VERTICO galaxies show molecular gas susceptible to stripping at the outskirts and between their spiral arms. I also find higher fractions of RPS
susceptible molecular gas in galaxies exhibiting clear atomic gas tails, suggesting that
RPS impacts multiple gas phases at once. Finally, a phase space analysis suggests
molecular gas RPS occurs primarily, potentially exclusively, at the first pericentric
passage when ram pressure is maximal. / Thesis / Master of Science (MSc)
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Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI. / Proposals for performance improvement of dynamics memory cell using a single transistor SOI UTBOX.Sasaki, Kátia Regina Akemi 05 February 2013 (has links)
Neste trabalho foi analisado o comportamento de um transistor UTBOX FD SOI MOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo N, em sua aplicação como uma célula de memória 1T-DRAM, dando ênfase no estudo das polarizações e propostas de melhorias de desempenho para viabilizar sua aplicação como uma célula de memória. Dessa forma, foram analisados os efeitos das diferentes polarizações (de porta, de dreno e de substrato), bem como a influência da concentração de uma região de extensão de fonte e dreno menos dopada (LDD Lightly Doped Drain), nos principais parâmetros da referida memória. Assim, foram analisados alguns parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Por fim, foram propostas algumas melhorias de desempenho para o tempo de retenção. Foi observado que o aumento da temperatura facilita a escrita na memória diminuindo a mínima tensão no dreno (até 72% para temperatura de 25 a 300°C, ficando limitada a 0,8V) e o tempo necessários para a escrita (até 95%), porém reduz a margem de sensibilidade (até 90%) e o tempo de retenção (até 2 ordens de grandeza). Verificou-se também que, apesar da menor espessura do filme de silício e do óxido enterrado aumentar a tensão no dreno necessária para ativar o efeito BJT (efeito bipolar parasitário), um potencial positivo no substrato pode reduzir este requisito (61% para tensão de substrato variando de 0 V até 1,5 V). Além disso, foi visto que pode haver uma geração ou uma recombinação de portadores, dependendo da tensão na porta durante o repouso, degradando o bit \'0\' ou \'1\'. Já a otimização da polarização de substrato demonstrou ser limitada pelo compromisso de ser alta o suficiente para ativar o efeito de corpo flutuante durante a escrita, sem prejudicar a leitura do \'0\'. Os resultados também demonstraram que a margem de sensibilidade é menos dependente da tensão do substrato que o tempo de retenção, levando a este último parâmetro ser considerado mais crítico. Com relação à leitura, maiores tensões no dreno resultaram na presença do efeito BJT também neste estado, aumentando a margem de sensibilidade (60%) e diminuindo o tempo de retenção (66%) e o número de leituras possíveis sem atualização do dado (de mais de 30 para 22 leituras). No tópico da concentração das extensões de fonte e dreno, os dispositivos sem extensão de fonte e dreno apresentaram uma taxa de geração de lacunas menor (aproximadamente 12 ordens de grandeza), levando a um tempo de retenção muito maior (aproximadamente 3 ordens de grandeza) quando comparado ao dispositivo referência. Em seu estudo no escalamento, verificou-se uma diminuição no tempo de retenção para canais mais curtos (quase 2 ordens de grandeza), demonstrando ser um fator limitante para as futuras gerações das memórias 1T-DRAM. Apesar disso, quando comparados com os dispositivos convencionais com extensão de fonte e dreno (com extensão), seu tempo de retenção aumentou (quase 1 ordem de grandeza), permitindo a utilização de menores comprimentos de canal (30nm contra 50nm do dispositivo com extensão) e polarizações de substrato menores. Outra proposta de melhoria no tempo de retenção apresentada foi a utilização da polarização de substrato pulsada apenas durante a escrita do nível \'1\', o que resultou no aumento do tempo de retenção em 17%. Finalmente, estudou-se também a variação da banda proibida motivado pela utilização de novos materiais para o filme semicondutor. Observou-se que o aumento da banda proibida aumentou o tempo de retenção em até 5 ordens de grandeza, possibilitando retenções mais próximas das DRAMs convencionais atuais. / In this work, it was analyzed the behavior of a planar UTBOX FD SOI NMOSFET (Ultra-Thin-Buried-Oxide Fully-Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor), as a 1T-DRAM (Single Transistor Dynamic Random Access Memory) cell, focusing on the best biases and other proposals for enabling the 1T-DRAM applications. Therefore, it was analyzed the effects of different biases (gate, drain and substrate), as well as the influence of the concentration of a less doped source/drain extension region on the main parameters of this kind of memory. Thus, it was analyzed some of the main memory parameters such as the trigger drain voltage, the sense margin, the read window and the retention time, as well as the mechanisms operating in each state of the memory (writing, reading and holding). Finally, it were proposed some performance enhancements for the retention time of this kind of memory. It was observed that the increase in temperature facilitates the memory write decreasing the minimum drain bias and time required for writing, but reduces the sense margin. It was also verified that, despite the thinner silicon film and buried oxide increase the drain voltage required to activate the BJT effect (parasitic bipolar effect), a positive potential on the substrate may reduce this requirement (61% for back gate bias varying from 0 to 1,5V), being an alternative for solving the problem and allowing the use of smaller devices as a memory cell. Furthermore, it was seen that there can be a carriers generation or recombination, depending on the gate voltage during the holding state, degrading the bit \'0\' or \'1\'. Moreover, the optimization of substrate bias proved to be limited by enabling the writing state, without degrading the reading of \'0\'. The results also demonstrated the sense margin is less dependent on the substrate voltage than the retention time, therefore, the retention time was considered as a more critical parameter. With respect to the reading state, there was the presence of BJT effect also in this state, increasing the margin of sensitivity (60%) and reducing the retention time (66%) and the number of possible readings without updating the data (over 30 for 22 readings) in cases of higher drain bias. On the topic of the concentration of the source and drain extensions, the devices with source and drain extensions presented a generation rate lower (about 12 orders of magnitude), resulting in a retention time far longer than the reference one (about 3 orders of magnitude). About its downscaling, the retention time decreased for shorter channel lengths (almost 2 orders of magnitude), which is a limiting factor for 1T-DRAM future generations. Nevertheless, when it was compared to the conventional devices with source and drain extensions, theirs retention time increased (almost 1 order of magnitude), allowing the use of shorter channel lengths (30nm against 50nm of reference device) and lower back gate biases. Another proposal presented to improve the retention time was the pulsed back gate only during the writing \'1\' state, which resulted in an increase on the retention time by 17%. Finally, we also studied the band gap influence motivated by the use of new materials for the semiconductor film. It was observed that higher band gaps increase the retention time by up to 5 orders of magnitude, allowing a retention time closer to the current conventional DRAMs.
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Estudo de célula de memória dinâmica de apenas um transistor SOI de óxido enterrado ultrafino. / Study of dynamic memory cell of only one SOI transistor with ultrathin buried oxide.Almeida, Luciano Mendes 25 September 2012 (has links)
Neste trabalho foi analisado o comportamento de um transistor UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) planar do tipo n, operando como uma célula de memória 1T-FBRAM (single transistor floating body random access memory). A memória em questão trata-se de uma evolução das memórias 1T1C-DRAM convencionais formada, porém, de apenas um transistor, sendo o próprio transistor o responsável pelo armazenamento da informação por meio do efeito de corpo flutuante. Assim, foram realizadas simulações numéricas bidimensionais, obtendo-se curvas dinâmicas e, a partir destas, foi possível extrair e analisar alguns dos principais parâmetros da memória tais como tensão de disparo no dreno, margem de sensibilidade, janela de leitura e tempo de retenção, além dos mecanismos atuantes em cada estado da memória (escrita, leitura e repouso). Foram estudadas as polarizações da célula de memória. Dentre as possíveis maneiras de programação do dado 1 desta tecnologia foram abordadas neste trabalho a programação pelos métodos GIDL (Gate Induced Drain Leakage) e BJT (Bipolar Junction Transistor). Pelo método de escrita por GIDL foi possível operar a célula de memória em alta velocidade sem dissipar potência expressiva. Mostrou-se que esse método é bastante promissor para a tecnologia low-power high-speed. E ainda, obteve-se maior estabilidade na operação de leitura quando esta é polarizada no ponto ZTC (Zero Temperature-Coefficient) devido ao nível de corrente do dado 0 ficar estável mesmo com a variação da temperatura. Pelo método de escrita por BJT, estudou-se a influência das espessuras do filme de silício e também do óxido enterrado, notou-se uma forte dependência da tensão mínima de dreno para a programação do dado 1 em função destas espessuras e também em função da temperatura. Conforme a espessura do filme de silício torna-se mais fina, a tensão de disparo aplicada ao dreno aumenta devido ao maior acoplamento. Porém, observou-se que o nível da tensão de disparo do dreno pode ser modulada através da tensão aplicada ao substrato, tornando possível operar a célula em uma tensão de disparo menor aumentando a vida útil do dispositivo. Quanto à temperatura, com o seu aumento observou-se que a tensão mínima de dreno necessária para disparar a escrita do dado 1 diminuiu favorecendo a programação da célula. Porém o tempo de retenção é prejudicado (torna-se menor) por causa do aumento da corrente de fuga na junção PN. Na análise sobre o impacto que a primeira e a segunda porta causam na margem de sensibilidade de corrente e no tempo de retenção, verificou-se que dependendo da tensão aplicada à porta durante a condição de armazenamento do dado, o tempo de retenção pode ser limitado ou pela geração ou pela recombinação dos portadores (lacunas). Notou-se que há um compromisso entre a obtenção da melhor margem de sensibilidade de corrente e o melhor tempo de retenção. Como o tempo retenção é um parâmetro mais crítico, mais atenção foi dada para a otimização deste. Concluiu-se nesta análise que a melhor polarização para reter o dado por mais tempo é a primeira interface estar em modo acumulação e a segunda em modo depleção. No estudo da polarização de dreno durante a operação de leitura, observou-se que quando aplicado alta tensão de dreno é obtido alta margem de sensibilidade, porém ao mesmo tempo esta polarização prejudica o dado 0 devido ao alto nível de geração de lacunas induzidas pela ionização por impacto, o qual diminui o tempo de retenção e destrói o dado 0 quando operações de múltiplas leituras são realizadas. Já para baixo nível de tensão de dreno durante a leitura notou-se que é possível realizar múltiplas operações de leitura sem perder o dado armazenado e também maior tempo de retenção foi obtido. / In this study was analyzed the behavior of one transistor called UTBOX (Ultra Thin Buried Oxide) FD SOI MOSFET (Fully Depleted Silicon-on-Insulator Metal- Oxide-Semiconductor Field-Effect-Transistor) working as a 1T-FBRAM (Single Transistor Floating Body Random Access Memory). This memory device is an evolution from conventional memories 1T1C-DRAM, however formed by only one transistor, the device itself is responsible for the storage of the information through the floating body effect. Thus two dimensional simulations were performed, where were obtained dynamic curves, and from these curves it was possible to extract and analyze some of the main parameters, such as, trigger drain voltage, sense margin current, read window, and the retention time, beyond the mechanisms in each state of memory (write, read and hold). Among the possible ways to program the data 1 in this technology were used the methods GIDL (Gate Induced Drain Leakage) and BJT (Bipolar Junction Transistor). By the GIDL method it was possible to operate the memory cell at high speed without spending significant power, showing that this method is very promising for low-power high-speed. Furthermore, greater stability was obtained in read operation when it is biased at point ZTC (zero-Temperature Coefficient) due to the current level of datum \'0\' remain stable even with temperature variation. By the BJT method, it was studied the influence of the silicon film thickness and the buried oxide thickness, and it was noted a strong dependence on minimum drain voltage for programming the data \'1\' as a function of both thicknesses. As the thickness of the silicon film becomes thinner, the trigger drain voltage increases due to stronger coupling. However, it was observed that the level of the trigger drain voltage can be modulated by the substrate bias in this way it is possible to operate the cell with lower voltage avoiding the damage and increasing the lifetime of the device. About the temperature, with its increase it was observed that the minimum drain voltage required to trigger the writing datum \'1\' decreased favoring the programming the cell. However the retention time is harmed (becomes smaller) due to the increment of leakage current in the PN junction. Analyzing the impact of the first and second gate on sense margin current and retention time, it was verified that depending on the voltage applied to the gate during the hold condition, the retention time may be limited by the generation or recombination of the carriers (holes). It was noted that there is a compromise between obtaining the best sense margin current and the best retention time. Since the retention is the most critical parameter, more attention should be given in order to obtain the optimization of this latter. It is concluded in this analysis that the best bias to retain the datum for longer time is the first interface being in accumulation mode and the second in depletion mode. In the study of biasing the drain during the read operation, it has been observed that the use of high drain voltage provides high sense margin, but at the same time, this polarization affect the data \'0\' due to high level of holes generation induced by impact ionization, which shortens the retention time and destroys the data \'0\' in multiple read operations. However, for low drain voltage during read operations it was possible to perform multiple read operations without losing the stored data and also higher retention time was obtained.
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