Denna rapport behandlar en radarsensors förmåga att upptäcka 107 mm raketerberoende på hur sensorn positioneras i förhållande till skyddsobjektet.Fältförsök, underrättelser och stridserfarenheter har visat att dessa raketer ärvanligt förekommande samt svåra att detektera med radarsensorer. En modell för hur räckviddsökning beror på olika sensorpositioner har skapats genom att använda dokument från USA och forna Sovjetunionen beskrivande ballistik tillsammans med teorier för hur räckvidd påverkas av radarmålarea (RCS) samten beskrivning av RCS tillhandahållen av FOI. Resultat från körningar iMATLAB visar att sensorpositioner inom 300 meter från skyddsobjektet ärfördelaktiga vid en skottvidd av 3000 meter. Som tumregel för att uppnå maximal sensorprestanda bör strävan vara att placera sensorn på ett avståndfrån skyddsobjektet understigande 10% av förväntad skottvidd.

This work deals with COMBO2 card interconnect and memory devices testing. In the beginning of the paper, some existing testing algorithms for interconnect and RAM memories testing are introduced. This work is devoted to proposal of generic architecture for interconnect and memory devices testing. The proposed architecture is optimized for FPGA implementation.

No description available.

O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL. / The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.

O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL. / The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.

Cette thèse vise à décrire comment un ordre religieux subit des processus d'évolution et de transformation qui permettent d'interpréter et de satisfaire les besoins religieux de la société. L'hypothèse à la base de ce travail est que les ordres religieux et les gourous sont des éléments centraux qui caractérisent et influencent la société indienne dans le passé et dans le présent.Je focalise mon attention sur le sampradāya des Rāmānandī –groupe religieux datant de Rāmānanda- qui eut un rôle primordial dans la diffusion de la bhakti de Ram (dévotion envers Ram) dans le nord de l’Inde vers la fin du XVème siècle. Mon but est de montrer comment la figure de Rāmānanda et l’organisation de l’ordre religieux ont évolué au cours des siècles, pour être capables ensuite d’interpréter les principaux changements survenus au XXème siècle.A cause de ces différences internes, les Rāmānandīs n’ont jamais eu de représentant dans un centre officiel qui puisse fonctionner comme pôle directeur pour l’ordre. Donc, l’utilisation du titre de Jagadgurū Rāmānandācārya et la construction du Śrī Math au XXème siècle représentent un changement significatif dans l’histoire de l’ordre. C’est pour cela que j’ai formulé mes principales questions, base de ma recherche, sur ce thème :1) pourquoi au XXème siècle, un sampradāya caractérisé par diverses disciplines religieuses (sādhanā-s) et diffusé dans différents centres indépendants a senti la nécessité de créer la fonction de Jagadgurū Rāmānandācārya comme leader principal ?2) le Śrī Math fait-il partie de la reconstruction du charisme du Rāmānanda et est-il un instrument pour aider à la fonction de Jagadgurū Rāmānandācārya ?Pour retracer l’évolution de la tradition des Rāmānandī de leur origine à nos jours j’ai utilisé une approche multidisciplinaire, dans laquelle méthodologies anthropologique et historique coopèrent. / In this dissertation, I focus my attention on the Rāmānandī sampradāya - a religious group supposedly formed by the religious teacher Rāmānanda – that had a primary role in spreading Rām bhakti (devotion toward Rām) throughout northern India, possibly from the end of the 15th century. My purpose here is to reconstruct how the representation of Rāmānanda and the organization of the sampradāya evolved over the centuries in order to interpret the two main changes that have occurred in the 20th century: the establishment of the office of Jagadgurū Rāmānandācārya as the leader of the sampradāya, and the construction of the Śrī Maṭh, a monastery on the place where, according to the Rāmānandī tradition, Rāmānanda used to preach. Because of these internal distinctions, the Rāmānandī-s have never had a single representative leader installed in a particular place that could work as directive pole for the sampradāya. Therefore, the bestowing of the title of Jagadgurū Rāmānandācārya and the construction of the Śrī Maṭh in the 20th century represent a significant change in the history of the order. For this reason, I formulated the main questions at the base of my research as follows: 1 Why has a sampradāya characterized by several religious disciplines (sādhanā-s) and spread across several independent religious centers established the office of a Jagadgurū Rāmānandācārya as central leader in the 20th century? 2 Which role does the Śrī Maṭh play in the reconstruction of Rāmānanda’s charisma and in support of the office of Jagadgurū Rāmānandācārya? To accomplish my analysis I employ a multidisciplinary approach – described in Chapter 1 – in which anthropological and historical methodologies cooperate to reconstruct the evolution of the Rāmānandī tradition from its origin until the present.

Spacecloth design and development is vital and crucial in Radar Absorbing Materials (RAM) for achieving Low Observability in an Aircraft or an Unmanned Air Vehicle(UAV). The RAM design translates into the spacecloth design. The spacecloths form the constituent layers in a broadband Jaumann absorber in which case they have to be designed for various values of surface resistivity. The design specifications of spacecloth(s) in RAMS is well understood and documented in literature. But the design of spacecloth hitherto, has been the domain of materials' scientists wherein the specified properties of the spacecloth are achieved by an iterative, trial and error process, by mixing various constituents in different proportions to get the design specified surface resistivity in the final end-product. In an effort to bridge this gap, a novel spacecloth for RAM applications is proposed in the thesis. It is proposed that a repetitive geometrical grid network of chip resistors simulates spacecloth. The sheet resistivity of the spacecloth is derived by analyzing various geometries like square, rectangle, triangle and hexagonal grids. The transmission and reflection loss for the chip resistor spacecloth is derived. The design of chip resistor spacecloths for operation at S and C bands is given followed by experimental verification using waveguide simulator experiments. Numerical study of multilayer RAM has been carried out with exponential taper variation of surface resistivities for constituent spacecloth layers and design curves are given for multilayer RAM both for normal and oblique incidence for TE and TM polarizations.

The aim of this thesis is to study the possibilities of spectrum calculations, as well as data transfer via USB 3.0 and data saving to a DDR3 memory via FPGA. The focus is also on design and realization of a spectral analyzer with a record of samples to DDR memory expnaded by a narrowband converter using gate arrays. The work is divided into two sections, the first one dealing with the theoretical background. The second part denotes the realization of the design. The result of this work is a signal analyzer in a FPGA controlled from a computer application via the USB 3.0 interface.

This work deals with design and implementation of a methodology for testing RAM memories connected to an FPGA circuit on Combo cards. In theoretical part of the work RAM faults are sorted by the way they affect the function of the memory and the algorithms to detect them are specified. In practical part, the methodology for testing RAM memories located on Combo cards are proposed, implemented and verified. The NetCOPE framework was used for the implementation. Within the NetCOPE structure, the project was divided into a hardware accelerated application for an FPGA circuit and a software application for a host computer. The project was designed with respect to an easy transfer to other versions of Combo cards.

La mémoire Flash est actuellement extrêmement utilisée en tant que mémoire non volatile pour le stockage des données numériques dans presque tout type d'appareil électronique nomade (ordinateur portable, téléphone mobile, tablette, …). Pour dépasser ses limites actuelles (densité d'informations, endurance, rapidité), un grand nombre de recherches se développent notamment autour du concept de mémoires résistives qui repose sur la commutation entre différents niveaux de résistance, via l'application d'une tension.Les mémoires dont la variation de résistance dépend de réactions électrochimiques (ReRAM) sont potentiellement de bonnes candidates pour les mémoires non volatiles de prochaine génération; les mécanismes d'oxydo-réduction impliqués sont cependant souvent de type filamentaire, mettant notamment en jeu des migrations de cations d’éléments métalliques (provenant des électrodes), ou de lacunes d’oxygène. Ce caractère filamentaire rend difficilement atteignable la miniaturisation extrême, à l’échelle nanométrique.Dans cette thèse, une classe de matériaux particulière -utilisée dans le domaine du stockage d'énergie- est étudiée. L’objectif est d’approfondir l’origine des processus de commutation de résistance observés sur des films de LixCoO2. Nous caractérisons d'abord les propriétés structurales et électriques de tels films, ainsi que le comportement électrique des dispositifs élaborés à partir de ces films. Nous étudions ensuite les mécanismes électrochimiques qui sont à l’origine des commutations résistives, dans la configuration d’un contact micrométrique électrode/film/électrode. Nous cherchons à déterminer la validité d’un mécanisme qui avait été proposé auparavant, mais non démontré. Nous étudions également la cinétique de commutation des dispositifs, et proposons un modèle numérique permettant d’expliquer les résultats expérimentaux observés. Enfin, nous étudions l’applicabilité potentielle des dispositifs (intégrant les films de LixCoO2) aux mémoires Re-RAM au travers de leurs performances en termes d’endurance (nombre maximum de cycles d’écriture/effaçage), et de stabilité. En particulier, nous étudions l’influence de plusieurs paramètres (impulsions de tension, nature des électrodes, température et c…) sur ces performances. / Flash memory is now extensively used as non-volatile memory for digital data storage in most mobile electronic devices (laptop, mobile phone, tablet...). To overcome its current limits (e.g. low information density, low endurance and slow speed), many researches recently developed around the concept of resistive memories based on the switching between different resistance levels by applying appropriate bias voltages.Memories whose resistance variations depend on electrochemical reactions (ReRAM) are potentially good candidates towards next-generation non-volatile memories. The underlying redox mechanisms observed are however often of the filamentary type, involving in particular migration of cations of metal elements (coming from the electrodes), or oxygen vacancies. This filamentary character makes it challenging to attain extreme downscaling towards the nanometric scale.In this thesis, a particular class of materials - used in the field of energy storage - is studied. The aim is to investigate the origin of the resistance switching processes observed in LixCoO2 films. We first characterize the structural and electrical properties of such films, as well as the electrical behaviors of the devices elaborated therefrom. We then investigate the electrochemical mechanisms which are at the origin of resistive switching, in the micrometric electrode/film/electrode configuration. We try to determine the validity of a formerly proposed mechanism which was however not yet demonstrated. Furthermore, we study the experimental switching kinetics of devices, and propose a numerical model to explain the results observed. Finally, we examine the potential applicability of LixCoO2-based devices to Re-RAM memories through the study of their performances in terms of endurance (i.e. maximum number of write/erase cycles) and retention. Specifically, the influence of several parameters (such as voltage pulses, chemical nature of the electrodes, temperature etc.) on these performances is investigated.