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Design and Implementaion of a High-Performance Memory GeneratorLee, Wan-Ping 18 August 2004 (has links)
The SRAM memory generator in this thesis is divided into four parts: row decoder, storage cell, column decoder, and sense amplifier & write controller. The row decoder is designed using pass-transistors logic with better area and regularity compared with conventional NAND based decoders. Two different column decoders, tree structure and NOR based predecoder, are provided in current version. Although only SRAM is implemented in this thesis, the memory generator platform is complete with all the necessary models required in the embedded design. In the future, other memories, such as cache, shift register, FIFO, stacks, ROM, register files, and content addressable memory, can be integrated in this memory generator platform.
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An energy efficient cache design using spin torque transfer (STT) RAMRasquinha, Mitchelle 23 August 2011 (has links)
The advent of many core architectures has coincided with the energy and power
limited design of modern processors. Projections for main memory clearly show
widening of the processor-memory gap. Cache capacity increased to help reduce
this gap will lead to increased energy and area usage and due to small growth in
die size, impede performance scaling that has accompanied Moore's Law to date.
Among the dominant sources of energy consumption is the on-chip memory hierar-
chy, specically the L2 cache and the Last Level Cache (LLC). This work explores
the use of a novel non-volatile memory technology - Spin Torque Transfer RAM
(STT RAM)" for the design of the L2/LLC caches. While STTRAM is a promising
memory technology, it has some limitations, particularly in terms of write energy and
write latencies. The main objectives of this thesis is to use a novel cell design for a
non-volatile 1T1MTJ cell and demonstrate its use at the L2 and LLC cache levels
with architectural optimizations to maximize energy reduction. The proposed cache
hierarchy dissipates significantly lesser energy (both leakage and dynamic) and uses
less area in comparison to a conventional SRAM based cache designs.
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A Study on Random Access Performance in Next Generation Mobile Network Systems / En studie i random access prestanda i nästa generations mobila nätverkssystemThalén, Magnus January 2015 (has links)
The next generation of mobile telecommunication, 5G, will be specified in the near future. One of the proposed changes relative to the previous generation, 4G,is the inclusion of a new system control plane (SCP). The purpose of the SCP is to improve system scalability, forward compatibility, peak performance and to enable a higher degree of support for advanced antenna techniques. This is done by logically separating data transmitted explicitly from and to the user, the dynamic transmissions, from the broadcasted transmissions that remain constant regardless of user activity, the static transmissions, and by then redesigning the static part to make it more lean. This is expected to have several positive effects such as considerably more free resources, resulting in energy savings and potentially increased usage of MIMO. Knowing what effect the SCP has upon aspects such as random access is of importance when designing the solution that will go into the standard. Simulations show that there is potential in the inclusion of the new SCP. While the simulated 5G candidate systems that include the SCP have an increased delay when running the random access procedure, some aspects of the procedure have been improved. The main differences relative to the simulated 4G system are the performance of the first message in the procedure, which increased, and the performance of the second message in the procedure, which decreased. The deficiencies found in the handling of the second message, however, can be alleviated by using a more proper algorithm and channel design than what was used in this study.
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A fast random access memoryJensen, John C. January 1973 (has links)
No description available.
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Analysis and design of efficient medium access control schemes for vehicular ad-hoc networksHan, Chong January 2012 (has links)
In this dissertation, analysis and design of the efficient Medium Access Control (MAC) sub-layer schemes are considered for Vehicular Ad hoc Networks (VANE~s). The contributions of this study are three-fold. First, an analytical model based on Markov chain is developed in order to investigate the performance of the MAC sub-layer of the IEEE 802.11p for vehicular communications. The results indicate that single channel MAC sub-layers may not be adequate for the future Intelligent Transportation Systems (ITS). The analytical model is validated with the results from simulation-based analysis. Performance analysis based on simulations is given on MAC metrics such as throughput, access delay, packet delivery. Second, a multi-channel MAC protocol is proposed and comprehensively analyzed in terms of channel utilizing and Quality of service (QoS) differentiation for dense VANETs. It is demonstrated that the proposed scheme, namely Asynchronous Multichannel MAC with Distributed TDMA (AMCMACD), improves the system performance in terms of throughput, packet delivery rate, collision rate on service channels, load balancing, and service differentiation for dense vehicular networks. Third, to cope with the interference from contention with neighbours within two hops in large-scale networks, a Large-scale Asynchronous Multichannel MAC (LS-AMCMAC) is proposed. The proposed scheme outperforms other benchmark multichannel MAC schemes in large-scale networks, in terms of throughput, channel utilization, dissemination of emergency messages, and the collision rates on control and service channels.
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Wide I/O DRAM architecture utilizing proximity communicationHarvard, Qawi IbnZayd. January 2009 (has links)
Thesis (M.S.)--Boise State University, 2009. / Title from t.p. of PDF file (viewed May 24, 2010). Includes abstract. Includes bibliographical references (leaves 79-82).
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Wide I/O DRAM architecture utilizing proximity communication /Harvard, Qawi IbnZayd. January 2009 (has links)
Thesis (M.S.)--Boise State University, 2009. / Includes abstract. Includes bibliographical references (leaves 79-82).
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Schemes for reducing power and delay in SRAMsBlomster, Katie Ann, January 2006 (has links) (PDF)
Thesis (M.S. in computer engineering)--Washington State University, August 2006. / Includes bibliographical references (p. 83-84).
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Aspects of the theory of weightless artificial neural networksNtourntoufis, Panayotis January 1994 (has links)
No description available.
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A Performance Analysis of a CSMA Multihop Packet Radio NetworkMulligan, Jeanette 20 June 1997 (has links)
In a packet radio network, multiple terminals broadcast information over a shared communications medium. Messages are transmitted from a source terminal to a destination terminal over multiple relays or hops. The actions of one terminal in the network directly affect the actions of other terminals within its range.
The analysis of packet radio networks is complex because system performance depends on the topology of the terminals in the network along with the random access protocol used. Researchers have been unable to model a packet radio network in its most general form. In this project, a model is developed for specific topologies of a packet radio network with a given random access protocol.
The sponsor of this project has developed a packet radio network for an indoor wireless alarm system. At the start of the project, the effect of message collisions on system performance was unknown. As a result of this research, a collision model for the network has been developed for topologies of four, five, and six alarm units. The model has been validated with actual system testing. Furthermore, the effects of indoor propagation on system performance have been studied. The results of this work have led to the development of an installation plan for the indoor wireless alarm system. / Master of Science
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