Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 92-98).

Thesis (M.S.)--University of Missouri-Columbia, 2008. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.

Thesis (M.S.)--Florida State University, 2005. / Advisor: Dr. Kartik Gopalan, Florida State University, College of Arts and Sciences, Dept. of Computer Science. Title and description from dissertation home page (viewed June 8, 2005). Document formatted into pages; contains ix, 41pages. Includes bibliographical references.

abstract: LTE-Advanced networks employ random access based on preambles transmitted according to multi-channel slotted Aloha principles. The random access is controlled through a limit <italic>W</italic> on the number of transmission attempts and a timeout period for uniform backoff after a collision. We model the LTE-Advanced random access system by formulating the equilibrium condition for the ratio of the number of requests successful within the permitted number of transmission attempts to those successful in one attempt. We prove that for <italic>W</italic>&le;8 there is only one equilibrium operating point and for <italic>W</italic>&ge;9 there are three operating points if the request load &rho; is between load boundaries &rho;₁ and &rho;₂. We analytically identify these load boundaries as well as the corresponding system operating points. We analyze the throughput and delay of successful requests at the operating points and validate the analytical results through simulations. Further, we generalize the results using a steady-state equilibrium based approach and develop models for single-channel and multi-channel systems, incorporating the barring probability <italic>P<super>B</super></italic>. Ultimately, we identify the de-correlating effect of parameters <italic>O, P<super>B</super>,</italic> and <italic>T_o<super>max</super></italic> and introduce the Poissonization effect due to the backlogged requests in a slot. We investigate the impact of Poissonization on different traffic and conclude this thesis. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2014

Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications’ performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing unaccessed devices to be put into power-down mode, hence saving power to meet a certain power budget.

No description available.

Internet of things (IoT) is envisioned as a promising paradigm to interconnect enormous wireless devices. However, the success of IoT is challenged by the difficulty of access management of the massive amount of sporadic and unpredictable user traffics. This thesis focuses on the contention-based random access in massive cellular IoT systems and introduces two novel frameworks to provide enhanced scalability, real-time quality of service management, and resource efficiency. First, a local communication based congestion control framework is introduced to distribute the random access attempts evenly over time under bursty traffic. Second, a multi-agent reinforcement learning based preamble selection framework is designed to increase the access capacity under a fixed number of preambles. Combining the two mechanisms provides superior performance under various 3GPP-specified machine type communication evaluation scenarios in terms of achieving much lower access latency and fewer access failures. / Master of Science / In the age of internet of things (IoT), massive amount of devices are expected to be connected to the wireless networks in a sporadic and unpredictable manner. The wireless connection is usually established by contention-based random access, a four-step handshaking process initiated by a device through sending a randomly selected preamble sequence to the base station. While different preambles are orthogonal, preamble collision happens when two or more devices send the same preamble to a base station simultaneously, and a device experiences access failure if the transmitted preamble cannot be successfully received and decoded. A failed device needs to wait for another random access opportunity to restart the aforementioned process and hence the access delay and resource consumption are increased. The random access control in massive IoT systems is challenged by the increased access intensity, which results in higher collision probability. In this work, we aim to provide better scalability, real-time quality of service management, and resource efficiency in random access control for such systems. Towards this end, we introduce 1) a local communication based congestion control framework by enabling a device to cooperate with neighboring devices and 2) a multi-agent reinforcement learning (MARL) based preamble selection framework by leveraging the ability of MARL in forming the decision-making policy through the collected experience. The introduced frameworks are evaluated under the 3GPP-specified scenarios and shown to outperform the existing standard solutions in terms of achieving lower access delays with fewer access failures.

With a view to reduce the number of components in a Static Random Access Memory (SRAM) cell, the feasibility of use of Lambda Bipolar Transistor (LBT)in the bistable element of the cell has been explored under the present study. The LBT under consideration here comprises of an enhancement mode MOSFET integrated with a parasitic bipolar transistor so as to perform as a negative resistance device. LBTs for the study have been fabricated and analysed. The devices have been shown to function at much lower voltage and current levels than those reported earlier/ and thus have been shown to be suitable for lower power applications. The issues of agreements and discrepancies of the experimental results with the original DC model of the device have been highlighted and discussed. The factors contributing to the drain current of the MOSFET in the LBT have been identified. It has also been shown that in the real case of an LBT in operation, the MOSFET in it does not function as a discrete device for the same conditions of voltages and current levels as in an LBT. As per the present study, it is assessed to be influenced by the presence of the BJT in operation and this effect is felt more at the lower current levels of operation. With a separate and tailored p-well implantation the possibility of fabrication of LBTs with a CMOS technology is established. Along with a couple of polysilicon resistors, the LBTs have been successfully made to perform in the common-collector configuration as the bistable storage element of SRAM cell (as proposed in the literature). The bistable element with the LBT in common-emitter mode also has been visualised and practically achieved with the fabricated devices. The WRITE transients for either case have been simulated for various levels of WRITE voltages and their time of hold.The speed of Writing achieved are found comparable with that of the standard SRAMs. The advantages and disadvantages of using the LBT in either mode have been highlighted and discussed. The power consumption of the bistable element with the LBT in either mode is however shown to be the same. A different approach of READING has been proposed to overcome the factors known to increase the cycle time. On the whole, under the present study, the proposal of using LBTs in the bistable storage element of the SRAM cell has been shown to be feasible. Such SRAM circuits can find possible applications in the fields where smaller circuit area is the major concern.

Digital radiographic images are created by a variety of diagnostic imaging modalities. A multi-modality workstation, known as the Arizona Viewing Console (AVC), was designed and built by the University of Arizona Radiology Department to support research in radiographic image processing and image display. Two specially designed VMEbus components, the base image memory and the video display memory, were integrated into the AVC and are the subject of this thesis. The base image memory is a multi-ported, 8 megabyte memory array based on random access memory used for raw image storage. It supports a 10 megapixel per second image processor and can interface to a 320 megabit per second network. The video display memory utilizes video memories and is capable of displaying two independent high resolution images, each 1024 pixels by 1536 lines, on separate video monitors. In part, these two memory designs have allowed the AVC to excel as a radiographic image workstation.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaf 73. / by Oliver Chukwudi Ibe. / M.S.