A DRAM communicates with a processing unit via two interfaces: a data interface and a command interface. In today's DRAMs, also known as synchronous DRAMs (SDRAMs), both interfaces use a clock to communicate with the processing unit. The clock times the communication between the processing unit and the SDRAM on both the data interface and the command interface. We propose a self-timed DRAM. The self-timed DRAM introduces more flexibility into the DRAM interface by eliminating the clock. The command interface and the data interface each communicate with the processing unit using a handshake protocol rather than a clock. This thesis presents the data interface between the self-timed DRAM and the processing unit. The proposed data interface is self-timed. The self-timed data interface allows the DRAM to deliver data to or accept data from the processing unit as the processing unit demands rather than on a schedule set from the command interface. The self-timed data interface is designed using GasP circuits and micropipeline circuits. The design is simulated in 180nm CMOs process technology using hspice. This thesis presents the effects of width mismatch on the self-timed data interface. The micropipeline is slightly faster than the GasP. Also, the thesis compares the self-timed DRAM data interface with synchronous DRAM for the data burst rate.

Two common goals in computing system design are increasing performance and decreasing power consumption. DRAM-based memory subsystems are a major component of both system performance and power consumption. Memory controllers employ strategies to efficiently schedule DRAM operations to reduce latency and to utilize DRAM low power modes when possible. One of the most important of these is the page policy, which determines when to close pages in DRAM. An effective DRAM memory controller page policy is important to minimizing power consumption and increasing system performance. This thesis explores the impact memory controller page policy has on performance as measured by the number of page-hits minus page-misses and estimated average memory access latency. I captured real-time DDR3 command and address memory traces for the SPEC CPU2006 benchmarks under three memory controller page policies: closed page, fixed open-page, and Intel's adaptive open-page [1]. Traces were captured using a programmable memory traffic analyzer (PMTA), a device interposed between the DIMM slot and DDR3 DIMM on the motherboard. The memory traces for each benchmark were analyzed to determine the absolute number of page-hits and page-misses that occurred. In software post-processing I simulated a theoretically perfect "oracle" page policy for each captured trace to compare the efficiency of existing policies. The SPEC CPU 2006 benchmarks under the oracle page policy for each trace exhibited an average increase in the number of page-hits minus page-misses of 280.3% and an average decrease in the average memory latency of 11.1%. Two new adaptive open-page policies are proposed and simulated using the captured memory traces. These proposed policies result in an average increase of 74.8% and 62.4% in the number of page-hits minus page-misses over Intel's adaptive open-page policy and an average decrease in the average memory latency of 3.8% and 3.4%.

Despite the use of strong encryption schemes, one can still learn information about encrypted data using side channel attacks [2]. Watching what physical memory is being accessed can be such a side channel. One can hide this information by using oblivious simulation - hiding the true access pattern of a program. In this paper we will review the model behind oblivious simulation, attempt to formalize the problem and define a security game. We will review the major solutions pro- posed so far, the square root and hierarchical solutions, as well as propose a new variation on the square root solution. Additionally, we will show a new formalization for providing software protection by using an encryption scheme and oblivious simulation.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第18623号 / 情博第547号 / 新制||情||97(附属図書館) / 31523 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 守倉 正博, 教授 高橋 達郎, 教授 梅野 健 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

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京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24746号 / 情博第834号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 佐藤 高史, 教授 橋本 昌宜, 教授 新津 葵一 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

As the semiconductor industry grapples with escalating scaling challenges associated with the floating gate MOSFET, alternative memory technologies like Resistive Random Access Memory (ReRAM) are gaining prominence in the scientific community. Boasting a straightforward device structure, ease of fabrication, and compatibility with CMOS (Complementary Metal-oxide Semiconductor) Back-end of Line (BEOL), ReRAM stands as a leading candi- date for the next generation of non-volatile memory (NVM). ReRAM devices feature nanoionics-based filamentary switching, outperforming flash memory in terms of power consumption, scalability, retention, ON/OFF ratio, and endurance. Furthermore, integrating ReRAMs within the CMOS BEOL/low-k Cu interconnect system not only reduces latency between the connectivity constraints of logic and memory modules but also minimizes the chip footprint. However, investigations have revealed a significant concern surrounding ReRAMs—specifically, their electro-thermal reliability. This research provides evidence highlighting the critical influence of material properties, deposition effects, and thermal transport on the device's performance and reliability. Various material systems have undergone in this work scrutiny to comprehend the impact of intrinsic material properties such as thermal conductivity, specific heat capacity, thermal diffusivity, and deposition effects like surface roughness on the electroforming voltages of ReRAM devices. The reference device structure considered in this work is Cu/TaOx/Pt, which has been compared with alternative configurations involving metals like Ru and Co as potential substitutes for Pt. Additionally, a new vehicle has been introduced to quantify cell degradation resulting from thermal cross-talk in crossbar Resistive Random Access Memory (ReRAM) arrays. Furthermore, a novel methodology has been presented to predict cell degradation due to remote heating, taking into account the cell's location, the material properties of the device, and geometry of its electrodes. The experimental results presented in this study showcase filament rupture caused by remote heating, along with spontaneous filament restoration ensuing from the subsequent cooling of the ReRAM cell. / Doctor of Philosophy / As the demand for compact, high-speed logic-memory modules continues to surge, the diminishing silicon real estate in our gadgets poses a challenge in extending Moore's law to meet the scaling needs of the semiconductor device industry. To tackle this challenge, emerging memory technologies like Resistive Random Access Memory (ReRAM) are positioned as promising successors to flash memory. ReRAM devices offer distinct advantages over flash memory, showcasing superior power consumption, scalability, long retention, a high ON/OFF ratio, and good endurance. Their compatibility with current CMOS (Complementary Metal-oxide Semiconductor) technology facilitates seamless integration. However, a significant concern associated with ReRAMs is their electro-thermal reliability. This research delves into how material properties comprising a ReRAM device and fabrication factors, such as the surface roughness of the material, can impact the electrical and thermal reliability of a ReRAM cell. In this context, a novel methodology has been introduced to predict cell degradation within ReRAM crossbar arrays induced by thermal cross-talk, considering material properties and the geometry of the device. The new methodology has been thoroughly verified on manufactured ReRAM arrays with various composite electrodes. The study also presents experimental results demonstrating the rupture of cell filaments due to remote heating, along with instances of spontaneous filament restoration due to subsequent cooling.