Cette thèse vise principalement à faire face à la fiabilité de stockage de STT-MRAM au niveau dispositif, au niveau circuit et au niveau système. Les majeures contributions de cette thèse peuvent être résumées comme il suit: a) La modélisation de la jonction tunnel magnétique par courant polarisé en spin (STT-MTJ), pour développer un compact modèle SPICE de STT-MTJ. b) Le design de fiabilité de STT-MRAM au niveau dispositif, pour étudier les structures de base de cellule de mémoire et de cellules de référence. Dans cette partie, nous avons proposé une cellule de mémoire configurable (CMC), une cellule dynamique de référence (RDC) et un loquet magnétique de rayonnement durci (RHM-Latch). c) Le design de fiabilité de STT-MRAM au niveau circuit, pour étudier les modules de circuits périphériques. Dans cette partie, nous avons proposé un circuit de lecture séparé et précharge (SPCRC), un circuit de lecture offset-Tolérant sans perturbation (OTDFRC) et un circuit de correction d'erreur intégré. d) Le design de fiabilité de STT-MRAM au niveau système, vise principalement à étudier l'architecture de la puce. Dans cette partie, nous avons proposé une architecture reconfigurable (nommé Re-STT-MRAM) et une architecture de correction d'erreur hybride (nommé cRR-SECC). / This thesis aims mainly to deal with the storage reliability of STT-MRAM from device-Level, circuit-Level and system-Level perspectives. The major contributions of this thesis can be summarized as follows: a) Spin transfer torque magnetic tunnel junction (STT-MTJ) modeling, to develop a compact SPICE model of STT-MTJ.b) Device-Level reliability design of STT-MRAM, to study the basic memory cell and reference cell structures. We proposed a configurable memory cell (CMC), a dynamic reference cell (DRC) and a radiation hardened magnetic latch (RHM-Latch) in this part.c) Circuit-Level reliability design of STT-MRAM, to study the peripheral circuit modules. We proposed a separated pre-Charge read circuit (SPCRC), an offset-Tolerant disturbance-Free read circuit (OTDFRC) and a built-In error correction circuit in this part.d) System-Level reliability design of STT-MRAM, aims mainly to study the chip architecture. We proposed a reconfigurable architecture and a hybrid error correction architecture in this part.

Over the past few decades, wireless local area networks (WLANs) have been widely deployed for data communication in indoor environments such as offices, houses, and airports. In order to fairly and efficiently use the unlicensed frequency band that Wi-Fi devices share, the devices follow a set of channel access rules, which is called a wireless medium access control (MAC) protocol. It is known that wireless devices following the 802.11 standard MAC protocol, i.e. the distributed coordination function (DCF), suffer from packet collisions when multiple nodes simultaneously transmit. This significantly degrades the throughput performance. Recently, several studies have reported access techniques to reduce the number of packet collisions and to achieve a collision free WLAN. Although these studies have shown that the number of collisions can be reduced to zero in a simple way, there have been a couple of remaining issues to solve, such as dynamic parameter adjustment and fairness to legacy DCF nodes in terms of channel access opportunity. Recently, In-Band Full Duplex (IBFD) communication has received much attention, because it has significant potential to improve the communication capacity of a radio band. IBFD means that a node can simultaneously transmit one signal and receive another signal in the same band at the same time. In order to maximize the performance of IBFD communication capability and to fairly share access to the wireless medium among distributed devices in WLANs, a number of IBFD MAC protocols have been proposed. However, little attention has been paid to fairness issues between half duplex nodes (i.e. nodes that can either transmit or receive but not both simultaneously in one time-frequency resource block) and IBFD capable nodes in the presence of the hidden node problem.

Massive MIMO communication systems have been highlighted as the main technology for physical layer of next generation communication standards, like 5G. While conventional communication between BS and its covered users is performed in orthogonal time-frequency resources, the improved interuser interference mitigation capability provided by the large number of BS antennas enables the BS to communicate with several users in the same time-frequency resource. This better usage of available but scarce spectrum elevates the spectral efficiency to very appreciable levels, and has a similar effect on energy efficiency, since the transmit power is not increased. On the other hand, if the objective is to provide a target performance for the users, the required transmit power in both direct and reverse links can be made inversely proportional to the number of BS antennas employed. In this Doctoral Thesis, several important aspects of massive MIMO systems are systematically investigated aiming to improve their energy and spectral efficiencies. We can enumerate our main contributions as follows. Considering a cellular massive MIMO network, we proposed an optimized assignment policy of training sequences to the users, which is then combined with suitable power control algorithms. We have also investigated the adoption of alternative waveforms in this scenario, such as single-carrier transmission, in order to overcome the issues of conventional OFDM. Our contributions in this topic are to derive analytical performance expressions for a time-domain single-carrier equalizer taking advantage of the large number of BS antennas, and to evaluate and compare the total energy efficiency of OFDM versus single-carrier massive MIMO systems. Finally, considering crowded massive MIMO networks, composed by both human users as well as machine-type communication devices, we proposed an improved random access protocol aiming to decrease the average number of access attempts for the users and decreasing the probability of failed access attempts. / Sistemas de comunicação de múltiplas antenas (multiple-input multiple-output - MIMO) têm se destacado como a principal tecnologia para a camada física dos padrões de comunicação da próxima geração, como o 5G. Enquanto a comunicação convencional entre a estação base (base station - BS) e seus usuários atendidos é realizada em recursos ortogonais de tempo-frequência, a grande capacidade de redução da interferência interusuários possibilitada pelo grande número de antenas da BS habilita a BS a se comunicar com diversos usuários no mesmo recurso tempo-frequência. Este melhor uso do escasso espectro disponível eleva a eficiência espectral a níveis muito apreciáveis, e tem um efeito similar na eficiência energética, pois a potência de transmissão não é aumentada. Por outro lado, se o objetivo é fornecer um desempenho desejado para os usuários, a potência de transmissão necessária em ambos os enlaces direto e reverso pode ser feita inversamente proporcional ao número de antenas na BS. Nesta Tese de Doutorado, diversos aspectos importantes de sistemas MIMO massivo são sistematicamente investigados com o objetivo de melhorar suas eficiências energética e espectral. Pode-se enumerar as principais contribuições alcançadas como se segue. Considerando uma rede celular MIMO massivo, propõe-se uma política de atribuição de sequências de treinamento aos usuários otimizada, a qual é depois combinada com apropriados algoritmos de controle de potência. Também investiga-se a adoção neste cenário de formas de onda alternativas, tal como a transmissão de portadora única, visando superar as deficiências da convencional multiplexagem por divisão de portadoras ortogonais (orthogonal frequency-division multiplexing - OFDM). As principais contribuições obtidas neste tema são derivar expressões de desempenho analíticas para um equalizador de portadora única no domínio do tempo que aproveita o grande número de antenas na BS, e avaliar e comparar a eficiência energética total de sistemas MIMO massivo OFDM versus portadora única. Finalmente, considerando redes MIMO massivo sobrecarregadas, compostas por usuários humanos bem como dispositivos de comunicação do tipo máquina, propõe-se um protocolo de acesso aleatório melhorado visando diminuir o número médio de tentativas de acesso para os usuários e diminuir a probabilidade de falhas de tentativa de acesso.

With CMOS technology scaling reaching its limitations rigorous research of alternate and competent technologies is paramount to push the boundaries of computing. Spintronic and resistive memories have proven to be effective alternatives in terms of area, power and performance to CMOS because of their non-volatility, ability for logic computing and easy integration with CMOS. However, deeper investigations to understand their physical phenomenon and improve their properties such as writability, stability, reliability, endurance, uniformity with minimal device-device variations is necessary for deployment as memories in commercial applications. Application of these technologies beyond memory and logic are investigated in this thesis i.e. for security of integrated circuits and systems and special purpose memories. We proposed a spintonic based special purpose memory for search applications, present design analysis and techniques to improve the performance for larger word lengths upto 256 bits. Salient characteristics of RRAM is studied and exploited in the design of widely accepted hardware security primitives such as Physically Unclonable Function (PUF) and True Random Number Generators (TRNG). Vulnerability of these circuits to adversary attacks and countermeasures are proposed. Proposed PUF can be implemented within 1T-1R conventional memory architecture which offers area advantages compared to RRAM memory and cross bar array PUFs with huge number of challenge response pairs. Potential application of proposed strong arbiter PUF in the Internet of things is proposed and performance is evaluated theoretically with valid assumptions on the maturity of RRAM technology. Proposed TRNG effectively utilizes the random telegraph noise in RRAM current to generate random bit stream. TRNG is evaluated for sufficient randomness in the random bit stream generated. Vulnerability and countermeasures to adversary attacks are also studied. Finally, in thesis we investigated and extended the application of emerging non-volatile memory technologies for search and security in integrated circuits and systems.

The objective of the research was to design and test an SRAM system which can meet the performance criteria for Memory Based Computing (MBC). This form of computing consists of a Look-Up Table (LUT) which is basically memory array mapped with a function; the computations thereafter consist of essentially read operations. An MBC framework requires very fast and low power read operations. Moreover, the cells need to be read stable as major part of the computation is done by reading the LUTs mapped in the SRAM array. Design and measurement of a prototype MBC test-chip with SRAM system optimized for read-heavy applications is presented in this thesis. For this purpose, a prototype MBC system was designed and taped out. Essential study of the write-ability of the core LUT is also presented. The core memory array for function table mapping was characterized for leakage, write-ability and power saving associated with pulsed read mode.

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.

The PhD thesis focuses on the always-on low power SRAM memories (essentially low dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the state of the art of the eSRAM and describes different techniques to reduce the static and dynamic power consumption with respect the variability issue. Main techniques of power reduction are reviewed with their contributions and their limitations. It presents also a discussion about a statistical variability modeling and the variability effects on the yield. An original low power architecture based on 5T-Portless bit-cell is presented, with current mode read/write operations, as an ideal candidate for the always-on SRAM memories. A test chip implementation in CMOS 32nm of the 5T-Porless is designed and a comparison with an existing 6T SRAM memory is presented based on simulation. Some test chip functionality results and power consumption are performed. Finally the conclusion highlights the major contributions of the study and discusses the various simplification assumptions to see possible limitations. It is concluded affirmatively about industrial interest of the 5T-Portless SRAM for always-on embedded applications. Perspectives concern the analytical modeling for statistical behavior of SRAM as the Monte-Carlo approach is no more practicable. The migration of the 5T-Portless SRAM may be already considered in advanced nodes.

Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

Various data structures have been proposed for representing the connectivity of manifold triangle meshes. For example, the Extended Corner Table (ECT) stores V+6T references, where V and T respectively denote the vertex and triangle counts. ECT supports Random Access and Traversal (RAT) operators at Constant Amortized Time (CAT) cost. We propose two novel variations of ECT that also support RAT operations at CAT cost, but can be used to represent and process Simplicial 2-Complexes (S2Cs), which may represent star-connecting, non-orientable, and non-manifold triangulations along with dangling edges, which we call sticks. Vlist stores V+3T+3S+3(C+S-N) references, where S denotes the stick count, C denotes the number of edge-connected components and N denotes the number of star-connecting vertices. Ering stores 6T+3S+3(C+S-N) references, but has two advantages over Vlist: the Ering implementation of the operators is faster and is purely topological (i.e., it does not perform geometric queries). Vlist and Ering representations have two principal advantages over previously proposed representations for simplicial complexes: (1) Lower storage cost, at least for meshes with significantly more triangles than sticks, and (2) explicit support of side-respecting traversal operators which each walks from a corner on the face of a triangle t across an edge or a vertex of t, to a corner on a faces of a triangle or to an end of a stick that share a vertex with t, and this without ever piercing through the surface of a triangle.

Dans le domaine des réseaux satellitaires, l'apparition de terminaux interactifs à bas-prix nécessite le développement et la mise en œuvre de protocoles d'accès multiple capables de supporter différents profils d'utilisateurs. En particulier, l'Agence Spatiale Européenne (ESA) et le centre d'étude spatial allemand (DLR) ont récemment proposé des protocoles d'accès aléatoires basés sur le codage réseau couche physique et l'élimination itérative des interférences pour résoudre en partie le problème de collisions sur une voie de retour du type Slotted ALOHA. C'est dans ce contexte que s'inscrit cette thèse qui vise à fournir une amélioration dans des méthodes d'accès aléatoires existantes. Nous introduisons Multi-Slot Coded Aloha (MuSCA) comme une nouvelle généralisation of CRDSA. Au lieu de transmettre des copies du même paquet, l'émetteur envoie plusieurs parties d'un mot de code d'un code correcteur d'erreurs ; chaque partie étant précédée d'un entête permettant de localiser les autres parties du mot de code. Au niveau du récepteur, toutes les parties envoyées par le même utilisateur, y compris celles qui sont interférées par d'autres signaux, participent au décodage. Le signal décodé est ensuite soustrait du signal total. Ainsi, l'interférence globale est réduite et les signaux restant ont plus de chances d'être décodés. Plusieurs méthodes d'analyse de performance basées sur des concepts théoriques (calcul de capacité, évolution des densités) et sur des simulations sont proposées. Les résultats obtenus montrent un gain très significatif de débit global comparé aux méthodes d'accès existantes. Ce gain peut encore être augmenté en variant le taux de découpe des mots de code. En modifiant certains de ces concepts, nous proposons également une application du codage réseau couche physique basée sur la superposition de modulations pour l'accès déterministe à la voie retour des communications par satellite. Une amélioration du débit est aussi obtenue par rapport à des stratégies plus classiques de multiplexage temporal. / In the domain of satellite networks, the emergence of low-cost interactive terminals motivates the need to develop and implement multiple access protocols able to support different user profiles. In particular, the European Space Agency (ESA) and the German Aerospace Center (DLR) have recently proposed random access protocols such as Contention Resolution Diversity Coded ALOHA (CRDSA) and Irregular Repetition Slotted ALOHA (IRSA). These methods are based on physical-layer network coding and successive interference cancellation in order to attempt to solve the collisions problem on a return channel of type Slotted ALOHA.This thesis aims to provide improvements of existing random access methods. We introduce Multi-Slot Coded Aloha (MuSCA) as a new generalization of CRDSA. Instead of transmitting copies of the same packet, the transmitter sends several parts of a codeword of an error-correcting code ; each part is preceded by a header allowing to locate the other parts of the codeword. At the receiver side, all parts transmitted by the same user, including those are interfered by other signals, are involved in the decoding. The decoded signal is then subtracted from the total signal. Thus, the overall interference is reduced and the remaining signals are more likely to be decoded. Several methods of performance analysis based on theoretical concepts (capacity computation, density evolution) and simulations are proposed. The results obtained show a significant gain in terms of throughput compared to existing access methods. This gain can be even more increased by varying the codewords stamping rate. Following these concepts, we also propose an application of physical-layer network coding based on the superposition modulation for a deterministic access on a return channel of satellite communications. We observe a gain in terms of throughput compared to more conventional strategies such as the time division multiplexing.