付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第24891号 / 工博第5171号 / 新制||工||1987(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 白石 誠司, 准教授 掛谷 一弘, 教授 小野 輝男, 教授 森山 貴広 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

No / This paper is not a survey related to generic wireless sensor networks (WSNs), which have been largely treated in a number of survey papers addressing more focused issues; rather, it specifically addresses architectural aspects related to WSNs in some way connected with a satellite link, a topic that presents challenging interworking aspects. The main objective is to provide an overview of the potential role of a satellite segment in future WSNs. In this perspective, requirements of the most meaningful WSN applications have been drawn and matched to characteristics of various satellite/space systems in order to identify suitable integrated configurations. Copyright (c) 2012 John Wiley & Sons, Ltd.

Physically unclonable functions are increasingly used as security primitives for device identification and anti-counterfeiting. However, PUFs are associated with noise and bias which in turn affects its property of reliability and predictability. The noise is corrected using fuzzy extractors, but the helper data generated during the process may cause leakage in min-entropy due to the bias observed in the response. This thesis offers two optimization techniques for PUF based protocols. The first part talks about the construction of a secure enrollment solution for PUFs on a low-end resource-constrained device using a microcontroller and a secure networked architecture. The second part deals with the combined optimization of min-entropy and error-rate using symbol clustering techniques to improve the reliability of SRAM PUFs. The results indicate an increase in min-entropy without much effect on the error rate but at the expense of PUF size. / Master of Science

High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test data volume and test application time. The degree of test data volume reduction depends on the fault coverage achievable in the broadcast mode. However, the fault coverage achieved in the broadcast mode of ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in ILS are either ad-hoc or use test pattern information from an a-priori automatic test pattern generation (ATPG) run. In this thesis, we present novel low cost techniques to construct ILS scan configuration for a given design. These techniques efficiently utilize the circuit topology information and try to optimize the flip-flop assignment to a scan chain location without much compromise in the fault coverage in the broadcast mode. Thus, they eliminate the need of an a-priori ATPG run or any test set information. In addition, we also propose a new scan architecture which combines the broadcast mode of ILS and Random Access Scan architecture to enable further test volume reduction on and above effectively configured conventional ILS architecture using the aforementioned heuristics with reasonable area overhead. Experimental results on the ISCAS'89 benchmark circuits show that the proposed ILS configuration methods can achieve on an average 5% more fault coverage in the broadcast mode and on average 15% more test data volume and test application time reduction than existing methods. The proposed new architecture achieves, on an average, 9% and 33% additional test data volume and test application time reduction respectively on top of our proposed ILS configuration heuristics. / Master of Science

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D.

Recently, the resistance switching random access memory (ReRAM) in several MIM systems has been studied extensively for applications to the next generation non-volatile memory (NVM) devices and memristors since the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult. ReRAM is being considered one of the most promising candidates for next generation non-volatile memory due to its relatively high switching speed, superior scalability, low power consumption, good retention and simple fabrication method. Cu/TaOX/Pt resistive switching device is a very good candidate due to its well performance and well characterization. However, since platinum (Pt) acting as the inert electrode is not economical efficient for industrial production, a compatible replacement of Pt is highly desirable. The device property of Co based resistive switching devices has been explored in this work. Compared with Pt devices, electric characterization of the fabricated Cu/TaOX/Co devices exhibits very similar FORM, SET and RESET voltages for Cu conductive filaments. However, for the oxygen vacancy (VO) filament the Co device has a significant smaller FORM, SET and RESET voltages of VO filament, which can be partly attributed to the work function difference between Pt and Co of 1.35 V and partly to the impaired integrity properties of Co vs Pt inert electrode. The limit of SET-RESET operations is mainly due to the geometrical shape of the Cu conductive filament is more cylindered rather than Cone-like shape as well as the high Joules heat dissipation. What’s more, ReRAM is also the most promising candidate for a flexible memory, as a variety of materials can be used both inorganics, organics and even hybrid nanocomposites. Besides inorganic ReRAM device, we also fabricated an organic ReRAM device with the structure Cu doped PANI-CSA/O-AA/Al. We have manufactured ReRAM based on Cu-doped PANI-CSA polymer electrode, O-AA as the polymer solid electrolyte and Al as the bottom electrode for the first time. This polymer device shows a significantly lower forming voltage than inorganic ReRAM devices such as Cu/TaOX/Pt. Our results also demonstrate that our organic ReRAM is a promising candidate for inexpensive candidate for inexpensive and environmentally friendly memory devices. We have demonstrated that the FORM operation of the polymer devices depends on the concentration of Cu+ ions as well as the thickness of the polymer electrode. / M.S. / Although the scaling of conventional memories such as volatile dynamic random access memory (DRAM) and non-volatile flash technology is becoming increasingly difficult, new types of non-volatile memories, such as resistive switching memories, have recently attracted the attention of both industry and academia. Resistive switching memory is considered as the next generation non-volatile memory because of its excellent scalability, high switching speed, simple structure and low power consumption. What’s more, ReRAM is also a promising candidate for a flexible memory, as a variety of materials can be used both inorganics, organics and even hybrid nanocomposites. ReRAM shows unique nanoionics based filamentary switching mechanism. Besides the nonvolatile memory applications, resistive switching devices implement the formation of a memristor, which is the fourth basic electrical component and can be used for neuromorphic computing. First, we report the device property of Co based resistive switching devices with a structure of Cu/TaOX/Co layers. The I-V characteristics of the manufactured Cu/TaOX/Co devices shows very similar FORM, SET and RESET voltages for Cu conductive filaments compared with Pt device. However, the Co device has a significant smaller FORM, SET and RESET voltages for oxygen vacancy (VO) filaments, which can be partly attributed to the work function difference between Pt and Co of 13.5 eV and partly to the impaired integrity properties of Co vs Pt inert electrode. The main reason for the limit of SET-RESET operations is that high Joules heat dissipation. With high Joules heat accumulation, the maximum switching cycles of Co devices is up to 8 times, while in the case of Pt cases, it is almost unlimited. Secondly, we fabricated an organic ReRAM device with the structure Cu-doped PANI-CSA/O-AA/Al. Cu-doped PANI-CSA polymer electrode has been introduced for the first time as the top polymer electrode of a ReRAM device. Compared to inorganic ReRAM device, this polymer device can be operated at a significantly lower forming voltage than inorganic devices such as Cu/TaOX/Pt. We have demonstrated that our organic ReRAM is a promising candidate for environmentally friendly and flexible memory devices. Our results demonstrate the FORM operation of the polymer devices depend on the concentration of Cu+ ions as well as the thickness of the polymer top layer.

Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit and device level innovations are required for existing memory technologies. Emerging memory solutions are widely explored to cater to strict budgets. This thesis presents design methodologies for custom memory design with the objective of power-performance benefits across specific applications. Taking example of STTRAM (spin transfer torque random access memory) as an emerging memory candidate, the design space is explored to find optimal energy design solution. A thorough thermal reliability study is performed to estimate detection reliability challenges and circuit solutions are proposed to ensure reliable operation. Adoption of the application-specific optimal energy solution is shown to yield considerable energy benefits in a read-heavy application called MBC (memory based computing). Circuit level customizations are studied for the volatile SRAM (static random access memory) memory, which will provide improved energy-delay product (EDP) for the same MBC application. Memory design has to be aware of upcoming challenges from not only the application nature but also from the packaging front. Taking 3D die-folding as an example, SRAM performance shift under die-folding is illustrated. Overall the thesis demonstrates how knowledge of the system and packaging can help in achieving power efficient and high performance memory design.

This thesis investigates a test method to detect the presence of Variable Retention Time (VRT) bits in manufactured DRAM. The VRT bits retention time is modeled as a 2-state random telegraph process that includes miscorrelation between test and use. The VRT defect is particularly sensitive to test and use conditions. A new test method is proposed to screen the VRT bits by simulating the use conditions during manufacturing test. Evaluation of the proposed test method required a bit-level VRT model to be parameterized as a function of temperature and voltage conditions. The complete 2-state VRT bit model combines models for the time-in-state and for the retention-time including miscorrelation. A copula is used to model the eect of miscorrelation between test and use. The proposed VRT test algorithm runtime is estimated as a function of VRT test coverage, test temperature and test voltage.

Graph algorithms are concerned with the algorithmic aspects of solving graph problems. The problems are motivated from and have application to diverse areas of computer science, engineering and other disciplines. Problems arising from these areas of application are good candidates for parallelization since they often have both intense computational needs and stringent response time requirements. Motivated by these concerns, this thesis investigates parallel algorithms for these kinds of graph problems that have at least one of the following properties: the problems involve some type of dynamic updates; the sparsification technique is applicable; or the problems are closely related to communications network issues. The models of parallel computation used in our studies are the Parallel Random Access Machine (PRAM) model and the practical interconnection network models such as meshes and hypercubes. ¶ Consider a communications network which can be represented by a graph G = (V;E), where V is a set of sites (processors), and E is a set of links which are used to connect the sites (processors). In some cases, we also assign weights and/or directions to the edges in E. Associated with this network, there are many problems such as (i) whether the network is k-edge (k-vertex) connected withfixed k; (ii) whether there are k-edge (k-vertex) disjoint paths between u and v for a pair of given vertices u and v after the network is dynamically updated by adding and/or deleting an edge etc; (iii) whether the sites in the network can communicate with each other when some sites and links fail; (iv) identifying the first k edges in the network whose deletion will result in the maximum increase in the routing cost in the resulting network for fixed k; (v) how to augment the network at optimal cost with a given feasible set of weighted edges such that the augmented network is k-edge (k-vertex) connected; (vi) how to route messages through the network efficiently. In this thesis we answer the problems mentioned above by presenting efficient parallel algorithms to solve them. As far as we know, most of the proposed algorithms are the first ones in the parallel setting. ¶ Even though most of the problems concerned in this thesis are related to communications networks, we also study the classic edge-coloring problem. The outstanding difficulty to solve this problem in parallel is that we do not yet know whether or not it is in NC. In this thesis we present an improved parallel algorithm for the problem which needs [bigcircle]([bigtriangleup][superscript 4.5]log [superscript 3] [bigtriangleup] log n + [bigtriangleup][superscript 4] log [superscript 4] n) time using [bigcircle](n[superscript 2][bigtriangleup] + n[bigtriangleup][superscript 3]) processors, where n is the number of vertices and [bigtriangleup] is the maximum vertex degree. Compared with a previously known result on the same model, we improved by an [bigcircle]([bigtriangleup][superscript 1.5]) factor in time. The non-trivial part is to reduce this problem to the edge-coloring update problem. We also generalize this problem to the approximate edge-coloring problem by giving a faster parallel algorithm for the latter case. ¶ Throughout the design and analysis of parallel graph algorithms, we also find a technique called the sparsification technique is very powerful in the design of efficient sequential and parallel algorithms on dense undirected graphs. We believe that this technique may be useful in its own right for guiding the design of efficient sequential and parallel algorithms for problems in other areas as well as in graph theory.

Resistive random access memory (RRAM) is a non-volatile memory technology based on resistive switching in a dielectric or semiconductor sandwiched between two different metals. Also known as memristors, these devices are potential candidates for a next-generation replacement for flash memory. In this thesis, bipolar resistive switching is reported for the first time in solution-deposited zinc-tin-oxide (ZTO). The impact of the compliance current on device operation, including the SET and RESET voltages, pre-SET, RESET and post-RESET currents, the resistance ratio between the low and high resistance states, retention, and the endurance, is investigated for an isolated Al dot/ZTO/Ir blanket device and for Al/ZTO/Pt crossbar RRAM devices. A gradual forming process is devised to improve device stability and performance. It is found that the device performance depends critically on the compliance current density that is used to limit the breakdown conduction during the SET operation. In addition, it was found that the conduction and switching mechanisms are consistent with the filament model of formation and rupture of conductive filaments. / Graduation date: 2012