<p>Like the rest of the society modern health care has to deal with the ever increasing information flow. Imaging modalities such as CT, MRI, US, SPECT and PET just keep producing more and more data. Especially CT and MRI and their 3D image stacks cause problems in terms of how to effectively handle these data sets. Usually a PACS is used to manage the information flow. Since a PACS often is implemented with a server-client setup, the management of these large data sets requires an efficient representation of medical image stacks that minimizes the amount of data transmitted between server and client and that efficiently supports the workflow of a practitioner.</p><p>In this thesis an efficient wavelet representation for large medical image stacks is proposed for the use in a PACS. The representation supports features such as lossless viewing, random access, ROI-viewing, scalable resolution, thick slab viewing and progressive transmission. All of these features are believed to be essential to form an efficient tool for navigation and reconstruction of an image stack.</p><p>The proposed wavelet representation has also been implemented and found to be better in terms of memory allocation and amount of data transmitted between server and client when compared to prior solutions. Performance tests of the implementation has also shown the proposed wavelet representation to have a good computational performance.</p>

The major limiting factor of DRAM access time is the low transconductance of the MOSFET's which have only limited current drive capability. The bipolar junction transistor(BJT) has a collector current amplification factor, ��, times base current and is limited mostly by the willingness to supply this base current. This collector current is much larger than the MOSFET drain current under similar conditions. The requirements for low power and low power densities results in lower power supply voltages which are also inconsistent with the threshold voltage variations in CMOS technology, as a consequence at least pulsed body bias or synchronous body bias will probably be utilized. Given that of the CMOS body will be driven or the CMOS gate and body connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing present CMOS process technology good results can be achieved with ultra low power using gate-body connected transistors and a current sense amplifier. / Graduation date: 1999

We consider a communication method, where the sender encodes n classical bits into 1 qubit and sends it to the receiver who performs a certain measurement depending on which of the initial bits must be recovered. This procedure is called (n,1,p) quantum random access code (QRAC) where p > 1/2 is its success probability. It is known that (2,1,0.85) and (3,1,0.79) QRACs (with no classical counterparts) exist and that (4,1,p) QRAC with p > 1/2 is not possible. We extend this model with shared randomness (SR) that is accessible to both parties. Then (n,1,p) QRAC with SR and p > 1/2 exists for any n > 0. We give an upper bound on its success probability (the known (2,1,0.85) and (3,1,0.79) QRACs match this upper bound). We discuss some particular constructions for several small values of n. We also study the classical counterpart of this model where n bits are encoded into 1 bit instead of 1 qubit and SR is used. We give an optimal construction for such codes and find their success probability exactly---it is less than in the quantum case. Interactive 3D quantum random access codes are available on-line at http://home.lanet.lv/~sd20008/racs

We consider a communication method, where the sender encodes n classical bits into 1 qubit and sends it to the receiver who performs a certain measurement depending on which of the initial bits must be recovered. This procedure is called (n,1,p) quantum random access code (QRAC) where p > 1/2 is its success probability. It is known that (2,1,0.85) and (3,1,0.79) QRACs (with no classical counterparts) exist and that (4,1,p) QRAC with p > 1/2 is not possible. We extend this model with shared randomness (SR) that is accessible to both parties. Then (n,1,p) QRAC with SR and p > 1/2 exists for any n > 0. We give an upper bound on its success probability (the known (2,1,0.85) and (3,1,0.79) QRACs match this upper bound). We discuss some particular constructions for several small values of n. We also study the classical counterpart of this model where n bits are encoded into 1 bit instead of 1 qubit and SR is used. We give an optimal construction for such codes and find their success probability exactly---it is less than in the quantum case. Interactive 3D quantum random access codes are available on-line at http://home.lanet.lv/~sd20008/racs

With the growth of multimedia services, it is essential to find new transmission schemes to support higher data rates in wireless networks. In this thesis, we study networks in which the Channel State Information (CSI) is only available at the destination. We focus on the analysis of three different network setups. For each case, we propose a transmission scheme which maximizes the average performance of the network. The first scenario, which is studied in Chapter 2, is a multi-hop network in which the channel gain of each hop changes quasi-statically from one transmission block to the other. Our main motivation to study this network is the recent advances in deployment of relay nodes in wireless networks (e.g., LTE-A and IEEE 802.16j). In this setup, we assume that all nodes are equipped with a single antenna and the relay nodes are not capable of data buffering over multiple transmission blocks. The proposed transmission scheme is based on infinite-layer coding at all nodes (the source and all relays) in conjunction with the Decode-and-Forward DF relaying. The objective is to maximize the statistical average of the received rate per channel use at the destination. To find the optimal parameters of this code, we first formulate the problem for a two-hop scenario and describe the code design algorithm for this two-hop setting. The optimality of infinite-layer DF coding is also discussed for the case of two-hop networks. The result is then generalized to multi-hop scenarios. To show the superiority of the proposed scheme, we also evaluate the achievable average received rate of infinite-layer DF coding and compare it with the performance of previously known schemes. The second scenario, studied in Chapter 3, is a single-hop network in which both nodes are equipped with multiple antennas, while the channel gain changes quasi-statically and the CSI is not available at the source. The main reason for selecting this network setup is to study the transmission of video signals (compressed using a scalable video coding technique, e.g., SVC H.264/AVC) over a Multiple-Input Multiple-Output (MIMO) link. In this setup, although scalable video coding techniques compress the video signal into layers with different importance (for video reconstruction), the source cannot adapt the number of transmitted layers to the capacity of the channel (since it does not have the CSI in each time slot). An alternative approach is to always transmit all layers of the compressed video signal, but use unequal error protection for different layers. With this motivation, we focus on the design of multilayer codes for a MIMO link in which the destination is only able to perform successive decoding (not joint-decoding). In this chapter, we introduce a design rule for construction of multilayer codes for MIMO systems. We also propose a algorithm that uses this design rule to determine the parameters of the multilayer code. The performance analysis of the proposed scheme is also discussed in this chapter. In the two previous scenarios, the ambiguity of the source regarding the channel state comes from the fact that the channel gains randomly change in each transmission block and there is no feedback to notify the source about the current state of the channel. Apart from these, there are some scenarios in which the channel state is unknown at the source, even though the channel gain is fixed and the source knows its value. The third scenario of this thesis presents an example of such network setups. More precisely, in Chapter 4, we study a multiple access network with K users and one Access Point (AP), where all nodes are equipped with multiple antennas. To access the network, each user independently decides whether to transmit in a time slot or not (no coordination between users). Considering a two-user random access network, we first derive the optimal value of network average Degrees of Freedom (DoF) (introduced in Section 4.1). Generalizing the result to multiuser networks, we propose an upper-bound for the network average DoF of a K-user random access network. This upper-bound is then analyzed for different network configurations to identify the network classes in which the proposed upper-bound is tight. It is also shown that simple single-stream data transmission achieves the upper-bound in most network settings. However, for some network configurations, we need to apply multi-stream data transmission in conjunction with interference alignment to reach the upper-bound. Some illustrative examples are also presented in this chapter.

Taiwan¡¦s DRAM has high technology, strong capital, and standardized products, but it still can not be escaped from economic fluctuations. With this impact, Taiwan¡¦s DRAM has faced the problem of cash flow imbalance; moreover, the problem is going from bad to worse. The study is based on the view of system dynamics and focuses on fixed assets and investment skills of the investment-cash flow, operating cash flow, and business cycles of Taiwan¡¦s DRAM. It considers the features of dynamic complex, including loop, time delay and nonlinear and constructs a system dynamics model. The model would apply key elements to suppose an investment strategy and then to mimic an investment situation. The aim of the study will figure out the suitable investment strategy to assistant Taiwan¡¦s DRAM making the most of its inputs. The study discovers: (1) the best investment strategy for 10 year is 5.0 (to invest three fixed asset sets); for 30 year is 6.0 (to invest manufacturing skills and one fixed asset set) and 7.0 (to invest manufacturing skills and two fixed asset sets), (2) the most effective element for investment strategy in the long run is to invest fixed asset sets rather than upgrading manufacturing skills, (3) to keep investing in semiconductor fabrications would endanger Taiwan¡¦s DRAM itself; hence the superior limit investment quantity for fixed assets are five to six sets,(4) the best investment timing for Taiwan¡¦s DRAM is the first two business cycle season, and (5)when Taiwan¡¦s DRAM faces economic downturn, the effective investment strategy for it is few. If Taiwan¡¦s DRAM doesn¡¦t change its industrial structure, it will face the high risk of loss.

In first part, the supercritical CO2 (SCCO2) fluid technology is employed to improve the device properties of ZnO TFT. The SCCO2 fluid exhibits liquid-like property, which has excellent transport ability. Furthermore, the SCCO2 fluid has gas-like and high-pressure properties to diffuse into the nanoscale structures without damage. Hence, the SCCO2 fluid can carry the H2O molecule effectively into the ZnO films at low temperature and passivate traps by H2O molecule at low temperature. The experimental results show that the on current, sub-threshold slope, and threshold voltage of the device were improved significantly. Next, the electrical degradation behaviors and mechanisms under drain bias stress of a-IGZO TFTs were investigated. A current crowding effect and an obvious capacitance-voltage stretch-out were observed after stress. During the drain-bias stress, the oxygen would be absorbed on the back channel near the drain region of IGZO film. Therefore, the carrier transport is impeded by the additional energy barrier near drain region induced by the adsorbed oxygen, which forms a depletion layer to generate the parasitism resistance. We also investigated the RRAM device based on IGZO film, and proposed the related physical mechanism models. The IGZO RRAM will be very promising for integration with IGZO TFTs for advanced system-on-panel display applications to be a transparent embedded system. In this part, the transparent RRAM device with ITO/IGZO/ITO structure was fabricated. The proposed device presents an excellent bipolar resistive switching characteristic and good reliability. The bipolar switching mechanism of our device is dominated by the formation and rupture of the oxygen vacancies in a conduction path. The influence of electrode material on resistance switching characteristic is investigated through Pt/IGZO/TiN and Ti/IGZO/TiN structure. As the bias applied on the Ti or TiN, the Ti or TiN electrode can play the role of oxygen reservoir to absorb/discharge oxygen ions. Therefore, the device presents a bipolar resistive switching characteristic. However, as the bias applied on the Pt electrode, the device presents a unipolar resistive switching characteristic. Because the Pt electrode can¡¦t store the oxygen ion, the device should use the joule heating mode to rupture the conduction path and present the unipolar resistive switching characteristic. Finally, the resistive switching properties of IGZO film deposited at different oxygen content were investigated, since the resistance switching behaviors are related to the formation and rupture of filaments composed of oxygen vacancies in the IGZO matrix. Experiment results show that the HRS current decreases when the oxygen partial pressure gradually increases. Based on the XPS analysis, these phenomena are related to the non-lattice oxygen concentration. With increasing oxygen ratio, the filaments will rupture completely through the abundant non-lattice oxygen inducing oxidation, which leads to HRS current decrease and an increase in the memory window.

With the progress of technology, large capacity and scalable are required for the future. Recent years, the physical limit is approached and a next-generation memory is needed in the future. In addition, non- volatile memory occupies more than 96% in the memory market, and RRAM has great advantages such as simple structure, high scalable, low operation voltage, high operation speed, high endurance and retention. That is the reason RRAM is the candidate in the next generation. In this experiment, multi-sputtering was used to deposit Zr:SiO 2 and Pt on TiN bottom electrode. The sandwich structure was metal/insulator/metal (MIM). With the different dielectric constant material, a different electrical field will be produced. And then I-V measurement and materials analysis were used to investigate the characteristic of the RRAM. At first, a forming process is required to the RRAM. The device was swept from negative to positive voltage and obtained the conduction mechanism from curve fitting. The different dielectric constant materials were used to fabricate the RRAM. High and low dielectric materials were HfO 2 and BN, respectively. The electric field distribution is centralized in low dielectric material so the electrons will drift to the direction of electric field. Hence, the Vset will be centralized and more stable. We also fabricated a Zr:SiO 2 /C:SiO 2 RRAM as an high K and low K material. The current fitting results that a hopping conduction occurs in low resistive state (LRS) and high resistive state (HRS). Both from Raman spectrum and FT-IR spectrum, a graphene oxide was existed in the C:SiO 2 thin film. While the filament was form, the tip of the filament will approach the graphene oxide because of the point effect. Hence, the resistance switching will happen in the grapheme oxide and set voltage will be more stable and lower the operated current. Next, an ICP treatment was used in order to "burn" the carbon in SiO 2 . The purpose is to make an extremely low K material and ignore the effect of the existence of carbon. From the FT-IR spectrum, the carbon signals were disappeared after the ICP oxygen plasma treatment. In the I-V fitting diagram, space char limit results in the high voltage region. The electrical field simulation was an auxiliary tool which shows a strong electrical field occurs in the extremely low K area. While the electrons flow through the conduction path, they will be confined in the porous area. The operation current will decrease because of the limited conduction area.

Sensory signals are represented and propagated as spiking activity in multiple neuronal populations to lead to cognitive or motor behavior in organisms. Neural processing underlying sensory-motor behavior is understood by uncovering the governing computational principles and the biophysical mechanisms that implement the principles. While these mechanisms have been studied extensively at the single-neuron and system levels, activity within neuronal networks significantly impact neural processing. For example, there are spatiotemporal interactions (neural correlations) between responses of neurons within populations that could potentially impact signal representation and propagation. Furthermore, the effects of associative plasticity are also expected to alter network activity and its propagation. The effects of plasticity on network activity cannot be predicted from individual neuronal responses due to the complex, non-linear interactions within neuronal networks. Thus examining neural correlations in network activity and the propagation of network activity, requires recording spiking activity from large, heterogeneous, populations of spatially distributed neurons simultaneously. Studies addressing the propagation of network activity have been limited to theoretical approaches. Empirical studies have been limited by the technical difficulties in recording from a large number of neurons simultaneously. To overcome this challenge we developed a novel technique, dithered random-access functional calcium imaging. This imaging technique records and extracts suprathreshold activity from a large number of neurons. This technique also has a high spike detection efficiency and millisecond temporal precision. We applied this technique to measure the propagation of activity and neural correlations in activity evoked by afferent, thalamocortical inputs in the recurrent cortical networks of the mouse barrel cortex. We found that the cortical activity evoked by novel (naïve), thalamocortical inputs showed limited propagation of activity and decrease in propagation of neural correlations (measured from neuronal pairs within each population) from L4 to L2/3 network of the responding column. However, associative cortical plasticity was induced from pairing thalamocortical inputs with intracortical inputs. This pairing resulted in increased propagation of activity. The pairing also modified the propagation of neural correlations. Our results suggest that synaptic plasticity in intracortical circuits contributes to the modified propagation of activity and neural correlations. The modified propagation of neural correlations could in turn contribute to behavioral performance in vivo following perceptual learning. / text

Main memory system performance is crucial for high performance microprocessors. Even though the peak bandwidth of main memory systems has increased through improvements in the microarchitecture of Dynamic Random Access Memory (DRAM) chips, conventional on-chip memory systems of microprocessors do not fully take advantage of it. This results in underutilization of the DRAM system, in other words, many idle cycles on the DRAM data bus. The main reason for this is that conventional on-chip memory system designs do not fully take into account important DRAM characteristics. Therefore, the high bandwidth of DRAM-based main memory systems cannot be realized and exploited by the processor. This dissertation identifies three major performance-related characteristics that can significantly affect DRAM performance and makes a case for DRAM characteristic-aware on-chip memory system design. We show that on-chip memory resource management policies (such as prefetching, buffer, and cache policies) that are aware of these DRAM characteristics can significantly enhance entire system performance. The key idea of the proposed mechanisms is to send out to the DRAM system useful memory requests that can be serviced with low latency or in parallel with other requests rather than requests that are serviced with high latency or serially. Our evaluations demonstrate that each of the proposed DRAM-aware mechanisms significantly improves performance by increasing DRAM utilization for useful data. We also show that when employed together, the performance benefit of each mechanism is achieved additively: they work synergistically and significantly improve the overall system performance of both single-core and Chip MultiProcessor (CMP) systems. / text